JPH10283780A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a power consumption and at the same time to stabilize an operation when the operation is started quickly by forming a current path against a ground by a level-pull-up circuit and by stepping down a voltage when an internal step-down voltage is increased. SOLUTION: An operation control signal EA is supplied to an internal step- down circuit VDLG 2 for forming essentially an internal step-down voltage to an internal step-down voltage generation circuit VDLG 1 for operation. A reference voltage VLR is compared with the internal step-down voltage VDL. When the VDL is lower than the VLR, the VDL level is increased by a MOSFET for supplying current. When the VDL exceeds the VLR, a level pull-up circuit LDW forms a current path between the VDL and the ground potential of a circuit and reduces the level. At this time, the operation time of the LDW is set to a specific short time, thus speeding up the stability of the VDL. An overshoot being generated by increasing the level is reduced temporarily. An under-shoot being generated at this time is suppressed to a low level since the LDG 2 is being operated, thus speeding up stability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a dynamic RAM (random access memory) for forming an operating voltage of a sense amplifier by an internal step-down voltage and operating an overdrive type sense amplifier. ), Which are effective technologies.

[0002]

2. Description of the Related Art A dynamic RAM is disclosed in "Nikkei Electronics" No. 641, pp. 99-214, published on July 31, 1995 by Nikkei McGraw-Hill. Further, only the necessary memory block in which the selected memory cell is provided is operated, the memory area to be operated is reduced as much as possible to achieve low power consumption, and the speed of the operation of selecting the sub-word line to which the memory cell is connected is increased. In order to achieve this, a split word line system has been proposed in which a plurality of sub-word lines are provided for connecting memory cells to a main word line.

[0003]

When writing a high level of a bit line to a dynamic memory cell comprising a storage capacitor and an address selection MOSFET, the word line selection level is set with respect to the bit line high level. It is necessary to use a high voltage that is boosted by the threshold voltage of the MOSFET. That is, the word line selection level is determined based on the high level of the bit line. With the miniaturization of elements due to the increase in storage capacity, the gate oxide film of the above-mentioned address selection MOSFET is also reduced in thickness, and the electric field strength of the gate oxide film becomes a problem. Therefore, it is conceivable to lower the power supply voltage supplied from the external terminal to form a constant-charged internal voltage and lower the word line selection level. However, in this case, the operating voltage of the sense amplifier that forms the high-level amplified signal of the bit line is reduced, and the operating speed is reduced.

In order to increase the operating speed of the sense amplifier, an overdrive method is considered in which the operating voltage is increased at the start of the operation of the sense amplifier and the rising of the high level of the bit line at the start of the amplification is accelerated. In such an overdrive system, the original operating voltage of the sense amplifier is raised by the overdrive voltage, so a circuit for extracting the same is required. Therefore, as a power supply circuit for generating an internal voltage, a level pull-up circuit for forming the internal voltage and a level pull-out circuit are required. At the start of the operation of the sense amplifier, the overdrive voltage is applied to these circuits and the internal voltage is reduced. Was found to be unstable.

An object of the present invention is to provide a semiconductor integrated circuit device which realizes stable operation while reducing power consumption of an internal step-down power supply circuit. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, the first operation control circuit operates on the power supply voltage supplied from the external terminal, receives the reference voltage and the internal step-down voltage, and performs the amplification operation based on the first operation control signal.
A level raising circuit configured to raise the internal step-down voltage by the current amplifying MOSFET when the internal step-down voltage is lower than a reference voltage, and a level boosting circuit that is supplied from the external terminal. A second differential circuit that operates at a power supply voltage, receives the reference voltage and the internal step-down voltage, and temporarily operates according to a second operation control signal at the start of operation of the level raising circuit according to the operation control signal; An internal step-down power supply circuit is configured by combining with a level extracting circuit that forms a current path for lowering the internal step-down voltage when the internal step-down voltage is increased with respect to the reference voltage.

[0007] The outline of another typical invention disclosed in the present application will be briefly described as follows. That is, it is configured by a differential circuit and a current amplification MOSFET that operate on the power supply voltage supplied from the external terminal, receive the first reference voltage and the internal step-down voltage, and perform an amplification operation based on an operation control signal. A level raising circuit for raising the internal step-down voltage by the current amplifying MOSFET when the internal step-down voltage is made lower than the first reference voltage, and operating with a power supply voltage supplied from an external terminal; A differential circuit which receives a second reference voltage and an internal step-down voltage raised by a very small voltage with respect to the second reference voltage, and performs an amplifying operation based on the operation control signal. When the internal step-down voltage is raised, the internal step-down power supply circuit is configured by combining with a level extraction circuit that forms a current path for lowering the internal step-down voltage.

[0008]

FIG. 1 is a block diagram showing one embodiment of an internal step-down power supply circuit according to the present invention. Each circuit block shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique together with other circuits on which the circuit block is mounted.

The internal step-down power supply circuit of this embodiment is configured by combining three circuit blocks. The internal step-down voltage generation circuit VLDG1 receives the power supply voltage VDD supplied from the external terminal and operates steadily to form the internal step-down voltage VDL that matches the reference voltage VLR. In order to reduce current consumption when the semiconductor integrated circuit device on which it is mounted is in a non-operating (standby) state, the internal step-down voltage generating circuit VDLG1 has a leak in an internal circuit which operates upon receiving the internal step-down voltage VDL. It is made to have only a small current supply capacity enough to supplement the current. That is, the internal step-down voltage generation circuit VDLG1 performs only an operation such that the internal step-down voltage VDL maintains a desired level when the internal circuit is not operating.

[0010] An internal step-down voltage generating circuit VLLG2 for forming a substantial internal step-down voltage is provided for the internal step-down voltage generating circuit VLLG1. The internal step-down voltage generation circuit VDLG2 has a function as a so-called level raising circuit, is brought into an operation state by a first operation control signal EA, and receives the reference voltage VLR and the internal step-down voltage VD.
And the internal step-down voltage VDL is compared with the reference voltage VL.
Output MOSFET for current supply when lower than R
Are in the operating state, and the level of the internal step-down voltage VDL is raised. In terms of circuit form, the internal step-down voltage generation circuit VDLG2 is constituted by a voltage follower circuit using a differential amplifier circuit, but its function is used only in the direction of raising the high level to reduce power consumption. .

The internal step-down voltage generation circuit VDLG2 as the level raising circuit is set to an operation state by an operation control signal EA, and when it becomes larger than the reference voltage VDL, it is returned to the reference voltage VLR. A level extraction circuit LDW is provided. This circuit compares the reference voltage VLR with the internal step-down voltage VDL and forms a current path between the internal step-down voltage VDL and the ground potential of the circuit when the internal step-down voltage VDL becomes higher than the reference voltage VLR. Then, it operates to lower the level.

In this embodiment, when the internal step-down voltage generating circuit VDLG2 as the level raising circuit and the level pulling circuit LDW are operated simultaneously, the internal step-down voltage V is obtained by the level raising operation and the level pulling operation.
Since it takes time for the DL to stabilize, the operation period of the level extraction circuit LDW is set to only a short fixed time.

FIG. 2 is a timing chart for explaining the operation of the internal step-down power supply circuit. Assuming that an internal circuit operated by the internal step-down voltage VDL is activated by the control signal / SAE, the first control signal EA is changed from a low level to a high level by the signal / SAE, and the internal level as a level raising circuit is increased. The step-down voltage generation circuit VLDG2 is set to an operation state. The above signal / SA
The internal circuit operates by the low level of E and the internal voltage VD
When L decreases, the internal step-down voltage generation circuit VLDG2
Senses this and performs a level raising operation. At this time, an overshoot occurs in internal step-down voltage VDL. This overshoot is detected by the level extraction circuit LDW activated by the second operation control signal, and is lowered once the current path for level extraction is formed.

On the contrary, an undershoot occurs due to the operation of the level pull-out circuit LDW. This undershoot is relatively small because the internal step-down voltage generating circuit VLDG2 as the level pull-up circuit is in the operating state. The overshoot that occurs during operation is also reduced. Since the level extraction circuit LDW is operated only for a relatively short period by the second control signal EB,
Since the tension with the second internal step-down voltage generation circuit VDLG2 as the level raising circuit does not continue, it is possible to quickly settle down to the stable voltage VDL by the operation current or the like in the internal circuit.

FIG. 3 is a block diagram showing another embodiment of the internal step-down power supply circuit according to the present invention. Each circuit block shown in the figure is formed on a single semiconductor substrate such as single-crystal silicon by a well-known semiconductor integrated circuit manufacturing technique together with other circuits on which the circuit blocks are mounted as described above.

The internal step-down power supply circuit of this embodiment is configured by combining three circuit blocks similar to the above. The internal step-down voltage generation circuit VDLG1 performs only an operation for maintaining the internal step-down voltage VDL at a desired level when the internal circuit is in a non-operation state, as described above.
The internal step-down voltage generating circuit VDLG2 has a function as a so-called level raising circuit that forms a substantial internal step-down voltage, and is brought into an operation state by a first operation control signal EA.

In this embodiment, the control of the level pull-out circuit LDW provided for the internal step-down voltage generating circuit VDLG2 as the level pull-up circuit is not performed by the operation control signal as described above, but by offsetting the reference voltage. Substantial operation control is performed by having the information. That is, the level extraction circuit L
The reference voltage supplied to the DW is ΔV
The reference voltage VLR is increased by V + ΔV.

FIG. 4 is a timing chart for explaining the operation of the internal step-down power supply circuit. Assuming that an internal circuit operated by the internal step-down voltage VDL is activated by the control signal / SAE, the first control signal EA is changed from a low level to a high level by the signal / SAE, and the internal level as a level raising circuit is increased. The step-down voltage generation circuit VLDG2 is set to an operation state. The above signal / SA
The internal circuit operates by the low level of E and the internal voltage VD
When L decreases, the internal step-down voltage generation circuit VLDG2
Senses this and performs a level raising operation. At this time, an overshoot occurs in internal step-down voltage VDL. This overshoot is detected by the level extracting circuit LDW when the voltage exceeds the reference voltage VLR + ΔV offset by ΔV as described above, and the level is lowered once the level extracting current path is formed. Is performed, and the operation is VLR + Δ
It stops when it reaches V.

The undershoot generated by the operation of the level extraction circuit LDW is opposite to the undershoot ΔV as described above.
And the internal step-down voltage generating circuit VLDG2 as the level raising circuit is in an operating state, so that it is relatively small, and the overshoot generated in the reverse direction is also small. Then, the internal step-down voltage VDL becomes VLR and V
During the period of LR + ΔV, since both of the circuits do not operate, the tension with the second internal step-down voltage generating circuit VDLG2 as the level raising circuit is weakened and the stable voltage VDL can be quickly settled.

FIG. 5 is a circuit diagram showing one embodiment of the internal step-down voltage generating circuit and the level extracting circuit.
In the figure, a P-channel type MOSFET is a MOS
An arrow is attached to a channel portion like the FET Q22 to distinguish it from an N-channel MOSFET. FIG. 1A shows an internal step-down voltage generating circuit, and FIG. 1B shows a level extracting circuit.

In FIG. 2A, an N-channel type MO
SFETs Q20 and Q21 are differentially configured by having their sources connected together. These MOSFET Q2
P-channel MOSFETs Q22 and Q23 in the form of a current mirror are provided between the drains of 0 and Q21 and the power supply voltage VDD supplied from the external terminal. That is, the gate of the MOSFET Q22 is connected to the commonly connected gate and drain of the MOSFET Q23. An N-channel MOS through which an operation current flows is provided between the sources of the differential MOSFETs Q20 and Q21 and the ground potential of the circuit.
An FET Q24 is provided. The operation control signal EA is supplied to the gate of the MOSFET Q24 when the differential circuit forms the internal step-down voltage generation circuit VDLG2 as the level raising circuit, and the gate of the MOSFET Q24 is supplied with a predetermined voltage when forming the internal step-down voltage generation circuit VLG1. A bias voltage is constantly supplied to perform a constant current operation.

The reference voltage VLR is supplied to the gate of the differential MOSFET Q20, and the internal step-down voltage VDL described below is supplied to the gate of the differential MOSFET Q21. The drain output of the MOSFET Q20 is supplied to the gate of a P-channel output MOSFET Q25. The source of this MOSFET Q25 is the power supply voltage V
DD is applied to form an internal step-down voltage VDL from the drain. And, to the drain of the MOSFET Q25,
N-channel MOSFET Q26 acting as a load
Is provided. The operation of the MOSFET Q26 is controlled by the operation control signal EA, and the MOSFET Q2 is controlled to reduce current consumption during operation.
5 so that only a small current is absorbed so as to absorb the leak current flowing through it.

That is, the internal step-down voltage generating circuit VDL
G2 is a voltage follower circuit in circuit form by the internal step-down voltage VDL as an output voltage being 100% negatively fed back to the gate of the differential MOSFET Q21, while the P-channel MOSFET Q25 has a desired current supply. On the other hand, although the MOSFET Q26 has only a small current in order to reduce the DC current, the MOSFET Q26 has almost no level extracting function, and therefore only operates as a level raising circuit.

In FIG. 1B, an N-channel type MO
The SFETs Q30 and Q31 are in a differential configuration with their sources commonly connected. These MOSFET Q3
Between the drains of 0 and Q31 and the power supply voltage VDD supplied from the external terminal, P-channel MOSFETs Q32 and Q33 in the form of a current mirror are provided. That is, the gate of the MOSFET Q32 is connected to the commonly connected gate and drain of the MOSFET Q33. An N-channel MOS through which an operation current flows is provided between the sources of the differential MOSFETs Q30 and Q31 and the ground potential of the circuit.
An FET Q34 is provided. When the MOSFET Q34 is used as in the embodiment of FIG.
When the operation control signal EB is applied and used as in the embodiment of FIG. 3, the operation control signal EA is applied.

The gate of the differential MOSFET Q31 is supplied with the internal step-down voltage VDL. On the other hand, the reference voltage VLR is supplied to the gate of the differential MOSFET Q30 when it is used as in the embodiment of FIG. 1, and VLR + ΔV is applied as the reference voltage when it is used as in the embodiment of FIG. You. This differential circuit operates as a voltage comparison circuit. That is, the reference voltage VLR (or VLR + ΔV) is compared with the internal step-down voltage VDL, and the reference voltage VLR (or VLR + ΔV) is compared.
V) when the internal step-down voltage VDL is higher than V
Since the current flowing through the FET Q31 relatively increases and is supplied to the drain of the MOSFET Q30 via the current mirror circuit, a high-level voltage signal is formed by the difference between the relatively reduced drain current of the MOSFET Q30. . Conversely, the reference voltage VLR (or VLR + Δ
When the internal step-down voltage VDL becomes lower than V
Since the current flowing through the FET Q31 relatively decreases and is supplied to the drain of the MOSFET Q30 via the current mirror circuit, a low-level voltage signal is formed by the relatively increased difference between the drain currents of the MOSFET Q30.

The level extracting circuit uses the internal step-down voltage VDL
And two N-channel MOSFETs Q39 provided between the CMOS inverter circuit and the ground potential of the circuit. That is, the drain output of the MOSFET Q30 is supplied to a CMOS inverter circuit composed of a P-channel MOSFET Q35 and an N-channel MOSFET Q36, where it is amplified. This amplified signal is
P-channel MOSFET Q37 and N-channel M
The N-channel MOSFET Q39 is supplied from the OSFET Q38 to the CMOS inverter circuit, and is provided between the output of the CMOS inverter circuit and the ground potential of the circuit. The power supply voltage VDD is applied to the gate of the MOSFET Q39 to operate as a resistance element.

When the drain output of the MOSFET Q30 of the differential circuit goes high, the CMOS inverter circuits (Q35 and Q36) form an amplified low-level output signal. As a result, the P-channel MOSFET Q37 of the CMOS inverter circuit is turned on, and a direct current path is formed with the MOSFET Q39 to form a current path for drawing out the internal step-down voltage VDL to a low level. If the differential circuit M
If the drain output of OSFET Q30 is at low level, the CMOS inverter circuit (Q35 and Q36)
Form an amplified high-level output signal. Thereby, the P-channel type MO of the CMOS inverter circuit is provided.
The SFET Q37 is turned off, and the MOSFET Q39
No direct current path is formed between them.

FIG. 6 is a circuit diagram showing one embodiment of the voltage generating circuit for forming the reference voltage VLR. The voltage generation circuit includes a reference voltage generation circuit Vr-G and a level conversion circuit LVC. The reference constant voltage Vr formed by the reference voltage generation circuit Vr-G is a relatively small voltage value such as about 1.2 V corresponding to a silicon band gap, and is a voltage required as an internal power supply of the semiconductor integrated circuit device. Are different. Therefore, the level conversion circuit LVC converts the reference constant voltage Vr into a required constant voltage VLR.
It is.

The reference voltage generating circuit Vr-G changes the emitter area ratio between the PNP transistors T1 and T2, and changes the emitter current density so that the same current IR flows therethrough. Thereby, a constant voltage corresponding to the silicon band gap such as ΔVBE is formed. In order to allow the same current IR to flow through the transistors T1 and T2, P-channel MOSFETs QP10, QP11,
N-channel MOSFETs QN10 and QN11 are provided. That is, the emitter potential of the transistor T1 is set to M
OSFET QN10 source-gate, MOSFET Q
The voltage is applied to one end of a resistor R3 via the gate-source of N11, and the other end of the resistor R3 is connected to the emitter of the transistor T2. Thus, the constant voltage ΔVBE corresponding to the silicon band gap is applied to the resistor R3, and the constant current IR flows.

This constant current IR is based on the MOSFET QN
11, P-channel MOSFETs QP10 to QP
Current mirror circuit composed of P12 and N-channel type MOS
The power is supplied to the emitter of the transistor T1 via the FET QN10. Also, a P-channel MOSFET QP12
Through the resistor R4 to obtain a constant voltage Vr. At the other end of the resistor R4, a transistor T3 having the same size as the transistor T2 is provided to perform temperature compensation. The output node of the reference voltage Vr
A capacitor C is provided to stabilize the voltage Vr.

Although not particularly limited, the bipolar transistor has an N-type well region for forming a P-channel MOSFET as a collector and an emitter for forming the P-channel MOSFET as a base. If P-type source / drain regions are used, they can be easily formed using the CMOS circuit technology as it is.

The reference constant voltage Vr is an N-channel type M which has a gate and a drain connected and is in the form of a diode.
It is supplied to the source of OSFET QN3. This MOSF
The gate of ETQN3 is commonly connected to the gate of N-channel MOSFET QN4 of the same size. A resistor R1 is provided between the source of the MOSFET QN4 and the ground potential point of the circuit as a reference potential point.

The current generated by the resistor R1 is equal to the M
P-channel type MOSFET having a gate and a drain connected to each other through OSFET QN4 to form a diode.
It is made to flow to QP3. This MOSFET QP3
In contrast, P-channel MOSFETs QP1, QP2 and QP4 are in a current mirror form. These P-channel MOSFETs QP1 to QP4 are formed with the same element size so that the same current flows.

The current formed by the P-channel MOSFET QP2 is supplied to the drain of the MOSFET QN3. The source of this MOSFET QN3
N-channel MOSFETs QN1 and QN2 receiving the current formed by P-channel MOSFET QP1
Is provided. As a result, the drain current and the source current of the N-channel MOSFET QN3 are set to the same current value as the current formed by the resistor R1.

A resistor R2 is provided between the drain of the N-channel MOSFET QP4 and the ground potential of the circuit. This resistor R2 is set to have a desired ratio with respect to the resistor R1. That is, the same constant current flows through the reference constant voltage Vr supplied to the source of the MOSFET QN3, and becomes equal to the source potential of the MOSFET QN4 having the same element size. Therefore, the resistance R1 has Vr
A constant current such as / R1 flows. The constant current equal to this constant current is equal to the P-channel MOSFET QP4.
Through the resistor R2, the output voltage VLR becomes
(Vr / R1) × R2.

Therefore, the ratio of the resistors R1 and R2 (R2 /
The reference constant voltage Vr is increased in proportion to the ratio of R1), and an output voltage VLR having a desired voltage value can be obtained. At this time, the resistance formed by the semiconductor integrated circuit has a relatively large variation in the resistance value, but the relative ratio can be formed with high accuracy.
R can be highly stabilized corresponding to the reference constant voltage Vr. In the level conversion circuit of this embodiment, since the gain is not determined by feedback, it is possible to operate with high stability even if the current flowing through the resistor R1 is set small. When forming the ΔV, a resistor R2 ′ may be provided corresponding to the ΔV.

FIG. 7 is a schematic layout diagram of one embodiment of a dynamic RAM on which the internal step-down power supply circuit according to the present invention is mounted. In the figure, of the circuit blocks constituting the dynamic RAM, a portion related to the present invention is shown so as to be understood. It is formed on one semiconductor substrate.

In this embodiment, although not particularly limited, the memory array is divided into four as a whole. Two memory arrays are divided into two on the left and right sides in the longitudinal direction of the semiconductor chip, and an address input circuit, a data input / output circuit, an input / output interface circuit including a bonding pad row, and the like are provided in the central portion 14. Column decoder regions 13 are arranged in portions of both sides of the central portion 14 in contact with the memory array.

As described above, in each of the four memory arrays divided into two on the left and right sides and two on the upper and lower sides with respect to the longitudinal direction of the semiconductor chip, the main row decoder is disposed at the upper and lower central portions in the longitudinal direction. An area 11 is provided. Main word driver regions are formed above and below the main row decoder, and drive the main word lines of the memory array divided vertically.
In the center part which divides the longitudinal direction of the semiconductor chip into two,
An internal voltage generation circuit 9 is provided. The internal voltage generation circuit 9 includes a booster circuit and a substrate voltage generation circuit, which will be described later, in addition to the internal step-down power supply circuit.

The above memory cell array (subarray) 15
Are formed so as to be surrounded by the sense amplifier region 16 and the sub-word driver region 17 with the memory cell array 15 interposed therebetween, as shown in the enlarged view. An intersection between the sense amplifier region and the sub-word driver region is an intersection region (cross area) 18. The sense amplifiers provided in the sense amplifier region 16 are configured by a shared sense method, and except for the sense amplifiers arranged at both ends of the memory cell array, complementary bit lines are provided on the left and right around the sense amplifier. Selectively connected to the complementary bit lines of the memory cell array.

As described above, the memory arrays divided into four on the left and right sides in the longitudinal direction of the semiconductor chip are arranged in groups of two. As described above, the two memory arrays arranged in groups of two each have the main word driver 11 arranged at the center thereof. The main word driver 11 is provided corresponding to the two memory arrays that are divided up and down around the main word driver 11. The main word driver 11 generates a selection signal of a main word line extended so as to penetrate the one memory array. The main word driver 11 is also provided with a sub-word selection driver, which extends in parallel with the main word line to form a sub-word selection line selection signal as described later.

Although not shown, one memory cell array (sub-array) 15 shown as an enlarged view has 256 sub-word lines and 256 pairs of complementary bit lines (or data lines) orthogonal thereto. In one memory array, 16 memory cell arrays (sub-arrays) 15 are provided in the word bit line direction. Therefore, about 4K sub-word lines are provided as a whole, and 8 sub-word lines are provided in the word line direction. The bit line is about 2
K are provided. Since eight such memory arrays are provided in total, a large storage capacity such as 8 × 2K × 4K = 64 Mbits is provided.

The one memory array is divided into eight in the main word line direction. A sub-word driver (sub-word line driving circuit) 17 is provided for each of the divided memory cell arrays 15. The sub-word driver 17 is divided into の 長 of the length of the main word line, and forms a sub-word line selection signal extending in parallel with the length. In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. Are arranged four sub-word lines. In order to select one sub-word line from among the sub-word lines divided into eight in the main word line direction and four in the complementary bit line direction, a sub-word selection driver is used. Be placed. This sub-word selection driver is extended in the arrangement direction of the sub-word drivers.
A selection signal for selecting one of the sub-word selection lines is formed.

Focusing on the one memory array, 1
One sub-word selection line is selected in a sub-word driver corresponding to one memory cell array including a memory cell to be selected among eight memory cell arrays allocated to one main word line, resulting in one main word One sub-word line is selected from 8 × 4 = 32 sub-word lines belonging to the line. As described above, 2K (2048) memory cells are provided in the main word line direction.
/ 8 = 256 memory cells are connected.
Although not particularly limited, in a refresh operation (for example, a self-refresh mode), eight sub-word lines corresponding to one main word line are set to a selected state.

As described above, one memory array has a storage capacity of 4K bits in the complementary bit line direction. However, if as many as 4K memory cells are connected to one complementary bit line, the parasitic capacitance of the complementary bit line increases, and a signal level that is read out cannot be obtained due to the capacitance ratio with a fine information storage capacitor. To
It is also divided into 16 in the complementary bit line direction. That is,
The complementary bit line is divided into 16 by the sense amplifier 16 indicated by a thick black line. Although not particularly limited, the sense amplifiers 16 are configured by a shared sense system, and are provided at both ends of the memory array.
Except for the above, complementary bit lines are provided on the left and right with respect to the sense amplifier 16, and are selectively connected to one of the left and right complementary bit lines.

FIG. 8 is a schematic layout diagram for explaining a dynamic RAM according to the present invention. The figure shows a schematic layout of the entire memory chip,
The layout of one memory array divided into eight is shown. This figure illustrates the embodiment of FIG. 7 from another point of view. That is, as in FIG. 7, the memory chip is located at right and left and up and down with respect to the longitudinal direction (word line direction).
Each memory array is divided into four parts, and a plurality of bonding pads and peripheral circuits (Bonding Pad & peripheral Circuit) are provided in the central part in the longitudinal direction.

Each of the two memory arrays has a storage capacity of about 8 Mbits, and one of the two memory arrays is divided into eight in the word line direction as shown in an enlarged manner. A sub-array divided into 16 in the bit line direction is provided. On both sides of the sub-array in the bit line direction, sense amplifiers (Sence Amplifiers) are arranged in the bit line direction. A sub-word driver (Sub-Wo) is provided on both sides of the sub-array in the word line direction.
rd Driver) is placed.

In one array, a total of 4096 word lines and 2048 pairs of complementary bit lines are provided.
As a result, the storage capacity is about 8 Mbits in total. As described above, 4096 word lines are divided into 16 sub-arrays and arranged, so that one sub-array is provided with 256 word lines (sub-word lines). In addition, since 2048 pairs of complementary bit lines are divided into eight sub-arrays as described above, one sub-array is provided with 256 pairs of complementary bit lines.

At the center of the two arrays, a main row decoder is provided. In other words, on the left side of the array shown in the figure, an array control circuit and a main word driver correspond to the main row decoder provided in common with the array provided on the right side. Is provided. The array control circuit includes a driver for driving the first sub-word selection line. A main word line extending so as to penetrate the eight divided sub-arrays is arranged in the array. The main word driver drives the main word line. Like the main word line, the first sub-word selection line is extended so as to pass through the eight divided sub-arrays. Above the array, a Y decoder (YDecoder) and a Y select line driver (YS
driver).

FIG. 9 is a main part circuit diagram of one embodiment of the sense amplifier section of the dynamic RAM and its peripheral circuits. FIG. 1 exemplarily shows a sense amplifier arranged between two sub-arrays and a circuit related thereto. The well region where each element is formed is shown by a dotted line, and the bias voltage applied thereto is also shown.

As the dynamic memory cell, one provided between the sub-word line SWL provided in the one sub-array and one of the complementary bit lines BL and / BL is exemplarily shown as a representative. ing. The dynamic memory cell includes an address selection MOSFET Qm and a storage capacitor Cs. Address selection MOS
The gate of the FET Qm is connected to the sub-word line SWL, the drain of the MOSFET Qm is connected to the bit line BL, and the storage capacitor Cs is connected to the source.
The other electrode of the storage capacitor Cs is shared and receives a plate voltage. The selection level of the sub-word line SWL is a high voltage VPP higher than the high level of the bit line by the threshold voltage of the address selection MOSFET Qm.

When the sense amplifier is operated at the internal step-down voltage VDL formed by the internal step-down power supply circuit, the high level amplified by the sense amplifier and given to the bit line is a level corresponding to the internal voltage VDL. To be. Therefore, the high voltage VPP corresponding to the word line selection level is set to VDL + Vth. A pair of complementary bit lines BL and / BL of the sub-array provided on the left side of the sense amplifier are arranged in parallel as shown in FIG.
In order to balance the capacitance of the bit lines and the like, they are appropriately crossed as needed. Such complementary bit lines BL and / BL
Is connected to the input / output node of the unit circuit of the sense amplifier by shared switch MOSFETs Q1 and Q2.

The unit circuit of the sense amplifier is composed of N-channel type amplifying MOSFETs Q5, Q6 and P-channel type amplifying MOSFETs Q7, Q8, whose gates and drains are cross-connected to form a latch. The sources of the N-channel MOSFETs Q5 and Q6 are connected to a common source line CSN. The sources of the P-channel MOSFETs Q7 and Q8 are connected to a common source line CS.
Connected to P. Each of the common source lines CSN and CSP is provided with a power switch MOSFET. Although not particularly limited, an N-channel type amplification MOS
Common source line C to which the sources of FETs Q5 and Q6 are connected
SN is the N provided in the cross area between the A and B sides.
Channel type power switch MOSFETs Q12 and Q
13 provides an operating voltage corresponding to the ground potential.

Although not particularly limited, the common source line CSP to which the sources of the P-channel type amplification MOSFETs Q7 and Q8 are connected has a P-channel type power MOSFET Q15 for overdrive and the internal voltage V
N-channel type power MOSFET Q for supplying DL
16 are provided. The overdrive voltage is
N-channel type M in which boosted voltage VPP is supplied to the gate
Clamp voltage VDD formed by OSFET Q14
CLP is used. A power supply voltage VDD supplied from an external terminal is supplied to a drain of the MOSFET Q14, and the MOSFET Q14 is operated as a source follower output circuit.
The clamp voltage VDDCLP lowered by the threshold voltage of the OSFET Q14 is formed.

Although not particularly limited, the boosted voltage VPP
Is controlled by using the reference voltage to operate the charge pump circuit, and is set to a stabilized high voltage such as 3.8V. The threshold voltage of the MOSFET Q14 is formed at a low threshold voltage lower than the address selection MOSFET Qm of the memory cell, and the clamp voltage VD
DCLP is brought to a stabilized constant voltage such as about 2.9V. The MOSFET Q26 is a MOSFET forming a leak current path, and does not flow a minute current of about 1 μA. This prevents the VDDCLP from excessively rising due to the standby state (non-operating state) for a long period of time or the bump of the power supply voltage VDD, and the amplifying MOS to which the voltage VDDCLP at the time of such excessive increase is applied.
The operation delay due to the back bias effect of the FETs Q7 and Q8 is prevented.

In this embodiment, noting that the overdrive voltage of the sense amplifier is formed by the clamp voltage VDDCLP as described above, a P-channel type power MOSFET Q15 for supplying the voltage,
P channel type amplification MOSFET Q of sense amplifier
7, Q8 are formed in the same N-type well region NWELL as shown by the dotted line in the same figure, and the clamp voltage VDDCLP is supplied as the bias voltage. Then, a P-channel type amplifier M of the sense amplifier
The power MOSFET Q16 for applying the original operating voltage VDL to the common source line CSP of the OSFETs Q7 and Q8 has N
MOSF for overdrive as the channel type
It is formed electrically separated from the ETQ 14.

The N-channel type power MOSFET
Sense amplifier activation signal S supplied to the gate of Q16
AP2 is an overdrive activation signal / S supplied to the gate of the P-channel MOSFET Q15.
The signal has a phase opposite to that of AP1, and although not particularly limited, a high level thereof is a signal corresponding to the power supply voltage VDD. That is, as described above, VDDCLP is approximately +2.9.
V, which is the minimum allowable voltage VDDmi of the power supply voltage VDD.
Since n is about 3.0 V, the P-channel MO
The SFET Q15 can be turned off, and a voltage corresponding to the internal voltage VDL can be output from the source side by using the N-channel MOSFET Q16 having a low threshold voltage.

An equalizing MOSF for short-circuiting a complementary bit line is provided at the input / output node of the unit circuit of the sense amplifier.
A precharge circuit including ETQ11 and switch MOSFETs Q9 and Q10 for supplying a half precharge voltage to a complementary bit line is provided. These MOSFETs
The gates of Q9 to Q11 share the precharge signal BL
EQ is supplied. The driver circuit for forming the precharge signal BLEQ is provided with an N-channel MOSFET Q18 in the cross area to speed up the fall. That is, in order to advance the timing of selecting a word line by the start of memory access, the N-channel MOSFET Q18 provided in each cross area is turned on to set the MOSFE which constitutes the precharge circuit.
TQ9 to Q11 are switched to the off state at high speed.

On the other hand, a P-channel MOSFET Q17 for forming a signal for starting a precharge operation
Are provided not in the individual cross areas as described above, but in the Y decoder & YS driver section. That is, the precharge operation is started by the end of the memory access, but since the operation has time margin, it is not necessary to make the rising of the signal BLEQ fast. As a result, the P-channel MOSFET provided in one cross area is only the power MOSFET Q15 for overdrive, and the P-channel MOSFET provided in the other cross area is a switch circuit IOSW of an input / output line described below. , And the MOSFETs constituting a precharge circuit for precharging the common input line MIO to the internal voltage VDL. The above-mentioned VDDCLP is provided in these N-type well regions.
And a bias voltage such as VDL are applied, so that one type of N-type well region is formed, and no parasitic thyristor element is formed.

The unit circuit of the sense amplifier is connected to similar complementary bit lines BL and / BL of the right sub-array via shared switch MOSFETs Q3 and Q4. The switch MOSFETs Q12 and Q13 constitute a column switch circuit, and upon receiving the selection signal YS, connect the input / output node of the unit circuit of the sense amplifier to the sub-common input / output line LIO. For example, when the sub word line SWL of the left sub array is selected, the right shared switch MOSFETs Q3 and Q4 of the sense amplifier are selected.
Are turned off. As a result, the input / output node of the sense amplifier is connected to the left-side complementary bit lines BL and / BL, amplifies the minute signal of the memory cell connected to the selected sub-word line SWL, and passes through the column switch circuit. It is transmitted to the sub common input / output line LIO. The sub common input / output line LIO is connected to the N provided in the cross area.
It is connected to an input / output line MIO connected to the input terminal of the main amplifier via a switch circuit IOSW composed of channel type MOSFETs Q19 and Q20 and the P-channel type MOSFETs Q24 and Q25.

The sub-word line drive circuit SWD includes a P-channel MOSFET Q21 formed in the deep N-type well region DWELL (VPP), one of which is exemplarily shown as a representative. D
The P-type well region PWELL (V
N-channel MOSFET Q22 formed in BB)
And Q23. Inverter circuit N1
Although it is not particularly limited, it constitutes the sub-word select line driving circuit FXD as shown in FIG. 3 and is provided in the cross area as described above. The sub-array address selection MOSFET Qm is also
LL formed in the P-type well region PWELL (VB
B).

FIG. 10 is a main block diagram for explaining the relationship between the main word lines and the sub word lines of the sub array. This figure mainly describes the circuit operation, and omits the actual geometric arrangement of the sub-word selection lines and collectively shows the sub-word selection lines FX0B to 7B. In the figure, two main word lines MWL are shown in order to explain a sub word line selecting operation.
0 and MWL1 are shown as representatives. These main word lines MWL0 are connected to a main word driver MWD0.
Is selected by The other main word line MWL1 is similarly selected by a main word driver similar to the above.

The one main word line MWL0 has:
Eight sets of sub-word lines are provided in the extending direction. FIG. 2 exemplarily shows two sets of the sub-word lines as representatives. The sub word line is even 0 to
A total of eight sub-word lines 6 and odd numbers 1 to 7 are alternately arranged in one sub-array. Except for even numbers 0 to 6 adjacent to the main word driver and odd numbers 1 to 7 arranged on the far end side (opposite side of the word driver) of the main word line,
The sub-word driver arranged between the sub-arrays drives the sub-word lines of the left and right sub-arrays centered on the sub-word driver.

As a result, although the sub-array is divided into eight as described above, the sub-word lines corresponding to the two sub-arrays are simultaneously selected by the sub-word driver SWD substantially as described above. The sub-array is divided into four sets. As described above, the sub word line SWL is divided into even numbers 0 to 6 and even numbers 1 to 7,
Sub word drivers S are provided on both sides of each memory block.
In the configuration in which the WDs are arranged, the substantial pitch of the sub-word lines SWL arranged at high density in accordance with the arrangement of the memory cells can be relaxed twice in the sub-word driver SWD.
The sub-word driver SWD and the sub-word line SWL can be efficiently laid out on a semiconductor chip.

In this embodiment, the sub-word driver SWD supplies a selection signal from the main word line MWL to four sub-word lines 0 to 6 (1 to 7) in common. A sub-word select line FXB for selecting one sub-word line from the four sub-word lines is provided. The sub-word selection lines are composed of eight lines FXB0 to FXB7, of which even-numbered FXB0 to FXB6 are supplied to the even-numbered sub-word drivers 0 to 6, and odd-numbered FXB1 to FXB7 are odd-numbered sub-word drivers 1 to 7 of the odd-numbered columns. Supplied to

The sub-word selection lines FXB0 to FXB7 are
On the sub-array, the second metal wiring layer M2
And a second sub-word select line extending in parallel with the main word lines MWL0 to MWLn also formed by the second metal wiring layer M2, and a second sub-word extending in a direction orthogonal thereto. Consists of a selection line.
Although not particularly limited, the second sub-word selection line is
A third metal wiring layer M3 is provided to cross the main word line MWL.

The sub-word driver SWD has a main word line M, one of which is illustratively shown.
The input terminal is connected to WL, and the sub-word line S is connected to the output terminal.
A first CM including a P-channel MOSFET Q21 and an N-channel MOSFET Q22 to which WL is connected.
An OS inverter circuit and a switch MOSFET Q23 provided between the sub-word line SWL and the ground potential of the circuit and receiving the sub-word selection signal FXB. In order to connect the gate of this switch MOSFET Q23, a total of eight sub-word selection lines FX and FXB are arranged along a sub-word driver row consisting of 0, 2, 4, and 6, but in FIG. It is represented by one line.

A second CMOS inverter circuit N1 for forming an inverted signal FX of the sub-word selection signal FXB is provided as a sub-word selection line driving circuit FXD, and its output signal is used as an operating voltage terminal of the first CMOS inverter circuit. It is supplied to the source terminal of the P-channel MOSFET Q21. This second CMOS inverter circuit N
Although not particularly limited, a plurality of sub-word drivers SW 1 are formed in the cross area as shown in FIG.
Commonly used corresponding to D.

In the above configuration of the sub-word driver SWD, when the main word line MWL is at a high level such as the boosted voltage VPP corresponding to the word line selection level, the N-channel type of the first CMOS inverter circuit The MOSFET Q22 is turned on, and the sub-word line SWL is set to a low level such as the ground potential of the circuit. At this time, the sub-word selection signal FXB becomes a selection level such as a low level such as the ground potential of the circuit, and the second CMOS as the sub-word selection line driving circuit FXD
Even if the output signal of the inverter circuit N1 is set to the selected level corresponding to the boosted voltage VPP, the main word line M
Depending on the non-selection level of WL, P-channel MOSFET
Since TQ21 is off, the sub word line SW
L is set to a non-selected state due to the ON state of the N-channel MOSFET Q22.

When the main word line MWL is at a low level such as the ground potential of a circuit corresponding to the selected level, the N-channel type MO of the first CMOS inverter circuit is
The SFET Q22 is turned off, and the P-channel type MO
SFET Q21 is turned on. At this time, if the sub-word selection signal FXB is at a low level such as the ground potential of the circuit, the output signal of the second CMOS inverter circuit N1 as the sub-word selection line driving circuit FXD is set to the selection level corresponding to the boosted voltage VPP. , The sub word line SWL is set to a selection level such as VPP. If,
If the sub-word selection signal FXB is at a non-selection level such as the boosted voltage VPP, the second CMOS inverter circuit N
2 becomes low level, and at the same time, N
The channel type MOSFET Q23 is turned on to set the sub-word line SWL to the low level non-selection level.

The main word line MWL and the first sub-word select line FXB arranged in parallel with the main word line MWL are both set to a non-selection level such as VPP as described above. Therefore, even when an insulation failure occurs between the main word line MWL and the first sub-word selection line FXB arranged in parallel when the RAM is in the non-selection state (standby) state, leakage current flows. There is no. As a result, the first sub-word selection line FXB can be formed between the main word lines MWL and arranged on the sub-array, and the DC failure due to the above-described leakage current can be avoided even when the layout density is increased. It will be reliable.

FIG. 11 is a main block diagram for explaining the relationship between the main word lines of the memory array and the sense amplifiers. In the figure, one main word line MWL is shown as a representative. This main word line MWL is selected by the main word driver MWD. Adjacent to the above main word driver,
Sub-word driver S corresponding to the even-numbered sub-word line
A WD is provided.

Although not shown in the figure, a complementary bit line (Pair Bit Line) is provided so as to be orthogonal to a sub-word line arranged in parallel with the main word line MWL. In this embodiment, although not particularly limited, the complementary bit lines are also divided into even columns and odd columns, and the sense amplifiers SA are distributed to the left and right corresponding to the respective sub-arrays (memory cell arrays). Although the sense amplifier SA is of the shared sense type as described above, the sense amplifier SA at the end does not substantially have one complementary bit line, but the sense amplifier SA is connected to the complementary bit line via a shared switch MOSFET. Connected.

In the configuration in which the sense amplifiers SA are dispersedly arranged on both sides of the sub-array as described above, since the complementary bit lines are allocated to odd columns and even columns, the pitch of the sense amplifier columns can be reduced. . In other words, it is possible to secure element areas for forming the sense amplifiers SA while arranging complementary bit lines at high density. The sub input / output lines are arranged along the arrangement of the sense amplifiers SA. This sub input / output line is connected to the complementary bit line via a column switch. The column switch is composed of a switch MOSFET. The gate of this switch MOSFET is connected to the column decoder CO.
Column selection line Y to which the LUMN DECORDER selection signal is transmitted
Connected to S.

FIG. 12 is a schematic block diagram showing one embodiment of the peripheral portion of the dynamic RAM.
The timing control circuit TG receives a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, and an output enable signal / OE supplied from external terminals, and determines an operation mode and responds to it. Thus, various timing signals necessary for the operation of the internal circuit are formed. In this specification and the drawings, the symbol / is used to mean that the low level is the active level.

Signals R1 and R3 are row-related internal timing signals, and are used for row-related selection operations.
The timing signal φXL is a signal for taking in and holding a row-related address, and is supplied to the row address buffer RAB. That is, the row address buffer RAB
Is controlled by the address signal A0 by the timing signal φXL.
ＡAi are fetched and held in the latch circuit. The timing signal φYL is a signal for capturing and holding a column address, and is supplied to the column address buffer CAB. That is, the column address buffer RAB fetches an address input from the address terminals A0 to Ai in response to the timing signal φYL and causes the latch circuit to hold the address.

The signal φREF is a signal generated in the refresh mode, and is supplied to the multiplexer AMX provided at the input of the row address buffer.
In the refresh mode, control is performed so as to switch to the refresh address signal formed by the refresh address counter circuit RFC. The refresh address counter circuit RFC counts a refresh step pulse φRC formed by the timing control circuit TG to generate a refresh address signal. In this embodiment, an auto refresh and a self refresh as described later are provided. The timing signal φX is a word line selection timing signal, and is supplied to the decoder XIB, and based on the decoded signal of the lower 2 bits of the address signal, there are four types of word line selection timing signals Xi.
B is formed. The timing signal φY is a column selection timing signal, and is supplied to the column predecoder YPD to output the column selection signals AYix, AYjx, AYkx.

Timing signal φW is a control signal for instructing a write operation, and timing signal φR is a control signal for instructing a read operation. These timing signals φW and φR are supplied to the input / output circuit I / O to activate an input buffer included in the input / output circuit I / O at the time of a write operation, thereby bringing the output buffer into an output high impedance state. On the other hand, at the time of the read operation, the output buffer is activated, and the input buffer is set to the output high impedance state. Timing signal φM
S is a signal that instructs, but is not limited to, a memory array selection operation, is supplied to a row address buffer RAB, and a selection signal MSi is output in synchronization with this timing. Timing signal φSA is a signal for instructing the operation of the sense amplifier. An activation pulse for the sense amplifier is formed based on the timing signal φSA.

In this embodiment, the row-related redundant circuit XR
ED is illustratively shown as a representative. That is, the circuit X-RED includes a storage circuit for storing a defective address and an address comparison circuit. The stored defective address is compared with the internal address signal BXi output from the row address buffer RAB, and when they do not match, the signal XE is set to the high level, and the signal XEB is set to the low level to enable the operation of the normal circuit. When the input internal address signal BXi matches the stored defective address, the signal XE is set to low level to inhibit the operation of selecting the defective main word line of the normal circuit, and the signal XEB is set to high level to set one signal. A selection signal XRiB for selecting a spare main word line is output.

The internal voltage generating circuit VG receives the power supply voltage VDD such as 3.3 V supplied from an external terminal and the ground potential VSS of 0 V, and receives the boosted voltage VPP (+3.8
V), an internal voltage VDL (+2.2 V), a plate voltage (precharge voltage) VPL (1.1 V), and a substrate voltage VBB (-1.0 V). Although not particularly limited, the boosted voltage VPP and the substrate voltage VBB stably form the voltages VPP and VBB using a charge pump circuit and its control circuit. The internal voltage VDL is formed by the internal step-down power supply circuit using the reference voltage VLR.
The plate voltage VPL and the half precharge voltage are:
It is formed by dividing the internal step-down voltage VDL by half.

FIG. 13 is a timing chart for explaining an example of the operation of the dynamic RAM according to the present invention. / RAS initiates row-related memory access, and generates a row address-related selection timing signal RAC, thereby causing word line SWL
Is selected. This signal RAC is delayed by a delay circuit to form sense amplifier activation signal / SAE.
The sense amplifier activation signal / SAE is supplied to a timing generation circuit to form an overdrive pulse and a sense amplifier activation signal. As a result, the potential of the common source line CSP becomes the internal voltage V for the overdrive time.
It is set to be higher than DL to speed up the rise of the bit line BL or / BL to a high level. Thereafter, the signal / SAE is delayed by a delay circuit to raise the Y selection signal YS.

Using the above overdrive pulse,
The timing signal EB of the embodiment shown in FIG. 1 may be formed. In other words, the operation of the level extraction circuit LDW is necessary because the overdrive voltage VDDCL is used.
This is because P causes the internal voltage VDL to become higher than the reference voltage VLR. Thus, the level extraction circuit L can be used without using a special timing generation circuit.
DW operation timing signals can be formed.

The operational effects obtained from the above embodiment are as follows. That is, (1) a first differential circuit and a current which operate on a power supply voltage supplied from an external terminal, receive a reference voltage and an internal step-down voltage, and perform an amplification operation based on a first operation control signal. The current amplifying MOSFET when the internal step-down voltage is made lower than a reference voltage.
A level raising circuit that raises the internal step-down voltage by an FET; operates with a power supply voltage supplied from the external terminal; receives the reference voltage and the internal step-down voltage; And a second differential circuit that temporarily operates according to the operation control signal of claim 2, wherein a level extraction circuit that forms a current path for lowering the internal step-down voltage when the internal step-down voltage is increased with respect to the reference voltage By combining the above, it is possible to obtain an effect that it is possible to obtain an internal step-down power supply circuit capable of stabilizing within a short time at the start of operation while reducing power consumption.

(2) A differential circuit and a current amplifying MOSFET that operate on the power supply voltage supplied from the external terminal, receive the first reference voltage and the internal step-down voltage, and perform an amplifying operation based on an operation control signal. A level raising circuit for raising the internal step-down voltage by the current amplification MOSFET when the internal step-down voltage is lower than the first reference voltage, and operating with a power supply voltage supplied from an external terminal. A differential circuit receiving a second reference voltage raised by a very small voltage with respect to the reference voltage and an internal step-down voltage, and performing an amplifying operation based on the operation control signal; Low power consumption is achieved by combining with a level extraction circuit that forms a current path for lowering the internal step-down voltage when the internal step-down voltage is increased with respect to the voltage. However, there is an effect that an internal step-down power supply circuit that can be stabilized within a short time at the start of operation can be obtained.

(3) It operates steadily by the power supply voltage supplied from the external terminal, receives the reference voltage and the internal step-down voltage, forms the internal step-down voltage corresponding to the reference voltage, and An internal step-down voltage generation circuit, which is designed so that the internal circuit operated by the step-down voltage has only a current supply capability corresponding to a leak current in a non-operating state, further secures an internal step-down voltage in a standby state of the internal circuit. The effect is obtained.

(4) By using the internal step-down power supply circuit as the operating voltage of the sense amplifier which is overdriven at a voltage higher than the internal step-down voltage at the start of the operation, the sense amplifier can be internally driven within a short time at the start of the operation. Since the step-down voltage can be stabilized, the effect that the column selection operation can be performed at an early timing can be obtained.

(5) A special timing generation circuit is provided by using the first operation control signal as the sense amplifier activation signal and the second control signal as the overdrive sense amplifier activation signal. The effect is obtained that the level pull-up circuit and the level pull-out circuit constituting the internal step-down power supply circuit can be operated at the optimum timing without any need.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, FIG.
As a current path for level extraction constituting the level extraction circuit of FIG.
OSFET Q38 can be omitted. MOSFE
TQ39 can be replaced by a resistance element. As described above, the path for level withdrawal can take various embodiments.

Dynamic RA to which the present invention is applied
Various embodiments can be adopted for the configuration of the sub-array constituting M or the arrangement of a plurality of memory arrays mounted on the semiconductor chip according to the storage capacity and the like. Also,
The configuration of the sub-word driver can take various embodiments. The portion of the input / output interface may be a synchronous dynamic RAM which operates in synchronization with a clock signal. As for the number of sub-word lines assigned to one main word line, various embodiments such as eight as well as four as described above can be adopted. The present invention can be widely used for a semiconductor integrated circuit device provided with an internal step-down power supply circuit required for operation of an internal circuit by stepping down a power supply voltage supplied from an external terminal in addition to the dynamic RAM. .

[0090]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the first operation control circuit operates on the power supply voltage supplied from the external terminal, receives the reference voltage and the internal step-down voltage, and performs the amplification operation based on the first operation control signal.
A level raising circuit configured to raise the internal step-down voltage by the current amplifying MOSFET when the internal step-down voltage is lower than a reference voltage, and a level boosting circuit that is supplied from the external terminal. A second differential circuit that operates at a power supply voltage, receives the reference voltage and the internal step-down voltage, and temporarily operates according to a second operation control signal at the start of operation of the level raising circuit according to the operation control signal; By combining with a level extraction circuit that forms a current path for lowering the internal step-down voltage when the internal step-down voltage is increased with respect to the reference voltage, power consumption can be reduced and the operation can be started within a short period of time. Thus, it is possible to obtain an internal step-down power supply circuit that can be stabilized.

The effects obtained by the other typical aspects of the invention disclosed in the present application will be briefly described as follows.
It is as follows. It operates with a power supply voltage supplied from an external terminal, receives a first reference voltage and an internal step-down voltage, and is configured by a differential circuit and a current amplification MOSFET configured to perform an amplification operation by an operation control signal. A level boosting circuit that raises the internal step-down voltage by the current amplification MOSFET when the internal step-down voltage is lower than the first reference voltage; and operates with a power supply voltage supplied from an external terminal. A differential circuit receiving the second reference voltage raised by a very small voltage and the internal step-down voltage, and performing an amplification operation based on the operation control signal. By combining with a level extraction circuit that forms a current path that lowers the internal step-down voltage when the voltage is increased,
It is possible to obtain an internal step-down power supply circuit capable of stabilizing within a short time at the start of operation while reducing power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of an internal step-down power supply circuit according to the present invention.

FIG. 2 is a timing chart for explaining an operation of the internal step-down power supply circuit of FIG. 1;

FIG. 3 is a block diagram showing another embodiment of the internal step-down power supply circuit according to the present invention.

FIG. 4 is a timing chart for explaining an operation of the internal step-down power supply circuit of FIG. 3;

FIG. 5 is a circuit diagram showing one embodiment of an internal step-down voltage generating circuit and a level extracting circuit of FIGS. 1 and 3;

FIG. 6 is a circuit diagram showing one embodiment of a voltage generating circuit for generating a reference voltage used in the present invention.

FIG. 7 is a layout diagram showing one embodiment of a dynamic RAM on which the internal step-down power supply circuit according to the present invention is mounted.

FIG. 8 is a schematic layout diagram for explaining the dynamic RAM.

FIG. 9 is a main part circuit diagram showing one embodiment of a sense amplifier section and peripheral circuits of the dynamic RAM.

FIG. 10 is a main part block diagram for explaining a relationship between a main word line and a sub word line of the sub array shown in FIG. 7;

11 is a main part block diagram for explaining a relationship between a main word line and a sense amplifier of the sub-array in FIG. 7;

FIG. 12 is a schematic block diagram showing one embodiment of a peripheral portion of the dynamic RAM of FIG. 1;

FIG. 13 is a waveform chart for explaining an example of the operation of the dynamic RAM according to the present invention.

[Explanation of symbols]

9: Internal voltage generating circuit, 10: Memory chip, 11: Main row decoder area, 12: Main word driver area, 13: Column decoder area, 14: Peripheral circuit, bonding pad area, 15: Meseli cell array (sub array) , 16: sense amplifier area, 17: sub-word driver area, 18: intersection area (cross area) SA: sense amplifier, SWD: sub-word driver, M
WD: Main word driver, CTRL: Memory array control circuit, MWL0 to MWLn: Main word line, S
WL, SWL0 ... sub-word line, YS ... column select line,
SBARY: sub-array, TG: timing control circuit,
I / O: input / output circuit, RAB: row address buffer,
CAB: column address buffer, AMX: multiplexer, RFC: refresh address counter circuit, X
PD, YPD: Pretecoder circuit, X-DEC: Row system redundant circuit, XIB: Decoder circuit, Q1-Q49: MO
SFET, CSP, CSN: common source line, YS: column selection signal, LIO: sub common input / output line, MIO: common input / output line, M1 to M3: metal layer, SN: storage node, PL: plate electrode, BL: Bit line, SD: source / drain, FG: first polysilicon layer.

Claims (8)

[Claims] A first differential circuit which operates on a power supply voltage supplied from an external terminal, receives a reference voltage and an internal step-down voltage, and performs an amplification operation based on a first operation control signal; A level raising circuit configured by an amplification MOSFET, which raises the internal step-down voltage by the current amplification MOSFET when the internal step-down voltage is made lower than a reference voltage; and operates by a power supply voltage supplied from an external terminal. A second differential circuit receiving the voltage and the internal step-down voltage and temporarily operating by a second operation control signal at the start of operation of the level raising circuit based on the operation control signal, and A semiconductor integrated circuit device comprising: a level extracting circuit for forming a current path for lowering the internal step-down voltage when the voltage is increased. 2. The apparatus operates steadily by a power supply voltage supplied from an external terminal, receives the reference voltage and the internal step-down voltage, forms the internal step-down voltage corresponding to the reference voltage, and forms the internal step-down voltage. 2. The semiconductor integrated circuit device according to claim 1, further comprising an internal step-down voltage generating circuit adapted to have an internal circuit operated by a voltage having only a current supply capability corresponding to a leak current in a non-operating state. . 3. A differential amplifier and a current amplifying MOSFET that operate on a power supply voltage supplied from an external terminal, receive a first reference voltage and an internal step-down voltage, and perform an amplifying operation based on an operation control signal. A level raising circuit configured to raise the internal step-down voltage by the current amplification MOSFET when the internal step-down voltage is lower than the first reference voltage; and operating with a power supply voltage supplied from an external terminal. A differential circuit that receives a second reference voltage raised by a very small voltage with respect to the reference voltage and an internal step-down voltage and performs an amplification operation based on an operation control signal; On the other hand, a semiconductor integrated circuit device comprising: a level extraction circuit for forming a current path for lowering the internal step-down voltage when the internal step-down voltage is raised. 4. An apparatus which operates steadily with a power supply voltage supplied from an external terminal, receives the first reference voltage and an internal step-down voltage, and forms an internal step-down voltage corresponding to the first reference voltage. 4. The circuit according to claim 3, further comprising an internal step-down voltage generating circuit configured to allow the internal circuit operated by the internal step-down voltage to have only a current supply capability corresponding to a leak current in a non-operating state. Semiconductor integrated circuit device. 5. A plurality of word lines and a plurality of complementary bit line pairs, provided between the word line and one of the complementary bit lines, a gate connected to the word line, and one source,
An address selection MOSFET connected to the one complementary bit line corresponding to the drain and the address selection MO
A dynamic memory cell comprising a storage capacitor in which the other source and drain of the SFET are connected to one electrode and a predetermined voltage is applied to the other electrode; and the cross-connected gate and drain are connected to the plurality of complementary gates and drains. A plurality of pairs of P-channel MOSFETs and a cross-connected gate and drain, which are respectively connected to a bit line pair and constitute an amplifying section on the power supply voltage side, are respectively connected to the plurality of complementary bit line pairs, and A sense amplifier including a plurality of pairs of N-channel MOSFETs forming an amplifying unit; a first common source line in which a source of the P-channel MOSFET of the sense amplifier is shared; and an N-channel MOSFET of the sense amplifier A second common source line in which the source of the common is shared, and the power supplied from the external terminal A voltage is supplied to a drain, and a boosted constant voltage is applied to a gate, and an N-channel type voltage clamp MOS for outputting an overdrive voltage higher than the internal step-down voltage from a source.
A source is connected to the source of the FET and the voltage clamp MOSFET, and an overdrive sense amplifier activation signal generated only for a certain period at the start of the amplification operation is applied to the gate and supplied from the drain to the first common source line. P-channel first power MO for outputting operating voltage
An SFET and a gate are supplied with a sense amplifier activation signal, a drain is supplied with an internal step-down voltage formed by the internal step-down voltage generation circuit, and a source is used to output an operating voltage supplied to the first common source line. Channel type second power M
An OSFET and an N-channel type third power MOSFET that has a gate supplied with a sense amplifier activation signal, a source supplied with a circuit ground potential, and a drain supplied with the ground potential supplied to the second common source line. 3. The semiconductor integrated circuit device according to claim 2, further comprising: 6. The P-channel type first power MOS
A constant voltage to be output from the source of the voltage-clamping MOSFET is supplied to an N-type well region in which a FET and a P-channel MOSFET constituting an amplifying unit on the internal step-down voltage side are formed. The semiconductor integrated circuit device according to claim 5. 7. The control circuit according to claim 6, wherein said first operation control signal is said sense amplifier activation signal, and said second control signal is said overdrive sense amplifier activation signal. Semiconductor integrated circuit device. 8. The sense amplifier activation signal supplied to the gate of the second power MOSFET is supplied from an external terminal in the same manner as the activation signal supplied to the gate of the first power MOSFET supplying the overdrive voltage. 8. The semiconductor integrated circuit device according to claim 7, wherein the semiconductor integrated circuit device is formed using a supplied power supply voltage.