JP2000243084A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To keep an electric charge holding characteristic in high grade without reducing sense speed while reducing operation lower limit voltage. SOLUTION: A DSG potential is made a ground potential by activating a second nMOS transistor 32 in a DSG(dynamic sense ground) driver circuit 3 only for pre-charge operation in a DRAM(dynamic random access memory) and a prescribed period from directly after a sense amplifier driving signal SE is activated, after that, the second nMOS transistor 32 is made a non- activation state, while a DSG potential in a sense amplifier activation period is clamped to near a threshold potential VTN of a first nMOS transistor 31 by raising a DSG potential by a current supplied from a DSG potential compensating circuit 5 and a current discharged from a sense amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a dynamic random access memory (DRAM), and more particularly to a semiconductor memory device having a low-level potential applied to a memory cell array, a bit line and a sense amplifier in accordance with an internal operation of the memory. The present invention relates to a semiconductor memory device to be switched.

[0002]

2. Description of the Related Art In recent years, in a semiconductor device using a DRAM as a memory cell, miniaturization of a transistor and lowering of an operation power supply voltage for the purpose of higher integration and improvement of operation speed have been promoted. In general, when the operating power supply voltage of a DRAM is lowered, the amount of charge stored in a memory cell capacitor is reduced, which causes a problem of deterioration of charge retention characteristics. In addition, since the withstand voltage of the gate oxide film decreases with miniaturization of the transistor, the conventional method of securing the read potential of the memory cell by boosting the word line can secure the reliability of the memory cell transistor. It's getting harder. Furthermore, in recent years, DRA
A semiconductor device in which a large-capacity memory such as M and a custom logic such as a CPU or an ASIC are integrated on one chip, that is, a custom LSI is being put into practical use, and there is a demand for a design that does not use an internal boosted potential and a simplification of the accompanying process. Is growing.

However, when the word line is not boosted, it is necessary to set the threshold potential of the memory cell transistor low in order to keep the read charge amount of the memory cell equal to that when the word line is boosted. On the other hand, when the threshold potential is lowered, the sub-threshold leakage current of the memory cell transistor increases, so that the deterioration of the charge retention characteristic also becomes a problem. As a conventional method for solving this problem, disclosed in Japanese Patent Application Laid-Open No. 7-240093,
So-called boosted sense ground (boostedsens)
e ground (BSG) system is known.

Hereinafter, the circuit configuration and operation of a conventional boost sense ground system will be described with reference to the drawings.

FIG. 16 shows a partial circuit configuration showing a connection relationship between a non-selected memory cell of a DRAM and an activated sense amplifier. As shown in FIG. 16, the memory cell 500 has a gate connected to the word line WL,
The memory cell transistor 502 has a drain connected to the bit complementary line / BL and a source connected to one electrode of the memory cell capacitor 501. The internally generated cell plate potential VCP is applied to the other electrode of the memory cell capacitor 501, and the internally generated substrate potential VBB is applied to the memory cell transistor 502.

The sense amplifier circuit 510 comprises a first n-type transistor 511n and a first p-type transistor 511
A first inverter 511 composed of p and a second inverter 512 composed of a second n-type transistor 512n and a second p-type transistor 512p are cross-coupled. An output portion, which is a common drain of the first n-type transistor 511n and the first p-type transistor 511p, is connected to the bit complementary line / BL, and is connected to the second n-type transistor 512n and the second p-type transistor 512p. The output part, which is a common drain, is a bit line BL
Is connected to Also, the first n-type transistor 51
1n and the second n-type transistor 512n have respective sources connected to the sense amplifier ground power supply line SAN,
Each source of the p-type transistor 511p and the second p-type transistor 512p is connected to the sense amplifier power supply line SAP.

FIG. 17 shows a circuit configuration of a boosted sense ground system, and a DRAM including a sense amplifier and a memory cell.
Of the internal circuit 550 is the BSG potential wiring 56
0 is connected. BSG potential wiring 560 is connected to BSG driver circuit 570 and BSG driver circuit 57.
0 has a first nMOS transistor 571 whose drain is shared, whose gate is diode-connected and whose source is grounded, and a second nMOS transistor 572 whose gate receives the control signal φ and whose source is grounded. ing. The BSG potential compensation circuit 5
80 is connected, and the BSG potential compensation circuit 580 is
When the BSG potential falls below a predetermined value, a current is supplied to the BSG potential wiring 560.

FIG. 18 illustrates the operation of the boosted sense ground system in the DRAM configured as described above.
(A) and (b) show the bit line pair and the sense amplifier ground potential SA during the read operation by the sense amplifier.
FIG. 18A shows potential waveforms of N and the power supply potential SAP for the sense amplifier. FIG. 18A shows each potential waveform when the boosted sense ground system is not used, and FIG. 18B shows a case where the boosted sense ground system is used. Of each potential waveform. 18A and 18B, time tc represents the drive timing of the word line WL, and time td represents the drive timing of the sense amplifier.

As shown in FIG. 18B, when the boosted sense ground system is used, the ground potential BSG for the sense amplifier is set at time td when the sense amplifier is activated.
Until the threshold voltage is maintained by the clamping action of the first nMOS transistor 571 in the BSG driver circuit 570 shown in FIG.

At time td, the second n shown in FIG.
MOS transistor 572 receives control signal φ at time t
By becoming conductive during the period from d to time tn, the rise of the BSG potential due to the current flowing from the sense amplifier is suppressed.

As described above, according to the boosted sense ground system, the potential of the bit complementary line / BL on the low potential side becomes higher than the ground potential VSS, so that it is the gate-drain voltage of the memory cell transistor 502 shown in FIG. The first bias voltage value VGS1 is larger than that in the method without using the boosted sense ground method shown in FIG. Thereby, the memory cell transistor 5 in the non-selected state
The sub-threshold leak current flowing in the channel direction 02 decreases exponentially as the first bias voltage value VGS1 increases. This sub-threshold leak current corresponds to the memory cell capacitor 501 shown in FIG.
However, by setting the BSG potential higher than the ground potential VSS, the first bias voltage value VGS1 can be secured large. As a result, the sub-threshold leakage current is reduced,
The charge retention characteristics of the DRAM can be improved.

[0012]

In the semiconductor memory device using the conventional boosted sense ground system, the sense amplifier ground potential SAN of the sense amplifier circuit 510 shown in FIG. 16 is shown in FIG. 17 with respect to the ground potential VSS. The first n
In order to maintain the voltage to be higher by the threshold potential of the MOS transistor 571, the second bias voltage VGS2 shown in FIG. 16 which is the source-gate voltage of the first n-type transistor 511n is changed to the level shown in FIG. This is smaller than the method in which the sense amplifier ground potential SAN is not boosted.

The second bias voltage VGS2 is equal to the value of the first n-type transistor 511 of the sense amplifier circuit 510.
n indicates a gate-source bias voltage value in the direction from the source to the gate of n, and when this value is small, the first n
Since the current drive capability of the type transistor 511n is reduced, the capability of bringing the bit complementary line / BL closer to the sense amplifier ground potential SAN is reduced.
There is a problem that the speed until a sufficient potential difference is generated between L and / BL, that is, the sense speed is reduced.

If the power supply voltage is lowered in order to reduce the voltage, the second bias voltage value VGS2 also decreases.
The problem that the sense speed is deteriorated is particularly problematic in DR.
It becomes remarkable in AM. When the power supply voltage value is extremely low, the second bias voltage value VGS2 is the first bias voltage of the sense amplifier circuit 510 even when the sense amplifier is activated.
Does not exceed the threshold value of the n-type transistor 511n, so that the sense amplifier circuit 510 cannot perform a desired operation.

In other words, the operating condition of the sense amplifier circuit 510 is that the precharge potential VBP of the bit line pair BL, / BL is equal to or higher than the sum of the BSG potential and the threshold potential VTN of the first n-type transistor 511n. Becomes For example, in FIG. 18B, when the BSG potential is 0.5 V,
When the threshold potential VTN is 0.6 V, the lower limit voltage of the precharge potential VBP is 1.1 V. If the precharge potential VBP is half the power supply potential VDD, the operation lower limit voltage as a DRAM is It becomes 2.2V or more.

On the other hand, in the case of FIG. 18A, since the low potential SG for the sense amplifier is short-circuited to the ground potential VSS, the lower limit voltage of the precharge potential VBP is 0.6V.
, And the operation lower limit voltage of the DRAM becomes 1.2 V or more. Therefore, the operation lower limit voltage of the DRAM in the case of using the boosted sense ground system shown in FIG.
8 (a) is higher than the operation lower limit voltage of the DRAM when the boosted sense ground method is not used, so that there is a problem that the power supply voltage cannot be substantially reduced.

As shown in FIG. 17, the BSG potential is set to the first nMOS in the BSG driver circuit 570.
Transistor 571 and second nMOS transistor 5
72 tends to steadily decrease due to the influence of a leak current or the like through 72, and the BSG potential is changed to the ground potential VSS.
To keep the potential higher than the BSG potential compensation circuit 5
80, the current must be constantly supplied, which causes a problem that the power consumption of the DRAM increases.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and it is an object of the present invention to reduce the lower-limit operation voltage while maintaining a high charge retention characteristic of a memory cell without lowering the sensing speed. Aim.

[0019]

In order to achieve the above object, the present invention has a configuration in which a ground potential for a sense amplifier in a DRAM type semiconductor memory device is switched according to a drive timing of the sense amplifier.

Specifically, a semiconductor memory device according to the present invention has a plurality of memory cells formed on a semiconductor substrate and provided at respective intersections of a plurality of word lines and a plurality of bit line pairs. A memory cell array, a plurality of sense amplifier circuits provided for each of a plurality of bit line pairs, and amplifying and outputting a potential difference read to each bit line pair; and a plurality of sense amplifier circuits applied to the memory cells, the bit line pairs, and the sense amplifier circuit. Low-level potential generating means for generating and outputting a low-level potential out of the high-level potential and the low-level potential, wherein the low-level potential generating means generates a first potential substantially equal to the ground potential as the low-level potential. A ground potential generation unit having a semiconductor element for generating a ground potential, and a second potential that operates when a potential exceeding the threshold potential is applied and is substantially equal to the threshold potential as a low level potential A generation threshold potential generating unit having a threshold potential generation semiconductor element, and a ground potential control section for controlling the operation of the semiconductor device for generating a ground potential.

According to the semiconductor memory device of the present invention, the low-level potential generating means includes the ground potential as the low-level potential among the high-level potential and the low-level potential applied to the memory cell, the bit line pair, and the sense amplifier circuit. Almost equal first
A ground potential generating section having a ground potential generating semiconductor element for generating a potential of the same; a threshold potential generating section having a threshold potential generating semiconductor element for generating a second potential substantially equal to the threshold potential as a low level potential; A ground potential control unit for controlling the operation of the potential generating semiconductor element. For this reason, when the memory cell includes a capacitor for holding data and a switch transistor in which access between the capacitor and the bit line is controlled by a word line, a low level is applied to a memory cell connected to an unselected word line. Since the potential is substantially equal to the threshold potential of the threshold potential generating semiconductor element which is the second potential higher than the ground potential, the gate-drain voltage when the switch transistor is off increases. Further, when the sense amplifier circuit includes a transistor, the low-level potential of the sense amplifier is substantially equal to the ground potential as the first potential, so that the gate-source voltage when the transistor is turned on increases.

In the semiconductor memory device according to the present invention, when the ground potential generating semiconductor element receives a control signal from the ground potential control unit and a part of the plurality of sense amplifier circuits is activated. It is preferable that the first potential is generated by being activated for a predetermined period from the time when the first potential is generated, and the threshold potential generating semiconductor element generates the second potential during a period in which the ground potential generating semiconductor element is not activated. . With this configuration, the low-level potential becomes substantially equal to the ground potential, which is the first potential, when the operation of the sense amplifier selected from the outside rises, so that the gate-source voltage of the sense amplifier when the transistor is turned on increases. Become.

In the semiconductor memory device according to the present invention, the semiconductor element for generating the ground potential receives a control signal from the ground potential control unit, and during a period in which the plurality of sense amplifier circuits are inactive and in the plurality of sense amplifier circuits. The first potential is generated by being activated during a predetermined period from the time when some of the sense amplifier circuits are activated, and the semiconductor element for generating the threshold potential is used as the semiconductor element for generating the ground potential. It is preferable to generate the second potential during a period in which it is not activated. With this configuration, even when the sense amplifier is in the inactive state, the low-level potential becomes substantially the first potential, that is, the ground potential. Therefore, the ground potential is generated during the standby period of the memory to maintain the ground potential. Is no longer needed.

In the semiconductor memory device of the present invention, the low-level potential generating means generates a reference potential substantially equal to the threshold potential, and the low-level potential becomes higher than the reference potential. A potential compensating unit that compensates the low-level potential by supplying current to the
It is preferable that the reference potential generator and the potential compensator operate during a period in which the ground potential generator is not activated. With this configuration, the reference potential generating unit and the potential compensating unit can be in an inactive state during the period when the low level potential is set to the ground potential.

In this case, the potential of the lower potential bit line of the bit line pair connected to the active sense amplifier circuit of the plurality of sense amplifier circuits is higher than the low level potential. It is preferable that the ground potential generating unit transition from the active state to the inactive state. Thus, when the sense amplifier is inactive, the bit line pair connected to the sense amplifier is normally precharged to about one half of the power supply potential, and the active sense amplifier circuit is When the potential of the lower potential bit line of the pair of bit lines connected to is higher than the lower potential, the ground potential generator transitions from the active state to the inactive state. Since the current flows from the activated low potential side bit line, the amount of current from the potential compensating unit for boosting the low level potential to the threshold potential can be reduced.

In this case, it is preferable that the potential compensator has current supply capability switching means for switching the current supply capability of the potential compensator in accordance with the memory capacity of the memory cell array.

In this case, the current supply capability switching means for switching the current supply capability of the potential compensation unit according to the number of sense amplifier circuits activated at one operation timing among the plurality of sense amplifier circuits among the plurality of sense amplifier circuits. It is preferable to have

In the semiconductor memory device according to the present invention, the low-level potential generating means includes a reference potential generating section for generating a reference potential substantially twice as high as the threshold potential, and a low-level potential generating section for making the low-level potential substantially equal to the threshold potential. A potential compensating unit that compensates for the low-level potential by supplying a current; the potential compensating unit has a gate receiving the reference potential, a drain receiving a current from the potential compensating unit, and a source having the low-level potential. It is preferable to include a field effect transistor for outputting. With this configuration, the potential compensating unit that compensates for the low-level potential includes a field-effect transistor that receives the reference potential at the gate, receives the current from the potential compensating unit at the drain, and outputs the low-level potential to the source. The operation of detecting the level potential and the operation of adjusting the current supply amount of the current for raising the low level potential are performed by one transistor. As a result, there is no transmission delay from the detection operation to the current supply operation.

In this case, the potential of the lower potential bit line of the bit line pair connected to the active sense amplifier circuit of the plurality of sense amplifier circuits is higher than the low level potential. It is preferable that the ground potential generating unit transition from the active state to the inactive state.

In this case, it is preferable that the potential compensator has a current supply capability switching means for switching the current supply capability of the potential compensator in accordance with the memory capacity of the memory cell array.

In this case, the potential compensation unit switches the current supply capability of the potential compensation unit according to the number of sense amplifier circuits activated at one operation timing among the plurality of sense amplifier circuits. It is preferable to have means.

In the semiconductor memory device according to the present invention, the threshold potential generating semiconductor element comprises a first semiconductor element and a second semiconductor element, and the low level potential generating means includes a low level potential higher than the ground potential. A potential compensating unit for compensating a low level potential by supplying a current so as to generate a threshold potential for receiving a control signal from a ground potential control unit and selecting a first semiconductor element or a second semiconductor element. Preferably, the semiconductor device further includes a semiconductor element selecting unit. With this configuration, since the threshold potential generating semiconductor element includes the first semiconductor element and the second semiconductor element, the threshold potential generation semiconductor element is higher than the ground potential depending on the period when a large current flows through the sense amplifier and the period when the large current does not flow. A high low-level potential can select either the first semiconductor element or the second semiconductor element.

In this case, the size of the second semiconductor element is smaller than the size of the first semiconductor element, and the semiconductor element selecting means for generating the threshold potential includes a part of the plurality of sense amplifier circuits. Preferably, an output from the first semiconductor element is selected for a predetermined period from the time when the circuit is activated, and an output from the second semiconductor element is selected after the predetermined period has elapsed. With this configuration, the low-level potential is generated by the first semiconductor element having a large size during a period in which a large current flows to the sense amplifier and a period during which the low-level potential is set to the ground potential. Can be In addition, during a period in which a part of the plurality of sense amplifier circuits is in an active state and a large current does not flow, a small-sized second semiconductor element is used, so that a low-level potential due to a leak current is less likely to decrease.

In the semiconductor memory device of the present invention, a plurality of memory cell arrays are provided, and a plurality of sense amplifier circuits are provided adjacent to a side parallel to a word line extending direction in each of the plurality of memory cell arrays. A plurality of sense amplifier rows, and a memory core block including a plurality of memory cell arrays and a plurality of sense amplifier rows, wherein the low-level potential generating means is provided in a direction in which the plurality of sense amplifier rows in the memory core block extend. It is preferable to be provided so as to be adjacent to both parallel side portions. With this configuration, the average distance to the sense amplifier row is reduced to about half compared to the case where the low-level potential generation means is provided only in one of the low-level potential generation means.
Since the current flowing out of the sense amplifier circuit flows in a distributed manner to both low-level potential generation units, the effective resistance value between the low-level potential generation unit and each sense amplifier circuit can be reduced. As a result, the deterioration of the sensing speed due to the voltage drop of the wiring resistance is alleviated, and the operating characteristics of the simultaneously activated sense amplifier circuits are less likely to vary.

In this case, the semiconductor element for generating the ground potential, the semiconductor element for generating the threshold potential, and the semiconductor element included in the sense amplifier row of the low-level potential generating means are formed in the shared wells respectively provided continuously on the semiconductor substrate. It is preferred that

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an outline of a semiconductor memory device according to the present invention will be described with reference to the drawings.

FIG. 1 shows a dynamic sense ground (Dynamic) in a DRAM which is a semiconductor memory device according to the present invention.
1 shows a functional configuration for implementing a sense ground (DSG) method. As shown in FIG. 1, the DRAM according to the present invention includes a DRAM internal circuit 1 including a sense amplifier circuit, a memory cell, and the like, and a low-level potential generation unit 2. The low-level potential generator 2 includes a DSG driver circuit 3 as a ground potential generator and a threshold potential generator.
, A control signal generation circuit 4 as a ground potential control unit, and a DSG potential compensation circuit 5 as a potential compensation unit.

The ground potential wiring of the internal circuit 1 is connected to the DSG potential wiring 6, and the DSG potential wiring 6 is connected to the DSG driver circuit 3 and the DSG potential compensation circuit 5.

The DSG driver circuit 3 has a first nMOS transistor 31 whose drain is shared, whose gate is diode-connected and whose source is grounded, and whose gate is internally supplied from the control signal generation circuit 4 as a ground potential control unit. A second nMO having a source grounded and receiving a control signal NSG
It has an S transistor 32.

The control signal generation circuit 4 receives the sense amplifier drive signal SE and outputs an internal control signal NSG obtained by adding a predetermined delay to the sense amplifier drive signal SE.

The DSG driver circuit 3 according to the present invention has a D
The DSG potential is set to the ground potential (= first potential) during the precharge operation in the RAM and for a predetermined period immediately after the activation of the sense amplifier drive signal SE, and then supplied from the DSG potential compensation circuit 5 The potential of DSG is increased by the current supplied and the current released from the sense amplifier circuit, so that D
The SG potential is clamped near the threshold potential VTN (= second potential) of the first nMOS transistor 31.

As described above, according to the DSG method according to the present invention, the low-level potential for a predetermined period from the start of the operation of the sense amplifier circuit is set to the ground potential, so that the sense amplifier circuit 510 shown in FIG. , The second bias voltage value VGS2 at the time of turning on is sufficiently secured, so that the sensing speed can be improved.

After a lapse of a predetermined period from activation of sense amplifier drive signal SE, DSG potential compensation circuit 5
The first bias voltage VGS1 when the memory cell 500 shown in FIG. 16 is turned off increases as shown in FIG. 16 because the DSG potential is increased by the current supplied from the sense amplifier circuit and the current discharged from the sense amplifier circuit. Improvement can be achieved. Further, since the predetermined period is shortened, that is, the timing difference between the sense amplifier drive signal SE and the internal control signal NSG is reduced, the low-level potential of the bit line becomes lower than the threshold potential VTN during the active period of the sense amplifier circuit. Since the voltage does not fall significantly below the vicinity, the charge retention characteristics are improved as in the conventional boost sense ground system.

The DSG potential compensating circuit 5 supplies current at any time so that the DSG potential becomes a predetermined potential when the sense amplifier circuit is in the active period, and supplies the current when the sense amplifier circuit is in the inactive period. Does not perform the current supply operation by stopping the operation with the DSG potential as the ground potential. As a result, the power consumption associated with driving the DSG potential is
Compared with the conventional boost sense ground system, it can be greatly reduced.

Hereinafter, D using the DSG method according to the present invention will be described.
The RAM type semiconductor memory device will be specifically described. (First Embodiment) A first embodiment of the present invention will be described with reference to the drawings.

FIG. 2 shows a semiconductor memory device according to the first embodiment of the present invention, and shows a block configuration of a DRAM chip. As shown in FIG. 2, the DR according to the present embodiment
The AM chip includes a plurality of memory cell array blocks 10 each having a plurality of memory cells each holding a charge serving as data, and the plurality of memory cell array blocks 10.
A plurality of sense amplifier blocks 20 provided between side portions of each of which are parallel to the direction in which word line WL extends.
And a plurality of sense amplifier driver circuits 21 for driving a sense amplifier circuit included in the sense amplifier block 20
Is provided.

In a region on the side opposite to the memory cell array block 10 with respect to the sense amplifier block 20 and the sense amplifier driver circuit 21, a column-related control circuit block 22 including a column decoder and the like and a low-level potential generating means are disposed adjacent thereto. Are selectively provided.

The sense amplifier ground circuit 23 supplies a dynamic sense amplifier ground potential DSG to each sense amplifier driver circuit 21, and the sense amplifier driver circuit 21 supplies a sense amplifier power supply potential to an adjacent sense amplifier block 20. SAP and the ground potential SAN for the sense amplifier are supplied.

A row decoder 40 for decoding a row address from the outside is provided at one peripheral portion of the memory cell array block 10 in the direction in which the word lines WL extend. Memory cell array 10 and row decoder 40
, Each receives a decode signal from the row decoder 40 and transmits the received decode signal to the word line WLn.
(N = 1, 2, 3,...) And a plurality of sense amplifiers that receive decode signals from the row decoder 40 and control the sense amplifier block 20 and the sense amplifier driver circuit 21 A control block 42 is provided.

The memory cell array block 10 includes a plurality of memory cells arranged in a matrix. For example, the memory cell 51 includes a word line WL 1 driven by a word line driver 41 and a sense amplifier block 2.
It is provided at an intersection where the bit complementary line / BL connected to 0 intersects.

FIG. 3 shows the memory cell array block 10 and the sense amplifier block 20 in the area 100 shown in FIG.
2 shows a specific circuit configuration of the sense amplifier driver circuit 21. As shown in FIG. 3, the memory cell array 101 constituting the memory cell array block 10 includes a memory cell 51, a bit line pair BL, / BL, and a word line WL.
n, WLn + 1.

The drain of the memory cell 51 is the bit line B
L or bit complementary line / BL, a memory cell transistor 51a composed of an nMOS transistor having a gate connected to word line WLn, one electrode connected to cell plate power supply VCP, and the other electrode connected to memory cell transistor 51a. And a memory cell capacitor 51b connected to the source.

The sense amplifier circuit 201 constituting the sense amplifier block 20 includes two nMOS transistors 2
02n and a pMOS transistor 202p, and a sense amplifier ground potential SAN is supplied from the source of each nMOS transistor 202n.
A power supply potential for sense amplifier SAP is supplied from the source of p.

Further, the sense amplifier circuit 201 has two precharging nMs whose drains are connected to a precharge power supply VBP and whose sources are connected to a first internal wiring 205 and a second internal wiring 206, respectively.
The OS transistor 203 and the gate are equalized signal E
And an equalizing nMOS transistor 204 that receives Q and makes the potentials of the bit line pair BL and / BL equal to each other (equalize). In sense amplifier circuit 201, first internal wiring 205 connected to bit line BL and second internal wiring 20 connected to bit complementary line / BL
6 are connected to each other via a first transfer transistor 207 and a second transfer transistor 208 forming transfer gates. First
The transfer transistor 207 receives the first shared gate signal SS1 at its gate, the second transfer transistor 208 receives the second shared gate signal SS2 at its gate, and receives the first shared gate signal SS1 or the second shared gate signal. By selectively activating the gate signal SS2, the memory cell array 10
1 and the bit line pair BL, / BL on the word line WL1 side.
Alternatively, one of the bit line pairs BL and / BL on the WL3 side is selected.

The first internal wiring 205 has a gate of YGT.
Third transfer transistor 209 receiving a signal
And the second internal wiring 206 is connected to the second data line 6 via a third transfer transistor 209 whose gate receives the YGT signal.
1 is connected. Here, the first data line 60 and the second data line 61 are connected to a read or write circuit (not shown).

The sense amplifier driver circuit 21 has an nMOS switch transistor 211 whose gate receives the sense amplifier drive signal SE and sets the sense amplifier ground potential SAN to the dynamic sense amplifier ground potential DSG.
And the sense amplifier drive signal SE inverted by the inverter circuit 212 to receive the sense amplifier power supply potential SAP.
Is connected to the precharge power supply VBP, and the source is connected to the SAP wiring and S p.
It is composed of two precharge nMOS transistors 214 respectively connected to the AN wiring, and an equalizing nMOS transistor 215 whose gate receives the equalizing signal EQ and equalizes the potentials of the SAP wiring and the SAN wiring. ing.

Here, the first shared gate signal SS1 and the second shared gate signal SS input to the sense amplifier circuit 201 and the sense amplifier driver circuit 21
2. The equalizing signal EQ, the YGT signal, and the sense amplifier drive signal SE are all supplied from the sense amplifier control block 42 shown in FIG. Each nM shown in FIG.
A back gate potential VBB having a potential of about -1.0 V is applied to the substrate of the OS transistor to reduce a sub-threshold leak current.

FIG. 4 shows a specific circuit configuration of the sense amplifier ground circuit 23 shown in FIG. The sense amplifier ground circuit 23 shown in FIG. 4 drives the dynamic sense amplifier ground potential DSG, and includes a DSG driver circuit 231 as a ground potential generation unit and a threshold potential generation unit, and a control signal generation circuit 232 as a ground potential control unit. , And a DSG potential compensation circuit 233 as a potential compensation unit.

The DSG potential compensating circuit 233 supplies the reference potential V
A reference potential generation circuit 234 as a reference potential generation unit for generating REF; a DSG level detection circuit 235 for detecting a potential difference between the DSG potential and the reference potential VREF;
A Schmitt trigger circuit 236 for giving a hysteresis characteristic to a control signal when the G potential is boosted, and a DSG as a current supply capability switching means for supplying a boosting current to the DSG driver circuit 231 so that the current supply capability can be switched.
It comprises a precharge circuit 237.

The DSG driver circuit 231 includes a first nMOS transistor 231a as a threshold potential generating semiconductor element having a gate and a drain commonly connected to an output terminal (DSG node) having a DSG potential, and the first nMOS transistor 231a. And a second nMOS transistor 231b as a ground potential generating semiconductor element that receives the ground potential control signal NSG from the control signal generation circuit 232 and sets the DSG potential to the ground potential.

The control signal generation circuit 232 receives the sense amplifier drive signal SE, and outputs a delay signal having a predetermined delay time, for example, a 1 ns delay time with respect to the sense amplifier drive signal SE; Delay circuit 23
A NAND circuit 232b which receives the delay signal from 2a and the sense amplifier drive signal SE and outputs a detection circuit control signal NAMP for activating the DSG level detection circuit 235;
An inverter circuit 232c that receives an output signal from the delay circuit 232a and outputs a ground potential control signal NSG obtained by inverting the received signal.

The reference potential generation circuit 234 is a current source, the gate is grounded, and the source is the power supply potential VD.
D, the drain and the drain of the pMOS transistor 234a are commonly connected to the pMOS transistor 234a having an output terminal, and the reference potential V
A first nMOS transistor 234b for generating and outputting REF, and a drain connected to the first nMOS transistor 2
34b, the gate receives the sense amplifier drive signal SE, the source is grounded, and the reference potential VREF
NMOS transistor 234c for controlling generation of
Consists of Here, the transistor size of the pMOS transistor 234a is smaller than the transistor size of the first and second nMOS transistors 234b and 234c.

The gate of the DSG level detection circuit 235 is a detection circuit control signal NAM from the control signal generation circuit 232.
A first pMOS transistor 2 receiving P and serving as a current source
35a and the source is the first pMOS transistor 235
a first drive transistor 235b having a gate connected to the drain of the first pMOS transistor 235a and having a gate receiving the DSG potential, and a first drive transistor 235b having a gate receiving the reference potential VREF. The second drive transistor 235c, a gate and a drain are commonly connected to the drain of the first drive transistor, and a source is grounded. The first nMOS transistor 235d is grounded, and a gate is shared with the first nMOS transistor 235d. Are connected in common with the drain of the second drive transistor 235c, and the second nMOS transistor 235e whose source is grounded has a differential amplifier circuit. Here, the first nMOS transistor 235d and the second nMOS transistor 235e form a so-called current mirror circuit, and an output signal AMPO is output from a common drain of the second drive transistor 235c and the second nMOS transistor 235e. Is output. Further, the DSG level detection circuit 235 has a gate receiving the detection circuit control signal NAMP and receiving the detection circuit control signal NAMP.
A third nMOS transistor 235f for fixing the output signal AMPO to a low level when AMP is at a high level, that is, when the differential amplifier is in an inactive state, is provided.

When activated in response to the low-level detection circuit control signal NAMP, the differential amplifier configured as described above functions as a comparison circuit for detecting the potential difference between the reference potential VREF and the DSG potential. The output potential resulting from the above operation is output as an output signal AMPO.

An input terminal of the Schmitt trigger circuit 236 is an output signal AMP from the DSG level detection circuit 235.
O, a first inverter circuit including a first pMOS transistor 236a and a first nMOS transistor 236b for outputting a detection signal DET obtained by inverting the polarity of the output signal AMPO;
T, the second pMOS transistor 236c and the second nMOS transistor 236 that output a trigger output signal PSG obtained by inverting the polarity of the detection signal DET.
d, a source connected to the power supply potential VDD, a drain connected between an output terminal of the first inverter circuit and an input terminal of the second inverter circuit, and a gate connected to the second inverter circuit. A third pMOS transistor 236e connected to the output terminal of the circuit. The feedback operation of the third pMOS transistor 236e delays the inversion operation of the detection signal DET and the trigger output signal PSG, so that the trigger output signal P
A hysteresis characteristic is given to SG.

In a normal operation, the high-level potential of the output signal AMPO from the DSG level detection circuit 235 does not reach the power supply potential VDD, so that it is necessary to reduce the through current of the first inverter circuit. The transistor size of the first pMOS transistor 236a is smaller than the transistor size of the first nMOS transistor 236b.

Each of the DSG precharge circuits 237 receives a trigger output signal PSG at one input terminal, and receives a first memory capacity designating signal MEM0 and a second memory capacity designating signal inputted from the outside at the other input terminal. Signal ME
It has a first NAND circuit 237a, a second NAND circuit 237b, and a third NAND circuit 237c that receive M1 and the third memory capacity designation signal MEM2 in this order. Furthermore, the source is selectively activated by receiving the power supply potential VDD, the drain outputting the DSG potential, and the gate receiving the outputs of the first to third NAND circuits 237a to 237c in this order. First
PMOS transistor 237d, second pMOS transistor 237e, and third pMOS transistor 23
7f.

In the present embodiment, the first nMOS transistor 231a in the DSG driver circuit 231
And the substrate of the second nMOS transistor 231b includes:
In order to reduce the sub-threshold leak current, a back gate potential VBB having a potential of about -1.0 V is applied, thereby suppressing a decrease in the DSG potential caused by the sub-threshold leak current.

In the reference potential generation circuit 234, the first nMOS transistor 234b is set such that the reference potential VREF becomes substantially equal to the DSG potential.
The same back gate potential VBB is also applied to the substrate.

Here, the operation of each of the DSG level detection circuit 235, the Schmitt trigger circuit 236, and the DSG precharge circuit 237 will be described with reference to the characteristic curves shown in FIG.

First, the DSG level detection circuit 235
A comparison circuit for detecting and comparing the potential difference between the SG potential and the reference potential VREF, wherein the DSG potential is equal to the reference potential VREF.
When the output signal AMPO is high,
And outputs a low-level output signal AMPO when high.
Is output. When the DSG potential changes at a potential close to the reference potential VREF, the output signal AMPO becomes the power supply potential VD
It becomes an intermediate potential between D and the ground potential VSS.

Next, the Schmitt trigger circuit 236
It has a hysteresis characteristic due to the feedback action via the third pMOS transistor 236e, receives the output signal AMPO from the DSG level detection circuit 235, and receives the output signal AMPO.
A trigger output signal PSG having different threshold values for the rising and falling edges of PO is output.

Next, the DSG precharge circuit 237
The first to third pMOs that receive a trigger output signal PSG and become a plurality of current sources by the received trigger output signal PSG
Activate at least one of S transistors 237d to 237f to compensate for DSG potential (precharge)
I do.

As shown in FIG. 5, by these circuits,
For example, when the DSG potential is the ground potential VSS,
Since the output signal AMPO of the SG level detection circuit 235 and the trigger output signal PSG of the Schmitt trigger circuit 236 become high level, the DSG potential rises. This DS
When the G potential rises to the first threshold potential VTN1, which is substantially equal to the threshold potential of the first nMOS transistor 231a of the DSG driver circuit 231, the precharge operation of the DSG precharge circuit 237 stops.

On the other hand, when the DSG potential decreases from a state higher than the first threshold potential VTN1 due to a leak current or the like, the DSG potential changes to a second threshold potential VTN2 lower than the first threshold potential VTN1. At the time of drop, DSG
The precharge operation is started by the precharge circuit 237, and the DSG potential is raised to the first threshold potential VTN1.

Hereinafter, the operation of the semiconductor memory device configured as described above will be described with reference to the drawings.

FIG. 6 is a timing chart of the DRAM which is the semiconductor memory device according to the present embodiment. Here, of the memory cells 51 shown in FIG. 3, the sense amplifier circuit 201 and the sense amplifier ground circuit 2 for reading data of the memory cell A in which the low level is written are read.
Operation 3 will be described. DRAM according to the present embodiment
FIG. 2 shows an internal strobe signal / RAS synchronized with an externally input RAS (row address strobe) signal.
Are used as activation signals for the row decoder 40 and the sense amplifier control block 42 shown in FIG.

First, in a first period T1 shown in FIG. 6, the internal strobe signal / RAS is at a high level, which corresponds to a DRAM precharge period. During this precharge period, the first shared gate signal SS1
Since both the first and second shared signals SS2 and SS2 are at the high level, both the first transfer transistor 207 and the second transfer transistor 208 shown in FIG. 3 are turned on, and extend outward from both sides of the sense amplifier 201. Bit line pairs BL and / BL are electrically connected to each other.

Further, since the equalizing signal EQ is also at the high level, the precharge n
Since the MOS transistor 203 and the equalizing nMOS transistor 204 are turned on, each bit line pair BL, / BL is precharged to the precharge potential VBP. Similarly, also in the sense amplifier driver circuit 21, the precharge nMOS transistor 214 and the equalization nMOS transistor 215 are in the ON state and the sense amplifier drive signal SE is in the low level inactive state. Both the 211 and the pMOS switch transistor 213 are off, and the power supply potential SAP for sense amplifier and the ground potential SAN for sense amplifier are both precharged to the precharge potential VBP.

On the other hand, in the sense amplifier ground circuit 23 shown in FIG. 4, since the sense amplifier drive signal SE is at the low level, the ground potential control signal NSG from the control signal generation circuit 232 goes to the high level, The potential DSG is short-circuited to the first potential, the ground potential, by the second nMOS transistor 231b in the ON state.

In the reference potential generation circuit 234, since the second nMOS transistor 234c is in the off state due to the low level of the sense amplifier drive signal SE, the reference potential VREF becomes almost the power supply potential VDD.

Since the detection circuit control signal NAMP from the control signal generation circuit 232 is at a high level, DSG
The differential amplifier of the level detection circuit 235 becomes inactive, and furthermore, the third nMOS transistor 2 in the ON state
By 35f, the output signal AMPO is fixed at a low level. Since the trigger output signal PSG also becomes low level by the low level output signal AMPO, the first to third signals are output.
All pMOS transistors 237d to 237f are turned off.

As described above, in the precharge period shown in the first period T1, the sense amplifier ground circuit 23
Sets the dynamic sense amplifier ground potential DSG to the ground potential, and further sets the control signal generation circuit 232, the reference potential generation circuit 234, and the DSG level detection circuit 23
5. Since a steady current does not flow through any of the Schmitt trigger circuit 236 and the DSG precharge circuit 237, no current is consumed.

Next, the operation in the second period T2 will be described.

As shown in FIG. 6, at time ta, internal strobe signal / RAS transitions from high level to low level, and at time tb after a predetermined time, for example, second shared gate signal SS2 changes from high level to low level. , The second transfer transistor 208 shown in FIG. 3 is turned off. Thus, the first or second shared gate signal SS1, SS
2 controls the sense amplifier circuit 201 to open one of the bit line pairs BL and / BL extending from both sides of the sense amplifier circuit 201 at a timing other than the precharge period.

Further, at time tb, since equalizing signal EQ transitions from high level to low level, the precharging operation between bit lines BL and / BL, the power supply potential SAP for sense amplifier and the ground potential SAN for sense amplifier are performed. The precharge operation between and stops.

Next, at time tc, which is a predetermined time after time tb,
3, when the word line WL1 is selected from the plurality of word lines WLn shown in FIG. 3 by the row decoder 40 shown in FIG. 2 and the potential of the word line WL1 transitions from a low level to a high level, the memory of the memory cell A Cell transistor 51a is turned on, and charge redistribution of the accumulated charge is performed between bit complementary line / BL and memory cell capacitor 51b.

In the present embodiment, it is assumed that the memory cell A holds a low level. Therefore, the potential of the bit complementary line / BL becomes the precharge potential VBP after the word line WL1 is selected. Stabilizes at a slightly lower potential than Further, since the word line driver 41 for driving the word line shown in FIG. 2 does not boost the word line WLn, the high level of the word line WL1 is equal to the power supply potential VDD. At time tc, sense amplifier drive signal SE
Is low level, the DSG potential is equal to the ground potential VSS.
And remain short-circuited.

Next, the operation in the third period T3 will be described.

At time td, which is a predetermined time after time tc, when sense amplifier drive signal SE changes from low level to high level, nMOS switch transistor 211 and pM switch of sense amplifier driver circuit 21 shown in FIG.
The OS switch transistors 213 are both turned on. As a result, of the two drive lines of the sense amplifier driver circuit 21, the power supply potential VDD is supplied to the SAP wiring via the pMOS switch transistor 213, and the power supply potential VDD is supplied to the SAN wiring via the nMOS switch transistor 211. Since the DSG potential is supplied, two sets of p
The sense amplifier circuit 201 constituted by the MOS transistor 202p and the nMOS transistor 202n is activated, and thereby a small initial potential difference generated between the pair of bit lines BL and / BL is amplified.

The second nMOS transistor 234c of the reference potential generation circuit 234 shown in FIG. 4 is turned on by the activation of the sense amplifier drive signal SE. As a result, the second nMOS transistor 234c
PMOS transistor 2 having a lower current driving capability than
34a, the reference potential V fixed at the high level
REF falls to the threshold potential (= VTN3) of the second nMOS transistor 234c. At this time, as shown in FIG.
01 are activated at the same time, a large current instantaneously flows into the DSG node.
A slight voltage rise from S is shown.

Next, from time td, one of the delay times of the delay circuit 232a of the control signal generation circuit 232 shown in FIG.
ns, the internal control signal NS
Since G transitions from high level to low level, DSG
Second nMOS transistor 23 of driver circuit 231
1b is turned off. At this time, the NAND circuit 232
b changes from the high level to the low level, thereby causing the third nMOS transistor 2 in the DSG level detection circuit 235 to change.
Since 35f is turned off and the first pMOS transistor 235a is turned on, the DSG level detection circuit 235 is activated.

Next, during the period from time te to time tf in the third period T3, the activated DSG level detection circuit 235 compares the reference potential VREF with the DSG potential. Immediately after time te, the DSG potential becomes VRE.
Since the potential is lower than the F potential, the output signal AMPO of the DSG level detection circuit 235 goes high, and the trigger output signal PSG is output via the Schmitt trigger circuit 236.
Becomes high level, the DSG precharge circuit 23
7 starts supplying the precharge current to the DSG node. As a result, the DSG potential quickly rises due to the precharge current and the current flowing from the sense amplifier circuit 201. At this time, at least one of the first to third memory capacity designation signals MEM0 to MEM2 is in the ON state.

Next, the operation in the fourth period T4 will be described.

At time tf, when the DSG potential rises above the first threshold potential VTN1, the trigger output signal PSG goes low, and the current supply from the DSG precharge circuit 237 stops. At this time, the potential of the bit complementary line / BL has fallen to substantially the same level as the DSG potential.
Since the amount of current flowing into the node decreases, the rise of the DSG potential stops near the first threshold potential VTN1, which is the second potential.

Here, the value of the first threshold potential VTN1 is
In the Schmitt trigger circuit 236, the threshold value is set to be substantially equal to the threshold value of the first nMOS transistor 231a of the DSG driver circuit 231, and at time tf
The DSG potential thereafter becomes the first threshold potential VTN by the clamping action of the first nMOS transistor 231a.
It is kept at a potential near 1.

Further, in the fourth period T4, the DSG potential once increased to the first threshold potential VTN1 then gradually decreases due to the sub-threshold leakage current of the first nMOS transistor 231a. Therefore, the DSG potential becomes the second threshold potential VTN2
If it becomes lower, the DSG level detection circuit 235 detects the lowered DSG potential, activates the DSG precharge circuit 237 again, and performs an operation of boosting the DSG potential to the first threshold potential VTN1. This step-up operation is intermittently repeated in the fourth period T4, so that the DSG
The potentials are the second threshold potential VTN2 and the first threshold potential VTN
1 is maintained.

When the sense amplifier circuit 201 completes the amplifying operation of amplifying the potential difference between the pair of bit lines BL and / BL, the potential of the bit complementary line / BL on the lower potential side becomes the sense amplifier ground potential SAN. , Ie DS
The potential becomes equal to the G potential and becomes a potential between the second threshold potential VTN2 and the first threshold potential VTN1. On the other hand, the potential of the bit line BL on the high potential side is a potential lower than the VDD potential supplied from the SAP wiring by the threshold potential of the first transfer transistor 207.

Next, the operation in the fifth period T5 will be described.

Immediately before the end of fourth period T4, internal strobe signal / RAS transitions from low level to high level, and at time tg thereafter, word line signal WL
When 1 transitions from the high level to the low level and the memory cell transistor 51a is turned off, the bit line / BL electrically connected via the memory cell transistor 51a and the memory cell capacitor 51b are connected. Is disconnected, the potential of bit complementary line / BL at time tg is held as the storage potential of memory cell A.

As in the present embodiment, bit complementary line / BL
Is on the low voltage side of the pair of bit lines BL and / BL, the storage potential of the memory cell A becomes equal to the DSG potential at the time tg, and therefore the potential between the second threshold potential VTN2 and the first threshold potential VTN1 is Potential.

Next, at the time th after a predetermined time from the time tg,
, The sense amplifier drive signal SE changes from the high level to the low level. Thereby, the second nMOS transistor 234c of the reference potential generation circuit 234 shown in FIG. 4 is turned off, and the reference potential VREF becomes pM
The voltage is boosted to the power supply potential VDD by a current flowing through the OS transistor 234a.

At the same time, since the detection circuit control signal NAMP from the control signal generation circuit 232 transitions from the low level to the high level, the DSG level detection circuit 235 becomes inactive.

Next, at time ti, which is a predetermined time after time th,
, The second shared gate signal SS2 transitions from the low level to the high level, so that the second transfer transistor 208 shown in FIG. 3 is turned on.
At this time, since the equalizing signal EQ also transits from the low level to the high level, the bit line pair BL, / BL is precharged to the precharge potential VBP and the SAN
The wiring for SAP and the wiring for SAP are also precharged to the precharge potential VBP.

Next, the operation in the sixth period T6 will be described.

At time tj after a lapse of 1 ns from time th, ground potential control signal NSG shown in FIG. 4 transitions from high level to low level. Thereby, the second nMOS transistor 231b of the DSG driver circuit 231
Is turned on, and the DSG potential becomes the ground potential VSS, so that the charges that have been accumulated on the DSG potential wiring are extracted to the ground potential side. The operation state of the circuit in the subsequent sixth period T6 is the same as the operation state in the first period T1 described above.

Hereinafter, the effect of the DSG potential that dynamically changes in accordance with the operation state of the semiconductor memory device according to the present embodiment will be described.

FIGS. 7A and 7B are graphs showing how the potential of the dynamic sense amplifier ground (DSG) according to the present embodiment changes. FIG. 7A shows D for comparison.
This shows a case where the SG potential is fixed to the ground potential, and (b) shows a DSG potential when the sense amplifier ground circuit according to the present embodiment is used. FIGS. 7A and 7B
Compares the potential waveforms of the bit line pair BL, / BL, the sense amplifier ground potential SAN, and the sense amplifier power supply potential SAP when the sense amplifier circuit is driven. Here, the times tc and tc shown in FIGS.
Each timing of d and te is the same as the time shown in FIG.

As shown in FIG. 7B, the time from time td which is the drive timing of the sense amplifier circuit 201 to time te which is the activation time of the DSG level detection circuit 235 of the sense amplifier ground circuit 23 is 1 ns. Since the time is extremely short, the low-level potential of the bit line pair BL, / BL becomes the threshold potential VTN of the nMOS transistor.
Does not drop much below the potential of As a result, for example, the first bias voltage value VGS1 of the memory cell transistor 502 in the memory cell 500 shown in FIG. 16 is always maintained at about VTN or higher.

As described above, the first bias voltage value VGS1 shown in FIG. 16 corresponds to the memory cell transistor 502 in which the word line WL is at the low level and the word line WL is in the non-selected state.
And the sub-threshold leakage current flowing in the channel direction increases as the first bias voltage value VGS1 increases.
Exponentially smaller. Since the sub-threshold leak current flows in a direction in which the data held in the memory cell capacitor 501 is destroyed, a large first bias voltage value VGS1 can be secured by using the sense amplifier ground circuit 23 according to the present embodiment, and the sub-threshold leak current is reduced. The current can be reduced. As a result, the charge retention characteristics of the DRAM can be improved.

Further, as described above, the second bias voltage value VGS2 shown in FIG.
Indicates the bias value in the direction from the source to the gate of the first n-type transistor 511n. In a general cross-coupled sense amplifier circuit 510, the second bias voltage at the start of the operation of the sense amplifier circuit 510 is shown. The operating speed of the sense amplifier circuit 510 decreases as the value VGS2 decreases.

Further, the operating condition of the sense amplifier circuit 510 is that the value of the second bias voltage value VGS2 is larger than the threshold value of the first n-type transistor 511n.
The smaller the power supply voltage value, the second bias voltage value VGS2
And the second bias voltage value VG during normal operation
As S2 becomes smaller, low voltage operation of the DRAM becomes more difficult.

However, when the sense amplifier ground circuit 23 according to the present embodiment is used, the time td to the time te immediately after the activation of the sense amplifier circuit 201 is activated.
During this period, the DSG potential, the potential of the bit complementary line / BL, and the ground potential SAN for sense amplifier change in the same manner as the method of fixing the DSG potential to the ground potential shown in FIG. Therefore, the second bias voltage value V immediately after the start of the operation of the sense amplifier circuit 201
GS2 are equal to each other.

As a result, the sense amplifier ground circuit 23 according to the present embodiment does not lower the operation speed of the sense amplifier circuit 201 and has a sufficiently large second bias voltage value VGS2. Can be reliably reduced.

In addition, the sense amplifier ground circuit 23
Is DS when sense amplifier circuit 201 is inactive.
By short-circuiting the G potential to the ground potential VSS, the control signal generation circuit 232, the reference potential generation circuit 234,
Since all the circuit groups of the DSG level detection circuit 235, the Schmitt trigger circuit 236, and the DSG precharge circuit 237 are in an inactive state, steady current consumption is not performed. As a result, the sense amplifier ground circuit 23 according to the present embodiment can significantly reduce the current consumption related to the generation of the DSG potential in the standby state of the DRAM.

As shown in FIG. 7B, at time te
Activate the DSG precharge circuit 237 to start increasing the DSG potential.
In this case, the potential of the bit complementary line / BL does not drop to the DSG potential, and a current flows from the sense amplifier circuit 201 to the DSG node. in this way,
Since the second nMOS transistor 231b of the DSG driver circuit 231 is turned off with the current flowing from the sense amplifier circuit 201 to the DSG node, the charge subsequently flowing from the sense amplifier circuit 201 is accumulated in the DSG potential wiring. This contributes to the precharge operation of the DSG potential.

In an actual DRAM, since the amount of current flowing from the sense amplifier circuit 201 is extremely large,
Most of the charge that contributes to the SG potential precharge is supplied from the sense amplifier circuit 201. The current flowing from the sense amplifier circuit 201 is generated by the release of the charges accumulated in the pair of bit lines BL and / BL during the precharge period. At time te, most of the current necessary for boosting the DSG potential is reduced by the discharged charges. By using it, DS
New power consumption accompanying the switching of the G potential can be minimized.

As described above, according to the semiconductor memory device of this embodiment, the memory cell 51 and the bit line pair B
L, / BL and the low level potential applied to the sense amplifier circuit 201, that is, the sense amplifier ground potential SA
A sense amplifier ground circuit 23 that generates and outputs a dynamic sense amplifier ground potential DSG that dynamically and positively changes N is provided. The sense amplifier ground circuit 23 has the sense amplifier circuit 201 activated. Immediately after a predetermined period (1 ns from time td to te)
During this period, the DSG potential is kept substantially at the ground potential VSS, and after a lapse of a predetermined period, the potential on the low level side of the pair of bit lines BL and / BL is boosted while taking in the charge discharged from the sense amplifier circuit 201. Therefore, the sense amplifier circuit 2
Since the second bias voltage VGS2 required immediately after the activation of 01 is sufficiently large, the sense speed and the lower limit operation voltage are not sacrificed, and the above-mentioned memory cell 51 is not selected. First bias voltage value VGS
Since 1 can be made sufficiently large, the charge retention characteristics of the memory cell 51 do not deteriorate.

During the precharge period of the bit line pair BL, / BL, the sense amplifier ground circuit 23
Since no current is consumed except for grounding the potential, the current consumption of the entire DRAM is reduced as compared with the conventional boost sense amplifier ground system.

Hereinafter, the use of the first memory capacity designating signal MEM0, the second memory capacity designating signal MEM1, and the third memory capacity designating signal MEM02 externally input to the DSG precharge circuit 237 shown in FIG. The method and its effects will be described with reference to the drawings.

The DRAM according to the present embodiment is assumed to be a DRAM in which the physical memory capacity of the memory cell array block 10 can be changed. Therefore, these first to third
Are used as control signals for changing the memory capacity value.

FIG. 8 shows an example of a method of setting each MEM signal to the DSG precharge circuit 237 according to the present embodiment, and shows seven combinations of three MEM signals. For example, when only the first memory capacity designation signal MEM0 is at a high level, the memory capacity is designated as 1 Mbit or 2 Mbit, and the second memory capacity designation signal M
When only EM1 is at the high level, the memory capacity is 3M
Specified as a bit. In addition, pMOSTr. 237
d, pMOSTr. 237e and pMOSTr. 237
f is the first to third pMOS transistors 2 shown in FIG.
37d to 237f, respectively, and their gate widths are 200 μm, 400 μm, and 800 μm, respectively, so that the third pMOS transistor 237f has the largest current supply capability. Here, transistors that are activated when the trigger output signal PSG is at a high level are marked with a circle indicating an active state, and transistors that are not activated are marked with a cross indicating an inactive state.

As described above, a plurality of memory capacity designating signals ME
Since the sense amplifier ground circuit 23 to which M0 to MEM2 is input can change the current supply capability of the DSG precharge circuit 237 for each memory capacity of the DRAM, this is a case where the wiring capacity value of the DSG potential changes depending on the memory capacity. Also optimizes the DSG potential precharge capability,
An increase in power consumption can be suppressed.

Next, a modification of the method of using the memory capacity designation signal MEM will be described.

It is also possible to switch the current supply capability of DSG precharge circuit 237 in accordance with the number of sense amplifier circuits 201 when a plurality of sense amplifier circuits 201 are selectively activated by a column address input from the outside. And is effective.

Of the plurality of sense amplifier circuits 201, in a DRAM in which the number of the sense amplifier circuits 201 activated at one timing during the normal read operation or refresh operation is changeable, the sense amplifier circuits 201 activated simultaneously are used. 7B, the rise of the DSG potential immediately after the time te shown in FIG. 7B is delayed, so that the potential on the low level side of the bit line changes from the first threshold potential VTN1 between the time td and the time te. Is relatively long, the effect of improving the pause time may be reduced.

However, in the present modification, the first
To the third memory capacity designating signal MEM0 to MEM2, the current supply capacity of the DSG precharge circuit 237 can be selected in accordance with the number of simultaneously activated sense amplifier circuits 201. Since the speed can be maintained at the predetermined value, the potential holding characteristics can be more reliably improved.

In this embodiment, the cross-coupled sense amplifier circuit 201 is shown as an example as shown in FIG. 3, but the present invention is not limited to this, and the potentials of the memory cells and the bit lines are determined. Any circuit may be used as long as it is a circuit that amplifies a minute potential difference read to a line, and for example, a circuit configuration of a current mirror type or a current detection type may be used.

Similarly, bit line pair BL, / B shown in FIG.
Connection position of the L precharge nMOS transistor 203 or the equalization nMOS transistor 204;
The connection method and the like between the first data line 60 and the bit line BL or between the second data line 61 and the bit complementary line / BL are not limited to the configuration of the present embodiment, and the operation is essentially , The racing relationship with other signals may be changed before and after.

Further, the reference potential generation circuit 234 or the Schmitt trigger circuit 236 in the sense amplifier ground circuit 23 shown in FIG. 4 is only a description of the configuration and operation at the block level, and the configuration at the transistor level is not limited. .

The back gate potential VBB is set to about -1.
Although set to 0 V, if the potential is different from this potential, for example, the back gate potential VBB may be set to a ground potential without impairing the essence of the present invention, and the potential can be set to an appropriate value.

Although the first embodiment according to the present invention has been described above, the present invention is not limited to this embodiment, and various design changes can be made without departing from the spirit of the present invention. Needless to say. (Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 9 shows a layout configuration of a DRAM chip which is a semiconductor memory device according to the second embodiment of the present invention. As shown in FIG. 9, on a main surface of a DRAM chip 300, an interface circuit block 301 including a circuit group for controlling input / output of data to / from the outside, and a column of a plurality of memory cells provided in a matrix are provided. A column control block 302 including a circuit group for controlling memory cells in the direction, a row control block 303 including a circuit group for controlling memory cells in the row direction among a plurality of memory cells provided in a matrix, and a plurality of memories. A memory core block 304 having a cell array block and the like, a sense amplifier ground circuit 305 for generating a low level dynamic sense amplifier ground potential DSG such as a sense amplifier circuit, and a DSG driver circuit for supplying the DSG potential to the sense amplifier circuit and the like 306 are formed.

The memory core blocks 304 are provided at intervals in the direction in which the column control block 302 extends, and each includes a plurality of sense amplifier blocks 3 each including a plurality of sense amplifier circuits and a sense amplifier driver circuit.
07 and a plurality of memory cell array blocks 308 provided between the sense amplifier blocks 307 and having a plurality of memory cells each provided in a matrix.
It is composed of

The DSG driver circuit 306 corresponds to the DSG driver circuit 231 shown in FIG. 4 of the first embodiment, and includes a memory core block 304 and a column control block 3.
02 and adjacent to the side of the memory core block 304 opposite to the column control block 302.

The sense amplifier ground circuit 305 is connected to the first
4 corresponds to the control signal generation circuit 232 and the DSG potential compensation circuit 233 shown in FIG.

In FIG. 9, reference numeral 311 denotes a DRAM chip 3
The wirings extend at intervals in the row direction of the wiring layer at 00, for example, from about the same
A first DSG potential wiring 312 is formed to extend in the column direction of a wiring layer in the DRAM chip 300, and is a first DSG potential wiring composed of a plurality of metal wirings formed at relatively small intervals up to about twice. A second DSG potential wiring made of a metal wiring electrically connected at the intersection with the wiring 311; 313 is formed above the sense amplifier ground circuit 305 and the DSG driver circuit 306 so as to extend in the column direction; This is a third DSG potential wiring electrically connected to the first DSG potential wiring 311.

314 is a sense amplifier ground circuit 305
And the DSG driver circuit 306 is formed so as to extend in the column direction, and the sense amplifier ground circuit 30
5 and the internal control signal NS between the DSG driver circuit 306
A first NSG signal line 315 is formed of a metal line for transmitting G. A metal line 315 is formed in the upper layer of the memory core block 308 so as to extend in the row direction, and is electrically connected to the first NSG potential line 314. This is a second NSG potential wiring made of wiring. Here, as described later, the first
NSG potential wiring 314 and second NSG potential wiring 31
5 is formed as a second layer metal wiring of the DRAM chip 300, and the first to third DSG potential wirings 311 to 313 are formed as third layer metal wiring of the DRAM chip 300.

As described above, in this embodiment, DS
The G driver circuit 306 is provided on both sides of the memory core block 304.

As in the first embodiment shown in FIG. 6, the first to third DSG potential wirings 311 to 313 according to the present embodiment are connected to the time td which is the sense amplifier drive timing and the time after a predetermined time. In te, the DSG driver circuit 3
06 is short-circuited to the ground potential VSS. However, large currents that instantaneously flow from a large number of sense amplifier circuits that are activated at the same time cause the respective DSG potential wires 311 to 31
In order to cause a potential drop due to the wiring resistance of No. 3, DSG
The potential shows a slight potential rise especially near the activated sense amplifier circuit. This potential rise is caused by a relatively large distance from the DSG driver circuit 306,
This becomes remarkable in a portion where the wiring resistance component of the potential wirings 311 to 313 becomes large. As a result, when the potential rise becomes excessive, immediately after the activation of the sense amplifier circuit, FIG.
Since the second bias voltage value VGS2 shown in FIG.
This becomes a factor of deteriorating the driving capability of the sense amplifier circuit.

In order to suppress the potential rise, it is necessary to reduce the wiring resistance component of each of the DSG potential wirings 311 to 313 as much as possible.
In the case of 0, the DSG potential wirings 311 to 313 are formed in a mesh structure to reduce the wiring resistance, and the DSG driver circuits 306 are arranged on both sides of the memory core block 304.

As described above, when the DSG driver circuit 306 is provided on both sides of the memory core block 304, the average distance from the DSG driver circuit 306 to the sense amplifier circuit is smaller than when only one of the sides is provided. And the current flowing out of the sense amplifier circuit flows to both DSG driver circuits 306 in a distributed manner, so that the resistance component of each of the DSG potential wires 311 to 313 can be effectively reduced to half or less.

With such a layout configuration, for example, if all the sense amplifier circuits included in B among the plurality of sense amplifier blocks 307 are activated at the same time, Since the DSG driver circuit 306 is arranged at the same distance from the sense amplifier circuit and the DSG driver circuit 3,
06, the resistance values of the respective DSG potential wires 311 to 313 become substantially equal. As a result, the operating characteristics of the simultaneously activated sense amplifier circuits are less likely to vary, so that the read operation or write operation of the DRAM is stabilized.

FIG. 10 shows a partial cross-sectional structure of the DRAM chip according to the present embodiment, which is formed on the semiconductor substrate after package sealing along the CC line of the DRAM chip 300 shown in FIG. 9 and on the main surface thereof. FIG. In FIG. 10, a region D1 shows a cross-sectional configuration of a transistor of the DSG driver circuit 306, and a region D1
Reference numeral 2 denotes a cross-sectional configuration of a transistor of the sense amplifier driver circuit in the sense amplifier block 307.

The area E1 and the area E2 in the area D1
Respectively correspond to the second nMOS transistor 231b and the first nMOS transistor 231a in the DSG driver circuit 231 of the first embodiment shown in FIG. Regions E3, E4 and E5 in region D2
Is the nMOS switch transistor 21 in the sense amplifier driver circuit 21 of the first embodiment shown in FIG.
1. nMOS transistor 215 for equalization and pM
Each corresponds to the OS switch transistor 213.

As shown in FIG. 10, for example, an n-type well region 351 is formed in a semiconductor substrate 350 made of silicon, and a p-type well region 352 is selectively formed in the n-type well region 351. I have.

An element isolation region 353 made of an insulating film or the like is selectively formed on the main surface of the semiconductor substrate 350. On the respective regions E1, E2, E3 and E4 of the semiconductor substrate 350, N-type diffusion regions 354 are formed at intervals from each other, and p-type diffusion regions 355 are formed at intervals above region E5.

[0148] In addition, the region between the diffusion regions 354 and 355 on the main surface of the semiconductor substrate 350 is straddled.
Insulated gate electrodes 356A, 356B, 356C, 356D and 356E made of polysilicon in order from the region E1.
Are formed respectively.

On the upper surface of first interlayer insulating film 357 formed over the entire surface of semiconductor substrate 350, first layer metal interconnections 358A to 358E connected to contacts provided on first interlayer insulating film 357 are formed. Is formed,
Wirings 358A and 358C indicate a VSS potential wiring for supplying a ground potential VSS, a wiring 358B indicates a DSG potential wiring for supplying a DSG potential, 358D indicates an EQ signal wiring for supplying an equalizing signal, and 358E indicates a power supply potential VDD. The VDD potential wiring to be supplied is shown.

On the upper surface of second interlayer insulating film 359 formed over the entire surface of first layer metal interconnections 358A to 358E, the first layer is formed via vias provided in second interlayer insulating film 359. Second layer metal wirings 360A to 360E are formed to be selectively connected to metal wirings 358A to 358E, and wiring 360A is connected to DSG driver circuit 30.
6, an NSG signal line for supplying the internal control signal NSG, a line 360B indicates an SE signal line for supplying the sense amplifier drive signal SE, and a line 360C indicates a SAN potential line for supplying a sense amplifier ground potential SAN.
A wiring 360D indicates an SAP potential wiring for supplying the power supply potential SAP for the sense amplifier, and a wiring 360E indicates a / SE signal wiring for supplying a complementary signal / SE of the sense amplifier driving signal SE.

The upper surface of the third interlayer insulating film 361 formed over the entire surface of the second layer metal interconnections 360A to 360E is provided on the upper surface of the third interlayer insulating film 361 via a via provided in the third interlayer insulating film 361. A DSG potential wiring 362 for supplying a DSG potential is formed by a third-layer metal wiring selectively connected to the metal wirings 360A to 360E. This DSG potential wiring 362 corresponds to second DSG potential wiring 312 shown in FIG.

The NSG signal line 360A corresponds to the first NSG potential line 314 shown in FIG. 9, and is connected in parallel with the gate electrode 356A at a location not shown, so that an effective wiring of the gate electrode 356A is provided. Resistance is suppressed.

The substrate potential VDD is applied to the n-type well region 351, and the back gate potential VBB lower than the ground potential VSS is applied to the p-type well region 352.

In a normal DRAM, in order to reduce power consumption in a standby state, a back gate potential VBB is applied to the entire surface of the memory cell array block and the nMOS transistor forming regions of the sense amplifier circuit and the sense amplifier driver circuit. The used p-type well is used. Further, the DRAM chip 30 according to the present embodiment
As described above, 0 applies the VBB potential to the entire surface of the p-type well region of the DSG driver circuit in order to alleviate the decrease in the DSG potential due to the off-leak current.

FIG. 11 shows the DRAM chip 300 shown in FIG.
2 shows a layout configuration in which a region F surrounding the line CC in FIG. In FIG. 11, the same components as those shown in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 11, reference numeral 320 denotes a sense amplifier circuit forming the sense amplifier block 307, and 3
Reference numeral 21 denotes a sense amplifier driver circuit.

Also, the DSG driver circuit 3 shown in FIG.
In FIG. 6, the hatched regions in the sense amplifier block 307 and the memory cell array block 308 indicate the p-type well region to which the back gate potential VBB is applied. Therefore, as shown in FIG. 11, in the sense amplifier 320 and the sense amplifier driver 321 of the sense amplifier block 307, the nMOS transistor is formed in the p-type well region to which the back gate potential VBB is applied. Are formed in the n-type well region.

Transistors formed in well regions of different conductivity types need to be formed at predetermined intervals from each other in order to avoid problems such as latch-up.

In the present embodiment, the DSG driver circuit 306 is connected to the memory core block 3 as shown in FIG.
04 and the DSG driver circuit 30
6, sense amplifier 320 and sense amplifier driver 32
1 are adjacent to each other, but also in regions adjacent to each other, p is applied with the back gate potential VBB potential.
Since the mold well is formed, the well can be shared. As a result, it is not necessary to form transistors at an interval from each other, so that the degree of integration of a chip can be improved. (Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 12 shows a circuit configuration of a sense amplifier ground circuit in a semiconductor memory device according to the third embodiment of the present invention. The sense amplifier ground circuit 24 shown in FIG.
Driving the SG, a DSG driver circuit 241 as a ground potential generation unit and a threshold potential generation unit, a control signal generation circuit 242 as a ground potential control unit, and D as a potential compensation unit
SG potential compensating circuit 243.

The DSG potential compensating circuit 243 provides the reference potential V
A reference potential generation circuit 244 as a reference potential generation unit for generating REF2; a DSG precharge circuit 245 as current supply capability switching means for supplying a DSG potential boosting current to the DSG driver circuit 241; (VREF2 node),
The drain is connected to the DSG precharge circuit 245,
The source is connected to the DSG driver circuit 241,
And a DSG level detection transistor 246 composed of an nMOS transistor for detecting a potential.

The DSG driver circuit 241 includes a first nMOS transistor 241a as a threshold potential generating semiconductor element having a gate and a drain commonly connected to a DSG node having a DSG potential, and the first nMOS transistor 2
The second nMO as a ground potential generating semiconductor element which is connected in parallel with the reference potential 41a and receives the ground potential control signal NSG from the control signal generation circuit 242 and sets the DSG potential to the ground potential.
And an S transistor 241b.

Control signal generating circuit 242 receives sense amplifier drive signal SE and receives sense amplifier drive signal SE.
A delay circuit 242a that outputs a delay signal given a predetermined delay time, for example, a delay time of 1 ns, a ground potential control signal that receives an output signal of the delay circuit 242a and inverts the received output signal An NSG output inverter circuit 242b.

The reference potential generation circuit 244 has an input terminal connected to the internal control signal NS from the control signal generation circuit 242.
PMOS transistor 244a and first nMOS transistor 244b forming an inverter circuit receiving G
A second nMOS transistor 244c having a gate and a drain commonly connected to the output terminal of the inverter circuit and the gate of the DSG level detection transistor 246;
The gate and the drain of the second nMOS transistor 24
4c, which is commonly connected to the source of FIG.
NMOS transistor 244d. here,
The size of the pMOS transistor 244a is the second nM
The configuration is smaller than the sizes of the OS transistor 244c and the third nMOS transistor 244d.

The DSG precharge circuit 245 has a first memory capacity designating signal ME whose input terminal is externally input.
A first inverter circuit 245a receiving M0 and a second memory capacity designating signal ME having an input terminal inputted from outside.
A second inverter circuit 245b receiving M1 and a third memory capacity designating signal ME whose input terminal is externally input.
And a third inverter circuit 245c receiving M2. Further, the first embodiment receives the power supply potential VDD at the source, outputs the DSG potential at the drain, and receives the outputs of the first to third inverter circuits 245a to 245c in this order. A first pMOS transistor 245 selectively activated to conform to the core configuration or operation specifications of the DRAM in the same manner as described above.
d, the second pMOS transistor 245e and the third pMOS transistor 245e.
It has a MOS transistor 245f.

The DSG driver circuit 24 according to the present embodiment
In the substrate of the first nMOS transistor 241a and the second nMOS transistor 241b in FIG.
Since the back gate potential VBB of about 0 V is applied, a decrease in the DSG potential due to the sub-threshold leakage current is suppressed. Similarly, the reference potential generation circuit 2
The same back gate potential VBB is applied to the substrate of the second nMOS transistor 244c, the third nMOS transistor 244d, and the DSG level detection transistor 246 in 44, and the respective nMOS transistors having the back gate potential VBB applied to the substrate Have the same threshold voltage VTN.

Hereinafter, the operation of the sense amplifier ground circuit 24 configured as described above will be described with reference to the drawings.

FIG. 13 is a timing chart of the sense amplifier ground circuit 24 according to the present embodiment. Here, the sense amplifier ground circuit 2 according to the present embodiment
The configuration of the DRAM except for the configuration 4 is the same as the configuration shown in FIG. 2 of the first embodiment. The internal strobe signal / RAS, the first and second shared gate signals SS1 and SS2, the equalize signal EQ, the word line signal WL1, and the sense amplifier drive signal SE shown in FIG. 13 are all shown in FIG. The timings are the same as the corresponding signals, and the timing times ta to tj are also the same time axes.

Explaining only the differences from the first embodiment, first, in the period from the DRAM precharge period to time td, the sense amplifier drive signal SE is at the low level, and the control signal generation circuit 242 , The ground potential control signal NSG output from the reference potential generating circuit 244 becomes high level.
a is turned off and the first nMOS transistor 2
Since 44b is turned on, the reference potential VREF2 becomes the ground potential.

The DSG precharge circuit 245 includes
The first to third pMOS transistors 245d to 245d selected by the third memory capacity designation signals MEM0 to MEM2
245f is always on, but V
Since the REF2 node is grounded and the DSG level detection transistor 246 is turned off, the DSG
Precharge circuit 245 does not supply current to DSG driver circuit 241. At this time, the second nMOS transistor 241b of the DSG driver circuit 241
Receives the high-level ground potential control signal NSG, the DSG potential becomes the ground potential VSS.

Next, at time td, the sense amplifier drive signal SE changes from low level to high level. Thereafter, at a predetermined time generated by the delay circuit 242a of the control signal generation circuit 242, for example, at a time te after the elapse of 1 ns, the ground potential control signal NSG transitions from the high level to the low level. As a result, the DSG potential is changed to the ground potential VS
The second n of the DSG driver circuit 241 short-circuited with S
MOS transistor 241b is turned off.

On the other hand, in the reference potential generation circuit 244, the pMOS transistor 244 of the inverter circuit
a is turned on, and the first nMOS transistor 24
4b is turned off. At this time, the reference potential VREF2
Are a pMOS transistor 244a and a second nMOS
The potential stabilizes at the potential determined by the ratio of the current driving capabilities of the transistor 244c and the third nMOS transistor 244d, but the pMOS transistor 244a has the second and third nMOS transistors 244d.
Since the transistor size is smaller than MOS transistors 244c and 244d, reference potential VREF
The stable potential of the second nMOS transistor 244c
And the sum of the threshold potentials of the third nMOS transistor 244d is 2 VTN.

At this time, in the DSG level detection transistor 246, while the DSG potential as the source potential slightly rises due to the current flowing from the sense amplifier circuit, the reference potential VREF2 as the gate potential becomes 2 VTN from the ground potential. To be turned on. As a result, current starts to be supplied from the DSG precharge circuit 245 to the DSG node.

As described above, during the period from time te to time tf, the DSG potential is quickly changed by the currents flowing from the plurality of simultaneously activated sense amplifier circuits and the current supplied from the DSG precharge circuit 245. To rise.

Next, at time tf, when the DSG potential rises to the threshold potential VTN, the bias voltage between the source and the gate of the DSG level detection transistor 246 drops to the threshold potential VTN. The current supply to the DSG node is cut off again.

Further, when the DSG potential becomes higher than the threshold potential VTN, the first nMOS transistor 241a of the DSG driver circuit 241 is turned on, so that the excess accumulated charge on the DSG potential wiring becomes the ground potential. Since the potential of the bit complementary line / BL has fallen to substantially the same potential as the DSG potential during the period from time tf to time tj during the first operation to be pulled out, the sense amplifier circuit flows into the DSG node. Due to the second action in which the amount of current decreases, the DSG potential after time tf stabilizes near the threshold potential VTN.

As described above, during the period from time tf to tj, the DSG potential is clamped near the threshold potential VTN, but the first nMOS transistor 241a and the second nMOS transistor 241a of the DSG driver circuit 241 are provided.
If the DSG potential drops below the threshold potential VTN due to the influence of the sub-threshold leakage current 1b or external noise, the DSG level detection transistor 246 is turned on and the DSG precharge circuit
By supplying a current to the G node, the DSG potential is raised to the threshold potential VTN.

Next, at time th, the sense amplifier drive signal SE changes from the high level to the low level. Then, at time tj after a predetermined time generated by the delay circuit 242a of the control signal generation circuit 242, the ground potential control signal SE is generated. Since the signal NSG changes from low level to high level,
The second nMOS transistor 241b of the DSG driver circuit 241 is turned on, and the DSG potential becomes the ground potential VSS.

In the reference potential generation circuit 244, the pMOS transistor 244a is turned off and the first nMOS transistor 244b is turned on, so that the reference potential VREF2 is short-circuited to the ground potential VSS. Detection transistor 24
6 is turned off and the DSG precharge circuit 245
Current supply to the DSG node is stopped.

As described above, the sense amplifier ground circuit 24 according to the present embodiment has the DSG level detection transistor 246 instead of the DSG level detection circuit 235 of the sense amplifier ground circuit 23 according to the first embodiment. ing. This uses the property that the current driving capability of the DSG level detection transistor 246 decreases as the DSG potential approaches the predetermined potential VTN.

The DSG level detection transistor 24
Numeral 6 controls the amount of the precharge current supplied from the DSG precharge circuit 245 to the DSG node, so that there is no propagation delay from the DSG potential detection operation to the precharge operation, and the precharge current The extra consumption of can be kept very small.

Further, since the precharge current supplied to the DSG node changes in an analog manner in accordance with the DSG potential, the sense amplifier ground circuit 2 according to the first embodiment is changed.
Since the fluctuation of the DSG potential can be suppressed as compared with 3, the variation in the amount of charge stored in the memory cell of the DRAM to which the low data has been written is less likely to occur.

Further, there is no need to provide the DSG level detection circuit 235 and the Schmitt trigger circuit 236 according to the first embodiment.
Since the operating current of the four main bodies can be reduced, the layout size of the circuit can be reduced, so that a DRAM with low power consumption and high integration can be realized. (Fourth Embodiment) Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 14 shows a circuit configuration of a sense amplifier ground circuit in a semiconductor memory device according to the fourth embodiment of the present invention. The sense amplifier ground circuit 25 shown in FIG.
Driving the SG, a DSG driver circuit 251 and a DSG sub-driver circuit 252 as a ground potential generation unit and a threshold potential generation unit, a control signal generation circuit 232 as a ground potential control unit, and a DSG potential compensation circuit as a potential compensation unit 2
33 and the ground potential control signal NSG from the control signal generation circuit 232, and
DSG driver switching circuit 253 as a threshold potential generation semiconductor element selecting means for selecting sub-driver circuit 252
Consists of Here, the control signal generation circuit 232 and the DS
The G potential compensation circuit 233 has the same circuit configuration as that of the first embodiment.

The DSG driver circuit 251 includes a first nMOS transistor 251a as a first threshold potential generating semiconductor element having a gate and a drain commonly connected to one input terminal of the DSG driver switching circuit 253, and the first nMOS transistor 251a.
And a second nMOS transistor 251b as a ground potential generating semiconductor element receiving the ground potential control signal NSG from the control signal generation circuit 232 and setting the output potential to the ground potential.

The DSG sub-driver circuit 252 comprises an nMOS transistor 252a as a second threshold potential generating semiconductor element having a gate and a drain commonly connected to another input terminal of the DSG driver switching circuit 253.

DSG driver switching circuit 253 has one input terminal receiving ground potential control signal NSG from control signal generation circuit 232 and the other input terminal providing a predetermined delay time to ground potential control signal NSG. Circuit 25
3a, and an OR circuit 235b for receiving the delay signal from 3a and outputting an internal selection signal DSEL;
EL, a source receives an output signal from the DSG driver circuit 251, a drain is connected to the first nMOS transistor 253c connected to the DSG node, and a gate is inverted through an inverter circuit 253d.
SEL is received and the source is the DSG sub-driver circuit 252
And a second nMOS transistor 253e having a drain connected to the DSG node.

Here, the DSG driver circuits 251 and D
A back gate potential of about -1.0 V is applied to the substrate of the SG sub-driver circuit 252. Also, the nMOS transistor 252a of the DSG sub-driver circuit 252
Is the size of the first nMOS of the DSG driver circuit 251.
It is smaller than the size of the transistor 251a.

Hereinafter, the operation of the sense amplifier ground circuit 25 configured as described above will be described with reference to the drawings.

FIG. 15 is a timing chart of the sense amplifier ground circuit 25 according to the present embodiment. Here, the sense amplifier ground circuit 2 according to the present embodiment
The configuration of the DRAM except for the configuration 5 is the same as the configuration shown in FIG. 2 of the first embodiment.

First, during the period from the precharge period of the DRAM shown in FIG. 15 to time tk, the internal selection signal DSEL of the DSG driver switching circuit 253 is set to the level shown in FIG.
4 is a signal obtained by delaying the fall timing of the ground potential control signal NSG from the control signal generation circuit 232 shown in FIG. In this period, since the internal selection signal DSEL is at the high level, the first nMOS transistor 253c of the DSG driver switching circuit 253 shown in FIG.
Is turned on, and the second nMOS transistor 253 is turned on.
e is turned off. For this reason, the DSG node
Is electrically connected to the DSG driver circuit 251 via the nMOS transistor 253c. Therefore, during this period, the DSG driver circuit 251 short-circuits the DSG potential to the ground potential VSS during the period from the DRAM precharge period to time te;
An operation of raising the DSG potential to a predetermined threshold potential by a clamping action until k is performed.

Next, at time tk which is a timing after a predetermined time generated by delay circuit 253a of DSG driver switching circuit 253 from time te which is the transition time of ground potential control signal NSG to low level, internal selection signal DSEL transitions from high level to low level. Thereby, the DSG driver switching circuit 253 shown in FIG.
The first nMOS transistor 253c is turned off, and the second nMOS transistor 253e is turned on. Therefore, the DSG node is connected to the DSG sub-driver circuit 252 via the second nMOS transistor 253e.
Is electrically connected to The DSG potential after time tk is
The threshold potential of the first nMOS transistor 251a of the DSG driver circuit 251 has risen to the vicinity of a threshold potential VTN substantially equal to the threshold potential thereof, and the low level potential of the bit complementary line / BL has dropped to the DSG potential.

As a result, the amount of current flowing from the DSG potential compensating circuit 233 or the sense amplifier circuit in the active state to the DSG sub-driver circuit 252 is reduced, and is compared with the first nMOS transistor 251a of the DSG driver circuit 251. And the nMOS transistor 252a of the DSG sub-driver circuit 252 having a small size.
However, the DSG potential can be stably held near the threshold potential VTN.

Next, at time tj, internal control signal N
When both SG and the internal selection signal DSEL transition from low level to high level, the DSG node is electrically connected to the DSG driver circuit 251 via the first nMOS transistor 253c of the DSG driver switching circuit 253. Further, the DSG potential after time tj is changed to the second nMOS transistor 251 of the DSG driver circuit 251.
short-circuited to the ground potential VSS via b.

As described above, the sense amplifier ground circuit 25 according to the present embodiment includes the DSG driver circuits 251 and the DSG driver sub-circuits 252 having different current driving capabilities, and the DSG driver switching circuit 253 for selecting these. Therefore, immediately after time td, which is the drive timing of the sense amplifier, or the DSG potential compensation circuit 233
Is activated and D is raised immediately after the time te when the DSG potential is boosted.
During the period when a large current flows into the SG node, DS
By using a transistor having a relatively large size for the G driver circuit 251, an excessive increase in the DSG potential can be suppressed, so that the DSG potential is reliably stabilized.

Further, the DSG potential after time te when DSG potential compensating circuit 233 is activated and bit line pair BL, /
After the low-level potential of BL is stabilized near the threshold potential VTN substantially equal to the threshold of the first nMOS transistor of the DSG driver circuit 251, the DSG sub-driver circuit having a small transistor size as a driver circuit By selecting and using 252, it is possible to suppress a decrease in the DSG potential due to a leak current via the DSG driver circuit 251.

As described above, the sense amplifier ground circuit 25 according to the present embodiment is different from the sense amplifier ground circuit 23 according to the first embodiment in that the leakage current between the operation times tf to tj shown in FIG. Since the decrease in the DSG potential due to the current can be suppressed, the consumption amount of the precharge current for compensating the DSG potential can be reduced. Power consumption when performing the above.

[0197]

According to the semiconductor memory device of the present invention,
When the memory cell includes a capacitor for holding data and a switch transistor in which access between the capacitor and the bit line is controlled by a word line, a low-level potential is applied to a memory cell connected to an unselected word line. Since the threshold voltage of the semiconductor device for generating a threshold potential, which is the potential of 2, is substantially equal to the threshold potential of the semiconductor element, the gate-drain voltage when the switch transistor is off increases, and the sub-threshold leakage current of the memory cell is reduced.
The charge retention characteristics of the memory cell are improved. In the case where the sense amplifier circuit includes a transistor, the low-level potential of the sense amplifier is substantially equal to the ground potential, which is the first potential, so that the gate-source voltage when the transistor is on increases. The sense lower limit voltage of the memory cell can be reduced without deteriorating the sense speed of the sense amplifier.

In the semiconductor memory device of the present invention, when the ground potential generating semiconductor element receives a control signal from the ground potential control unit and a part of the plurality of sense amplifier circuits is activated. When the first potential is generated by being activated for a predetermined period from the time when the threshold potential generating semiconductor element generates the second potential during a period in which the ground potential generating semiconductor element is not activated, When the operation of the selected sense amplifier rises, the low-level potential is substantially equal to the ground potential, which is the first potential, so that the gate-source voltage of the sense amplifier when the transistor is turned on is reliably increased.

In the semiconductor memory device of the present invention, the ground potential generating semiconductor element receives a control signal from the ground potential control unit, and during a period in which the plurality of sense amplifier circuits are inactive and in the plurality of sense amplifier circuits. The first potential is generated by being activated during a predetermined period from the time when some of the sense amplifier circuits are activated, and the semiconductor element for generating the threshold potential is activated when the semiconductor element for generating the ground potential is activated. If the second potential is generated during the non-active period, the low level potential becomes almost the first potential, that is, the ground potential even when the sense amplifier is inactive, so that the ground potential is generated during the memory standby period. As a result, the means for holding the ground potential is not required, and the current consumption of the low-level potential generating means can be suppressed, so that the apparatus configuration is simplified and the current consumption of the entire apparatus is reduced. Kill.

In the semiconductor memory device of the present invention, the low-level potential generating means generates a reference potential substantially equal to the threshold potential, and the low-level potential becomes higher than the reference potential. A potential compensating unit that compensates the low-level potential by supplying current to the
When the reference potential generator and the potential compensator operate during a period in which the ground potential generator is not activated, the reference potential generator and the potential compensator are in an inactive state during a period in which the low-level potential is the ground potential. Therefore, power consumption associated with driving at a low level potential can be extremely reduced.

In this case, the potential of the lower potential bit line of the bit line pair connected to the active sense amplifier circuit of the plurality of sense amplifier circuits is higher than the low level potential. When the ground potential generating unit transitions from the active state to the inactive state, a current flows from the activated bit line to the low-level potential wiring.
Since the amount of current from the potential compensator for boosting the low-level potential to the threshold potential can be reduced, the current consumption of the potential compensator can be reliably reduced.

In this case, if the potential compensator has current supply capability switching means for switching the current supply capability of the potential compensator in accordance with the memory capacity of the memory cell array, the potential compensator is provided for each storage capacity of the storage device. , The power supply capability of the low-level potential can be optimized even if the wiring capacitance value of the low-level potential changes depending on the memory capacity, thereby increasing power consumption. Can be suppressed.

In this case, the potential compensation unit switches the current supply capability of the potential compensation unit according to the number of sense amplifier circuits activated at one operation timing among the plurality of sense amplifier circuits. With the means, the current supply capability of the potential compensator can be selected according to the number of sense amplifier circuits activated at one operation timing, so that the number of sense amplifiers activated at one operation timing Therefore, even when the number is small, the rising speed of the low-level potential can be prevented from becoming slow, so that the potential holding characteristics of the memory cell can be more reliably improved.

In the semiconductor memory device according to the present invention, the low-level potential generating means includes a reference potential generating section for generating a reference potential almost twice as high as the threshold potential, and a current so that the low-level potential becomes substantially equal to the threshold potential. And a potential compensator for compensating for the low-level potential by supplying the potential. The potential compensator has a gate receiving the reference potential, a drain receiving a current from the potential compensator, and a source outputting the low-level potential. When the transistor includes a field effect transistor, the detection operation of the low level potential and the adjustment operation of the current supply amount of the current for boosting the low level potential are performed by one transistor, so that the transmission from the detection operation to the current supply operation is performed. Since no delay occurs, the precharge current for precharging to the compensation potential can be reduced. Further, since the precharge current changes in an analog manner in correspondence with the low-level potential, the fluctuation of the low-level potential can be suppressed, and thus the amount of charge stored in the memory cell in which the low data is written hardly varies.

In this case, the potential of the lower potential bit line of the bit line pair connected to the active sense amplifier circuit of the plurality of sense amplifier circuits is higher than the low level potential. When the ground potential generating unit transitions from the active state to the inactive state, a current flows from the activated bit line to the low-level potential wiring.
Since the amount of current from the potential compensator for boosting the low-level potential to the threshold potential can be reduced, the current consumption of the potential compensator can be reliably reduced.

In the semiconductor memory device of the present invention, the semiconductor element for generating a threshold potential includes a first semiconductor element and a second semiconductor element, and the low-level potential generation means includes a low-level potential higher than a ground potential. A potential compensating unit for compensating a low level potential by supplying a current so as to generate a threshold potential for receiving a control signal from a ground potential control unit and selecting a first semiconductor element or a second semiconductor element. When the semiconductor device further comprises a semiconductor element selecting means, the first semiconductor element or the second semiconductor element can be set to a low level potential higher than the ground potential depending on a period in which a large current flows through the sense amplifier and a period in which the large current does not flow. Therefore, if a semiconductor element having a relatively large size is used during a period in which a large current flows through the sense amplifier, an excessive rise in the low-level potential can be suppressed. In addition, when a semiconductor element having a relatively small size is used in a period during which a large current does not flow, a decrease in low-level potential due to a leakage current of the semiconductor element can be suppressed, so that current consumption of the potential compensation unit can be reduced.

In the semiconductor memory device of the present invention, a plurality of memory cell arrays are provided, and a plurality of sense amplifier circuits are provided so as to be adjacent to respective sides of each of the plurality of memory cell arrays which are parallel to the direction in which the word lines extend. A plurality of sense amplifier rows, and a memory core block including a plurality of memory cell arrays and a plurality of sense amplifier rows, and the low-level potential generation means is provided in a direction in which the plurality of sense amplifier rows in the memory core block extend. The low-level potential generation means can reduce the effective resistance value between the low-level potential generation means and each sense amplifier circuit, so that the voltage drop of the wiring resistance is reduced. , The sense speed is less likely to deteriorate. Further, since the plurality of simultaneously activated sense amplifier circuits are located at the same distance from the low-level potential generation means, the operating characteristics of the simultaneously activated sense amplifier circuits are less likely to vary, so that the storage device Read operation and write operation become stable.

In this case, the semiconductor element for generating the ground potential, the semiconductor element for generating the threshold potential, and the semiconductor element included in the sense amplifier array of the low-level potential generating means are formed in the shared wells respectively provided continuously on the semiconductor substrate. In this case, in the case of semiconductor elements (transistors) formed in wells of different conductivity types, it is necessary to form them at a predetermined distance from each other in order to avoid problems such as latch-up. Because of the well structure,
The degree of circuit integration can be improved.

[Brief description of the drawings]

FIG. 1 is a functional configuration diagram illustrating a dynamic sense ground system in a semiconductor memory device according to the present invention.

FIG. 2 is a partial block configuration diagram illustrating the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a memory cell array block, a sense amplifier block, and a sense amplifier driver circuit in the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a sense amplifier ground circuit in the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a conceptual diagram illustrating operation characteristics of a DSG potential compensation circuit in the semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a timing chart of the semiconductor memory device according to the first embodiment of the present invention.

FIGS. 7A and 7B show a change in the potential of a dynamic sense amplifier ground (DSG) potential according to the first embodiment of the present invention, and FIG. FIG. 7 is a potential waveform diagram when the voltage is fixed to
(B) is a potential waveform diagram when the sense amplifier ground circuit according to the first embodiment is used.

FIG. 8 is a list for explaining a method of setting each MEM signal for the DSG precharge circuit according to the first embodiment of the present invention.

FIG. 9 is a configuration diagram showing a layout of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view of a semiconductor memory device according to a second embodiment of the present invention, showing a semiconductor substrate after package sealing along line CC of FIG. 9, elements formed on the main surface thereof, FIG. 2 is a cross-sectional view illustrating a configuration of a wiring.

FIG. 11 is a plan view of a semiconductor memory device according to a second embodiment of the present invention, and is an enlarged view of a region F surrounding the line CC in FIG. 9;

FIG. 12 is a circuit diagram showing a sense amplifier ground circuit in a semiconductor memory device according to a third embodiment of the present invention.

FIG. 13 is a timing chart of a sense amplifier ground circuit according to a third embodiment of the present invention.

FIG. 14 is a circuit diagram showing a sense amplifier ground circuit in a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 15 is a timing chart of a sense amplifier ground circuit according to a fourth embodiment of the present invention.

FIG. 16 is a partial circuit diagram showing a connection relationship between a non-selected memory cell of a general DRAM and an activated sense amplifier.

FIG. 17 is a functional configuration diagram for explaining a boost sense ground system in a conventional DRAM.

FIGS. 18A and 18B show potential changes of a bit line pair, a sense amplifier ground potential SAN and a sense amplifier power supply potential SAP during a read operation by a sense amplifier, and FIG. FIG. 7 is a potential waveform diagram when no voltage is used, and FIG. 7B is a potential waveform diagram when a boost sense ground system is used.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Internal circuit 2 Low level electric potential generation means 3 DSG driver circuit (ground electric potential generation part and threshold electric potential generation part) 31 1st nMOS transistor (semiconductor element for threshold electric potential generation) 32 2nd nMOS transistor (semiconductor for ground electric potential generation) 4) Control signal generation circuit (ground potential control unit) 5 DSG potential compensation circuit (potential compensation unit) 6 DSG potential wiring 10 memory cell array block 20 sense amplifier block 21 sense amplifier driver circuit 22 control circuit block 23 sense amplifier ground circuit ( Low-level potential generating means) 24 sense amplifier ground circuit (low-level potential generating means) 25 sense amplifier ground circuit (low-level potential generating means) 40 row decoder 41 word line driver 42 sense amplifier control block 100 area 101 memory cell array Reference Signs List 51 memory cell 51a memory cell transistor 51b memory cell capacitor A memory cell 60 first data line 61 second data line 201 sense amplifier circuit 202n nMOS transistor 202p pMOS transistor 203 precharge nMOS transistor 204 equalizing nMOS transistor 205 first Internal wiring 206 second internal wiring 207 first transfer transistor 208 second transfer transistor 209 third transfer transistor 211 nMOS switch transistor 212 inverter circuit 213 pMOS switch transistor 214 precharge nMOS transistor 215 equalizing nMOS transistor 231 DSG driver circuit (ground potential generator and 231a First nMOS transistor (semiconductor element for generating threshold potential) 231b Second nMOS transistor (semiconductor element for generating ground potential) 232 Control signal generation circuit (ground potential control section) 232a Delay circuit 232b NAND circuit 232c Inverter circuit 233 DSG potential compensation circuit (potential compensation unit) 234 Reference potential generation circuit (reference potential generation unit) 234a pMOS transistor 234b first nMOS transistor 234c second nMOS transistor 235 DSG level detection circuit 235a first pMOS transistor 235b First drive transistor 235c Second drive transistor 235d First nMOS transistor 235e Second nMOS transistor 235f Third nMOS transistor 236 Schmitt trigger circuit 236a First pMOS transistor 236b First nMOS transistor 236c Second pMOS transistor 236d Second nMOS transistor 236e Third pMOS transistor 237 DSG precharge circuit (current supply capability switching means) 237a First NAND circuit 237b Second NAND circuit 237c Third NAND circuit 237d First pMOS transistor 237e Second pMOS transistor 237f Third pMOS transistor 241 DSG driver circuit (ground potential generation unit and threshold potential generation unit) 241a first NMOS transistor (semiconductor element for generating threshold potential) 241b Second nMOS transistor (semiconductor element for generating ground potential) 242 Control unit) 242a delay circuit 242b inverter circuit 243 DSG potential compensation circuit (potential compensation unit) 244 reference potential generation circuit (reference potential generation unit) 244a pMOS transistor 244b first nMOS transistor 244c second nMOS transistor 244d third nMOS Transistor 245 DSG precharge circuit (current supply capability switching means) 245a First inverter circuit 245b Second inverter circuit 245c Third inverter circuit 245d First pMOS transistor 245e Second pMOS transistor 245f Third pMOS transistor 246 DSG level detection transistor 251 DSG driver circuit (ground potential generator and threshold potential generator) 251a First nMOS transistor (first threshold) 251b Second nMOS transistor (ground potential generation semiconductor element) 252 DSG sub-driver circuit 252a nMOS transistor (second threshold potential generation semiconductor element) 253 DSG driver switching circuit (threshold potential generation semiconductor) 253a Delay circuit 253b OR circuit 253c First nMOS transistor 253d Inverter circuit 253e Second nMOS transistor 300 DRAM chip 301 Interface circuit block 302 Column control block 303 Row control block 304 Memory core block 305 Sense amplifier ground circuit 306 DSG driver circuit 307 Sense amplifier block 308 Memory cell array block 311 First DSG potential wiring 312 Second DSG power Wiring 313 Third DSG potential wiring 314 First NSG signal wiring 315 Second NSG potential wiring 320 Sense amplifier circuit 321 Sense amplifier driver circuit 350 Semiconductor substrate 351 N-type well region 352 P-type well region 353 Element isolation region 354 n Diffusion region 355 P-type diffusion region 356A Insulated gate electrode 356B Insulated gate electrode 356C Insulated gate electrode 356D Insulated gate electrode 356E Insulated gate electrode 357 First interlayer insulating film 358A VSS potential wiring 358B DSG potential wiring 358C VSS potential wiring 358D EQ signal Wiring 358E VDD potential wiring 359 Second interlayer insulating film 360A NSG signal wiring 360B SE signal wiring 360C SAN potential wiring 360D SAP potential wiring 360E / SE signal wiring 361 Third layer Inter-insulation film 362 DSG potential wiring DSG dynamic sense amplifier ground potential (low level potential) PSG trigger output signal NSG internal control signal VGS1 first bias voltage value VGS2 second bias voltage value WL word line or word line signal BL bit line / BL bit complementary line SE sense amplifier drive signal EQ equalize signal SAP sense amplifier power supply potential SAN sense amplifier ground potential VDD power supply potential VSS ground potential VBP precharge potential VCP cell plate potential VBB back gate potential (substrate potential) VTN1 first Threshold potential VTN2 Second threshold potential

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kiyoto Ota 1006 Kadoma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. F term (reference) 5B024 AA01 AA07 AA15 BA09 BA21 BA27 CA11 CA15 CA21 5F083 AD00 GA05 GA09 LA03 LA09

Claims (15)

[Claims] 1. A memory cell array formed on a semiconductor substrate and having a plurality of memory cells provided at respective intersections of a plurality of word lines and a plurality of bit line pairs; A plurality of sense amplifier circuits for amplifying and outputting a potential difference read to each bit line pair; and a high level potential and a low level potential applied to the memory cell, the bit line pair and the sense amplifier circuit. And a low-level potential generating means for generating and outputting a low-level potential, wherein the low-level potential generating means generates a first potential substantially equal to a ground potential as the low-level potential. A ground potential generating unit having an element, a threshold which operates when a potential exceeding a threshold potential is applied, and generates a second potential substantially equal to the threshold potential as the low level potential A semiconductor memory device comprising: a threshold potential generation unit having a value potential generation semiconductor element; and a ground potential control unit that controls an operation of the ground potential generation semiconductor element. 2. The semiconductor device for generating a ground potential receives a control signal from the ground potential control unit, and a predetermined period from a time when a part of the plurality of sense amplifier circuits is activated. And the threshold potential generation semiconductor element generates the second potential during a period in which the ground potential generation semiconductor element is not activated. 2. The semiconductor memory device according to claim 1, wherein: 3. The semiconductor device for generating a ground potential receives a control signal from the ground potential control unit, during a period in which the plurality of sense amplifier circuits are in an inactive state, and among the plurality of sense amplifier circuits. The first potential is generated by being activated during a predetermined period from the time when some of the sense amplifier circuits are activated, and the threshold potential generation semiconductor element is connected to the ground potential generation semiconductor. 2. The semiconductor memory device according to claim 1, wherein said second potential is generated during a period when an element is not activated. 4. The low-level potential generation means includes: a reference potential generation unit that generates a reference potential that is substantially the same as the threshold potential; and a current so that the low-level potential is higher than the reference potential. And a potential compensating unit that compensates for the low-level potential by supplying the reference potential generating unit and the potential compensating unit to operate during a period in which the ground potential generating unit is not activated. The semiconductor memory device according to claim 2, wherein: 5. The state in which a lower potential bit line of the bit line pair connected to an active sense amplifier circuit of the plurality of sense amplifier circuits has a potential higher than the low level potential. 5. The semiconductor memory device according to claim 4, wherein said ground potential generating section transitions from an active state to an inactive state when said state is in said state. 6. The device according to claim 4, wherein the potential compensator has current supply capability switching means for switching the current supply capability of the potential compensator in accordance with the memory capacity of the memory cell array. Semiconductor storage device. 7. The current supply capability for switching a current supply capability of the potential compensation unit according to the number of sense amplifier circuits activated at one operation timing among the plurality of sense amplifier circuits. 5. The semiconductor memory device according to claim 4, further comprising switching means. 8. The low-level potential generating means includes: a reference potential generating unit configured to generate a reference potential substantially twice as high as the threshold potential; and a current flowing such that the low-level potential is substantially equal to the threshold potential. A potential compensating unit that compensates for the low-level potential by supplying the potential compensating unit. The potential compensating unit has a gate receiving the reference potential, a drain receiving a current from the potential compensating unit, and a source 4. The semiconductor memory device according to claim 2, further comprising a field-effect transistor that outputs a low-level potential. 9. A state in which a lower potential bit line of the bit line pair connected to an active sense amplifier circuit of the plurality of sense amplifier circuits is higher than the low level potential. 9. The semiconductor memory device according to claim 8, wherein said ground potential generating section transitions from an active state to an inactive state when said state is in said state. 10. The device according to claim 8, wherein the potential compensator has current supply capability switching means for switching the current supply capability of the potential compensator in accordance with the memory capacity of the memory cell array. Semiconductor storage device. 11. The current supply capability for switching a current supply capability of the potential compensation unit according to the number of sense amplifier circuits activated at one operation timing among the plurality of sense amplifier circuits. 9. The semiconductor memory device according to claim 8, comprising switching means. 12. The semiconductor device for generating a threshold potential includes a first semiconductor device and a second semiconductor device, and the low-level potential generating means sets the low-level potential to a potential higher than a ground potential. Compensating the low level potential by supplying a current as described above; and a threshold value for receiving a control signal from the ground potential control unit and selecting the first semiconductor element or the second semiconductor element. 4. The semiconductor memory device according to claim 2, further comprising a potential generation semiconductor element selection unit. 13. The size of the second semiconductor element is smaller than the size of the first semiconductor element, and the threshold potential generation semiconductor element selecting means senses a part of the plurality of sense amplifier circuits. An output from the first semiconductor element is selected during the predetermined period from the time when the amplifier circuit is activated, and an output from the second semiconductor element is selected after the predetermined period has elapsed. 13. The semiconductor memory device according to claim 12, wherein: 14. A plurality of memory cell arrays each comprising a plurality of said memory cell arrays, wherein said plurality of sense amplifier circuits are provided adjacent to respective sides of said plurality of memory cell arrays which are parallel to a direction in which said word lines extend. And a memory core block including the plurality of memory cell arrays and the plurality of sense amplifier rows, wherein the low-level potential generation unit extends the plurality of sense amplifier rows in the memory core block. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is provided so as to be adjacent to both side portions parallel to the direction. 15. The semiconductor element for generating the ground potential, the semiconductor element for generating the threshold potential, and the semiconductor element included in the sense amplifier row are each formed in a common well provided continuously with the semiconductor substrate. 15. The semiconductor memory device according to claim 14, wherein: