JP4534163B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and particularly to a technology that is effective when used for a power supply technology in a dynamic RAM (Random Access Memory).

In order to increase the information holding time of the memory cell in the dynamic RAM, it is necessary to reduce the impurity concentration of the substrate and to reduce the electric field at the pn junction formed between the source / drain diffusion layers of the address selection MOSFET and the substrate. . When the impurity concentration of the substrate is thus lowered, the threshold voltage of the MOSFET is lowered, and the leakage current between the source and the drain when the gate voltage is set to a non-selection level such as the ground potential is increased. For this reason, it has been proposed to set the non-selection level of the word line to which the gate is connected to a negative voltage. This negative voltage uses a charge pump circuit and controls the oscillation circuit to operate intermittently by a level sensor in order to stabilize it. As examples of the dynamic RAM in which the non-selection level of the word line is set to a negative voltage and the information holding time is improved as described above, Japanese Patent Application Laid-Open No. 2-5290, Japanese Patent Application Laid-Open No. JP-A-7-57461 and JP-A-7-307091.
Japanese Patent Laid-Open No. 2-5290 Japanese Patent Laid-Open No. 6-255566 Japanese Patent Laid-Open No. 7-57461 Japanese Patent Laid-Open No. 7-307091

  The substrate voltage has a relatively large potential fluctuation such as 10% to 30% when the level of the bit line or word line changes between the selection level and the non-selection level due to capacitive coupling with the bit line or word line. It will occur. Therefore, if the negative back bias voltage supplied to the substrate voltage by the charge pump circuit is used for the non-selection level of the word line, the current for pulling out the selection level of the word line to the non-selection level together with the capacitive coupling. As a result, the discharge is performed, and the non-selection level of the word line is temporarily insufficient, which is a major cause of deteriorating information retention characteristics. Therefore, it was considered to improve the internal power supply circuit that operates stably.

  An object of the present invention is to provide a semiconductor integrated circuit device provided with an internal power supply circuit that operates stably. Another object of the present invention is to provide a semiconductor integrated circuit device including a dynamic RAM that has improved information retention characteristics while increasing the storage capacity. It is still another object of the present invention to provide a semiconductor integrated circuit device that realizes reliability, high-speed operation, and low power consumption. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. The semiconductor integrated circuit device operates with an external power supply voltage supplied from an external terminal, and has a first internal voltage having the same polarity as the external power supply voltage and an absolute value larger than the external power supply voltage, and the external power supply voltage A first power supply circuit for generating a second internal voltage having the same polarity and an absolute value larger than the external power supply voltage and smaller than the first internal voltage; and operating with the external power supply voltage; A third internal voltage having a polarity different from that of the external power supply voltage and having an absolute value greater than that of the external power supply voltage, and a polarity different from that of the external power supply voltage and having a value greater than that of the external power supply voltage by absolute value. A second power supply circuit for generating a fourth internal voltage whose absolute value is smaller than the voltage, and an internal circuit to which the second and fourth internal voltages formed by the first and second power supply circuits are applied Is provided. The first internal voltage is applied to an N-type well region in which a P-type well region in which elements constituting the internal circuit are formed is formed. The third internal voltage is also used as a substrate back bias voltage applied to the P-type well region where the elements constituting the internal circuit are formed.

  A semiconductor integrated circuit device including an internal power supply circuit that operates stably can be obtained.

  FIGS. 1 and 2 are schematic circuit diagrams showing a part of an embodiment of a dynamic RAM according to the present invention. FIG. 1 shows a memory array portion, and FIG. 2 shows a power supply circuit. An address and data input / output interface, a column selection circuit, a control circuit, and the like constituting the dynamic RAM are omitted.

  In FIG. 1, a dynamic memory cell includes word lines W1 to W3... Wn provided in one memory array MAC, which is exemplarily shown as a representative, and two pairs of complementary bit lines bit and / bit. On the other hand, eight provided between bit or / bit are exemplarily shown as representatives. The dynamic memory cell includes an address selection MOSFET Qm and a storage capacitor Cs. The gate of the address selection MOSFET Qm is connected to the corresponding word line W1 and the like, the drain of the MOSFET Qm is connected to the corresponding bit line bit and the like, and the storage capacitor Cs is connected to the source. The other electrode of the storage capacitor Cs is made common and a plate voltage is applied.

  In the dynamic RAM of this embodiment, the selection level of the word line W1 or the like is a high voltage VCH that is higher than the high level of the bit line bit or the like by the threshold voltage of the address selection MOSFET Qm. The The non-selection level of the word line is a negative voltage VNN which is lowered with respect to the circuit ground potential VSS.

  When a sense amplifier, which will be described later, is operated with the internal step-down voltage VDL, the high level amplified by the sense amplifier SA described below and applied to the bit line is set to a level corresponding to the internal voltage VDL. Therefore, the high voltage VCH corresponding to the selection level of the word line is set to a high voltage such as VDL + Vth. An input / output node of the sense amplifier SA is connected to the pair of complementary bit lines bit and / bit. The complementary bit lines bit and / bit are arranged so as to extend in parallel as shown in the figure, and are appropriately crossed as necessary in order to achieve capacity balance and the like. The complementary bit lines bit and / bit are connected to the input / output node of the unit circuit of the sense amplifier SA by the shared switch MOSFET when the sense amplifier adopts the shared sense system.

  The unit circuit of the sense amplifier SA includes N-channel type amplification MOSFETs Q4 and Q5 and P-channel type amplification MOSFETs Q6 and Q7 whose gates and drains are cross-connected to form a latch. The sources of the N-channel MOSFETs Q4 and Q5 are connected to a common source line, and the ground potential VSS of the circuit is supplied to the common source line via the N-channel power switch MOSFET Q8 at the operation timing of the sense amplifier. The sources of the P-channel MOSFETs Q6 and Q7 are connected to a common source line, and the internal step-down voltage VDL is supplied to the common source line via the P-channel power switch MOSFET Q9 at the operation timing of the sense amplifier.

  Although not particularly limited, the operating voltage on the high level side of the sense amplifier is like VCH between the start of the amplification operation and before the amplified signal of the bit line reaches the voltage VDL in order to achieve high-speed operation of the sense amplifier. It may be an overdrive that temporarily supplies a high voltage. That is, a P-channel MOSFET may be provided in parallel with the MOSFET Q9, and the P-channel MOSFET may be temporarily turned on at the start of the amplification operation of the sense amplifier to supply the high voltage VCH.

  At the input / output node of the unit circuit of the sense amplifier, a precharge circuit comprising an equalize MOSFET Q1 for short-circuiting complementary bit lines and switch MOSFETs Q2 and Q3 for supplying a half precharge voltage VDL / 2 to the complementary bit lines bit and / bit. Is provided. The gates of these MOSFETs Q1 to Q3 are commonly supplied with an equalize (or precharge) signal EQ. The driver circuit for generating the equalize signal EQ is such that the selection level is VCH and the non-selection level is a negative voltage such as VNN, like the word driver WD1 for driving the word lines W1 to W3... Wn. .

  On the other hand, the driver SAND for driving the power switch MOSFET Q8 that supplies the circuit ground potential to the sense amplifier SA operates with the internal voltage VDL and the negative voltage VNN, and has a high level such as an internal step-down voltage. Then, a drive signal SAN having a low level such as the negative voltage VNN is formed. The driver SAPD for driving the power switch MOSFET Q9 for supplying the internal step-down voltage VDL to the sense amplifier SA forms a drive signal SAP having a high level such as the high voltage VCH and a low level such as the circuit ground potential VSS.

  Although not particularly limited, a substrate voltage VBB having a potential lower than the negative voltage VNN is applied to the P-type well region in which the memory array MAC is formed, and a deep N region in which the P-type well region is formed. A high voltage VPP that is higher than the high voltage VCH is applied to an N-type well region that is coupled to the type well region and in which a P-channel MOSFET that forms the sense amplifier is formed. The voltage VBB and the voltage VPP are each formed by a charge pump circuit as will be described later.

  An X decoder XDEC and a word driver WD that form a selection signal for the word line W1, etc., are included in the array control circuit AC, a driver that forms the precharge signal EQ, and drivers SAND and SANP that form a drive signal for the sense amplifier Are supplied with VCH, VDL, VSS, and VNN as the operating voltages, and a high voltage VCPP is applied as a bias voltage to the N-type well region in which the P-channel MOSFETs constituting these drivers are formed. A negative voltage VBB is applied to the P-type well region or the P-type substrate where the channel MOSFET is formed.

  In FIG. 2, the high voltage VPP is formed by a high voltage generation circuit VPPG. The high voltage generation circuit VPPG includes an oscillation circuit 1, a charge pump circuit 2, and a level sensor 3, and the charge pump circuit 2 includes an oscillation pulse formed by the oscillation circuit 1. In response, a high voltage is generated by a charge pump operation. A level sensing operation is performed by the level sensor 3 so that the high voltage VPP is stabilized at a desired high voltage, and the operation of the oscillation circuit 1 is intermittently controlled. That is, the oscillation operation is stopped when the high voltage VPP reaches a desired high voltage, and the oscillation circuit 1 is operated when the high voltage VPP decreases.

  The high voltage VPP is set higher than the high voltage VCH corresponding to the selection level of the word line W1 and the like. For example, as shown in the operation waveform diagram of FIG. 3, when the word line selection voltage VCH is set to 2.25V, the high voltage VPP is set to a high voltage such as 2.6V. An excessively high voltage is formed with respect to the necessary voltage VCH, and the reference voltage generating circuit RGFP is operated based on the high voltage VPP. The reference voltage generation circuit RGFP causes the constant current Ip to flow through a resistor Rp based on the internal voltage VDL (or external power supply voltage Vext) through a current mirror circuit composed of P-channel type MOSFETs Q10 and Q11, thereby selecting the address. A voltage corresponding to the threshold voltage Vth of the MOSFET Qm is generated. As a result, the reference voltage VRH is set to a voltage corresponding to the above VDL (or Vext) + Vth.

  The constant voltage generating circuit RGP is a differential amplifier that receives a P-channel MOSFET Q12 as a variable resistance element provided between the high voltage VPP and the internal high voltage VCH, and the reference voltage VRH and the internal high voltage VCH. The output signal of the differential amplifier circuit 4 is supplied to the gate of the MOSFET Q12. When the internal high voltage VCH is lowered with respect to the reference voltage VRH, a signal that changes to a low level is formed, the resistance value of the MOSFET Q12 is decreased to match both, and conversely, the above-mentioned reference voltage VRH is compared with the reference voltage VRH. When the internal high voltage VCH is to be increased, a signal that changes to a high level is formed, and the resistance value of the MOSFET Q12 is increased so as to match the two.

  Negative voltage VBB is formed by negative voltage generation circuit VBBG. The negative voltage generation circuit VBBG includes the oscillation circuit 6, the negative charge pump circuit (Negative Charge pump circuit) 7 and a level sensor (Level Sensor) 8 as described above. In response to the oscillation pulse formed in 6, a negative voltage is generated by the charge pump operation. A level sensing operation is performed by the level sensor 8 so that the negative voltage VBB is stabilized to a desired negative voltage, and the operation of the oscillation circuit 6 is intermittently controlled. That is, the oscillation operation is stopped when the negative voltage VBB reaches a desired negative voltage, and the oscillation circuit 6 is operated again when the negative voltage decreases in absolute value.

  The negative voltage VBB is set to a voltage that is larger in absolute value than the negative voltage VNN corresponding to the non-selection level of the word line W1 or the like. For example, as shown in the operation waveform diagram of FIG. 3, if the non-selection voltage VNN of the word line is set to -0.75V, the negative voltage VBB is set to a voltage having a large absolute value such as -1.1V. Is done. An excessively large voltage is formed in the negative direction with respect to the necessary voltage VNN, and the reference voltage generating circuit RGFN is operated in the same manner as described above based on the negative voltage VBB. The reference voltage generating circuit RGFN passes a constant current In through a current mirror circuit composed of N-channel MOSFETs Q13 and Q14 to a resistor Rn with the circuit ground potential VSS as a reference, and the gate and source of the address selecting MOSFET Qm. A reverse bias voltage VRN applied between them is generated. In this embodiment, the voltage VRN is set to a negative voltage such as −0.75 V as described above.

  The constant voltage generating circuit RGN includes an N-channel MOSFET Q15 as a variable resistance element provided between the negative voltage VBB and the internal negative voltage VNN, and a differential receiving the reference voltage VRN and the internal negative voltage VNN. The output signal of the differential amplifier circuit 9 is supplied to the gate of the MOSFET Q15. If the internal high voltage VNN is to be reduced in absolute value with respect to the reference voltage VRN, a signal that changes to a high level is formed, the resistance value of the MOSFET Q15 is reduced to match both, and conversely, the reference voltage VRN. On the other hand, if the internal negative voltage VNN is to increase in absolute value, a signal that changes to a low level is formed, and the resistance value of the MOSFET Q15 is increased so as to match the two.

  A constant voltage generation circuit (Voltage regurator) 5 receives the external voltage Vext supplied from an external terminal and generates the internal step-down voltage VDL by a circuit similar to the constant voltage generation circuit RGP. This constant voltage generation circuit 5 is not necessarily required. Peripheral circuits such as the sense amplifier and address selection circuit may be operated by an external voltage Vext supplied from an external terminal. In this case, the level of the internal high voltage VCH is formed on the basis of the external voltage Vext as described above. Even when the constant voltage generating circuit 5 is provided, the constant voltage VDL may be used as an operating voltage of the sense amplifier, and an internal circuit such as an address buffer or an address decoder may be operated by the external voltage Vext.

  The voltages VPP and VBB formed by the charge pump circuit 2 or 7 as described above are held in the charge accumulated in the parasitic capacitance or the like. For example, when switching the word line from the non-selection level to the selection level, Conversely, when switching from the selection level to the non-selection level, a large number of memory cells are connected, so that they largely vary as described above depending on the current for charging up or discharging a word line having a relatively large parasitic capacitance. When the selection level or non-selection level of the word line is set in anticipation of such voltage fluctuation, a gate insulating film of an address selection MOSFET connected to the word line and a word driver for driving the word line are configured. It is necessary to increase the breakdown voltage according to the fact that a large voltage is applied to the gate insulating film of the output MOSFET in consideration of the level fluctuation.

  On the other hand, in the present invention, when the selection level and the non-selection level of the word line are formed via the constant voltage circuits RGP and RGN as described above, the word line is selected from the non-selection level as described above. When switching to a level, or conversely, when switching from a selected level to a non-selected level, a large number of memory cells are connected to cause the above-mentioned current to charge up or discharge a word line having a relatively large parasitic capacitance. Similarly, VPP and VBB fluctuate, but the resistance values of MOSFETs Q12 and Q15 as variable resistors of the constant voltage circuits RGP and RGN change to absorb the voltage fluctuation, so that the substantially constant voltage VCH And VNN can be secured.

  The voltage difference between the internal high voltage VCH and the high voltage VPP and the voltage difference between the internal negative voltage VNN and the negative voltage VBB are fluctuations in the output voltage of the charge pump circuits 2 and 7 corresponding to the drive current of the word line, respectively. It is formed so as to compensate. As a result, the voltage applied to the gate insulating film of the output MOSFET of the word driver WD and the address selection MOSFET of the memory cell becomes a relatively small voltage determined by the stabilized voltages VCH and VNN. There is no need to apply an extra high breakdown voltage.

  FIG. 3 is a waveform diagram for explaining the schematic operation of the dynamic RAM according to the present invention. In the figure, the operation of selecting a memory cell is mainly shown. The equalize signal EQ is set to a high level like the internal high voltage VCH when the memory cell is in the information holding state. As a result, the MOSFETs Q1 to Q3 are turned on, the complementary bit lines bit and / bit are short-circuited, and the half precharge voltage VDL / 2 is supplied. Since the complementary bit lines bit and / bit are set to the half precharge voltage VDL / 2, there is no problem with the operation itself even if the level of the equalize signal EQ is a low potential such as VDL. By using the voltage VCH, the on-resistance of the MOSFET Q1 can be reduced, and the high level / low level of the complementary bit lines bit and / bit can be short-circuited and set to the intermediate potential VDL / 2 in a short time.

  When the memory is accessed, the equalize signal EQ changes from a high level to a low level. At this time, the low level of the equalize signal EQ is not the ground potential of the circuit but the negative voltage VNN. The reason for this is that the threshold voltage is reduced in order to increase the speed of coiling. Therefore, the negative voltage VNN is supplied to the gates of the MOSFETs Q1 to Q3 to prevent the leakage current flowing between the drain and source. It is what you want to do.

  Similarly to the above, the sense amplifier activation signal SAN is also set to the negative voltage VNN when the sense amplifier is not operating, thereby preventing leakage current from flowing to the power switch MOSFET Q8 to which it is supplied. That is, the MOSFET Q8 has a low threshold voltage because the gate insulating film is formed with a small thickness in order to increase the speed of the sense amplifier. By using such a low threshold voltage MOSFET, a relatively large current can flow when the MOSFET is in an operating state, and the amplification operation of the sense amplifier is accelerated. This also applies to the P-channel MOSFET Q9. When the sense amplifier is not operating, the internal high voltage VCH is set to prevent leakage current from flowing through the power switch MOSFET Q9 to which it is supplied.

  After the equalize signal EQ is set to a non-select level such as the negative voltage VNN, the word line Wi is set to a high level select state such as the internal high voltage VCH. Thereby, the address selection MOSFET Qm of the memory cell is turned on, and charge distribution is performed between the information storage capacitor Cs and the parasitic capacitance of the bit line bit or / bit set to the half precharge potential VDL / 2. For example, if there is no charge in the information storage capacitor Cs, the potential of the bit line connected to the memory cell is lowered as shown in FIG.

  The sense amplifier activation signal SAN rises from the negative voltage VNN to the internal step-down voltage VDL as described above, turns on the N-channel MOSFET Q8, and gives a low level operation voltage such as the circuit ground potential. The enable signal SAP falls from the internal high voltage VCH to a low level such as the circuit ground potential VSS, and turns on the P-channel MOSFET Q9 to give a high level operating voltage such as the internal step-down voltage VDL. As described above, the MOSFETs Q8 and Q9 are set to a low threshold voltage by forming a thin gate insulating film. Therefore, when the MOSFETs Q8 and Q9 are turned on, a relatively large current is supplied to perform the amplification operation of the sense amplifier. Make it faster. By the amplification operation of the sense amplifier, the potentials of the complementary bit lines bit and / bit are amplified to a high level such as the internal step-down voltage VDL and a low level such as the circuit ground potential by expanding the read potential difference from the memory cell. Is done.

  The memory cell connected to the bit line bit or / bit by the selection operation of the word line Wi corresponding to the high level and low level of the complementary bit lines bit and / bit by the amplification operation of the sense amplifier as described above. The low level corresponding to the original storage charge state is rewritten in the storage capacitor Cs.

  Upon completion of the memory access, the word line Wi falls from the internal high voltage VCH to the negative voltage VNN, and then the equalize signal EQ rises from the negative voltage VNN to the internal high voltage VCH, and the complementary bit lines bit and / bit Are short-circuited to a half precharge voltage VDL / 2. In order to prevent the half precharge voltage VDL / 2 formed in this way from fluctuating due to a leakage current, the MOSFETs Q2 and Q3 are provided, and the half precharge voltage VDL / 2 is complemented by the ON state. It is transmitted to bit lines bit and / bit.

  FIG. 4 is a schematic element cross-sectional view of one embodiment of the dynamic RAM according to the present invention. In the dynamic RAM of this embodiment, each element is formed by a triple well structure. That is, an n-type well region DWELL having a deep depth is formed on a p-type substrate, and an address selection MOSFET for a memory cell and an N-channel MOSFET for a sense amplifier are formed on the n-type well region DWELL. pWELL is formed. In this way, the substrate back bias voltage VBB is applied to the p-type well region pWELL in which the memory cells are formed, the threshold voltage of the address selection MOSFET is increased to increase the information holding time, and the α ray For example, fractional carriers generated in the p-type well region pWELL are absorbed on the substrate back bias voltage VBB side to increase the information holding time.

  An n-type well region is formed so as to surround the p-type well region pWELL and to be joined to the DWELL, thereby forming a P-channel type MOSFET constituting a sense amplifier or the like. Peripheral circuits such as an X decoder are formed in a p-type well region pWELL formed on the p-substrate. In this configuration, the sense amplifier, the memory cell, and the word driver can be collectively formed in the DWELL including the pWELL in which the N channel type MOSFET of the memory cell and the sense amplifier is formed without providing a special element isolation region. High integration can be realized.

  In this embodiment, the MOSFET has two types of gate insulating films. In the address selection MOSFET of the memory cell and the output MOSFET constituting the word driver, the gate insulating film is formed with a thickness as thick as tox2. In the MOSFET constituting the sense amplifier and the peripheral circuit, the gate insulating film is formed as thin as the film thickness tox1. Thus, the advantage of using two types of film thicknesses of the gate insulating film is that both device reliability and high-speed operation can be achieved. That is, when there is only one type of gate insulating film, the film thickness of the gate insulating film is defined under the highest voltage condition applied for ensuring device reliability (securing the breakdown voltage of the gate insulating film). This is because in such a circuit where a high voltage is not applied, the threshold voltage becomes high, the current driving capability is lowered, and the operation speed becomes slow. In particular, the peripheral circuit and the sense amplifier are greatly influenced by the driving capability of the MOSFET, so that the influence is great.

  In this embodiment, an address selection MOSFET to which a large signal amplitude such as the internal high voltage VCH and the negative voltage VNN as described above is applied to the gate, and an output MOSFET of a word driver that forms an output signal having such a signal amplitude, In order to prevent breakdown voltage breakdown of the gate insulating film, a thick thickness tox2 is set, and a sense amplifier or a peripheral circuit MOSFET to which only the internal step-down voltage VDL or the like is applied has a thin thickness tox1 for high-speed operation. As described above, the reliability of the device and the speeding up of the operation are compatible.

  In this embodiment, a bias voltage such as a circuit ground potential VSS is applied to the p-substrate through a pWELL formed thereon. A high voltage VPP formed by a charge pump circuit is applied to the DWELL. The substrate back bias voltage VBB formed by the charge pump circuit is applied to the pWELL formed in the DWELL. In this configuration, the DWELL junction capacitance and the pWELL junction capacitance can be used as the voltage holding capacitors of the charge pump circuits 2 and 7, respectively.

  The internal high voltage VCH may be supplied to the DWELL, and the negative voltage VNN may be supplied to the pWELL formed in the DWELL. In this configuration, the junction capacitance of DWELL and the junction capacitance of pWELL can be used for capacitors CDH and CDN for voltage stabilization provided at the outputs of constant voltage circuits RGP and RGN shown in FIG. Therefore, as shown in the figure, in the configuration in which the high voltage VPP is supplied to the DWELL and the negative voltage VBB is supplied to the pWELL formed in the DWELL, the output voltage of the constant voltage circuits RGP and RGN is stable. Capacitors CDH and CDN must be formed of MOS capacitors or the like.

  FIG. 5 shows a schematic element cross-sectional view of another embodiment of the dynamic RAM according to the present invention. Also in this embodiment, each element is formed by a triple well structure as described above. That is, a deep n-type well region DWELL is formed on a p-type substrate, and a p-type well region pWELL for forming an address selection MOSFET of a memory cell is formed on the n-type well region DWELL. A substrate back bias voltage VBB is applied to the p-type well region pWELL in which the memory cell is formed, and the threshold voltage of the address selection MOSFET is increased to increase the information retention time, and the p-type well region pWELL is affected by α rays or the like. The fractional carriers generated in the type well region pWELL are absorbed on the substrate back bias voltage VBB side, thereby extending the information holding time.

  In this embodiment, the N-channel type MOSFET constituting the sense amplifier is formed in a p-type well region separated from the p-type WELL in which the memory cell is formed by the DWELL. In this configuration, not the substrate back bias voltage VBB but the circuit ground potential VSS is supplied to the p-type well region pWELL where the N-channel MOSFET of the sense amplifier is formed, as in the memory cell. As a result, the influence of the substrate effect is not affected by the back bias, and the threshold voltage of the N-channel type MOSFET constituting the sense amplifier can be reduced. Can be speeded up.

  FIG. 6 shows a circuit diagram of an embodiment of the word driver WD. In the drawing, of the word drivers WD, one word driver WDi corresponding to the word line Wi is exemplarily shown as a representative. The logic circuits G1, G2, etc. constituting the X decoder XDEC are operated by the internal step-down voltage VDL and the ground potential VSS of the circuit as described above, and high level / low level non-selection / selection outputs are correspondingly performed. Signal N1 is formed.

  On the other hand, since the selection level of the word line Wi corresponds to the internal voltage VCH and the non-selection level corresponds to the internal negative voltage VNN, the output signal N1 of the X decoder XDEC corresponding to the VDL and VSS is leveled. Need to convert. In this embodiment, in order to increase the reliability of the device, the voltage applied to the gate of the output MOSFET is devised so as to be as small as possible. That is, the output signal N1 is converted into two different levels by the two level conversion circuits LSP and LSN. The level conversion circuit LSP is for forming the signal N5 supplied to the gate of the output MOSFET MP1 that forms the selection level like the high voltage VCH from the output signal N1 of the X decoder XDEC. The level conversion circuit LSN Is for forming the signal N3 supplied to the gate of the output MOSFET MN1 that forms the non-selection level such as the negative voltage VNN from the output signal N1 of the X decoder XDEC.

  The level change circuit LSP is operated with the ground potential VSS and the high voltage VCH, and includes a pair of CMOS inverter circuits composed of P-channel MOSFETs Q18 and Q19, N-channel MOSFETs Q16 and Q17, and the P-channel MOSFET Q18. P-channel MOSFETs Q20 and Q21, which are connected in series to Q19 and latched so that the output signals of the other CMOS inverter circuit are supplied to each other, are provided to supply the high voltage VCH. The output signal N1 of the X decoder XDEC is supplied to the gates of MOSFETs Q17 and Q19 constituting one CMOS inverter circuit, inverted by the inverter circuit IV1, and supplied to the gates of MOSFETs Q16 and Q18 constituting the other CMOS inverter circuit. The

  The output signal N4 of the one inverter circuit is supplied to the input of the CMOS inverter circuit IV2 that operates as a driver, and the output signal N5 of the inverter circuit IV2 is supplied to the gate of the P-channel output MOSFET MP1. To drive. Although the inverter circuit IV1 is shown as a part of the level conversion circuit LSP, it actually has only a role of forming an inverted signal of the output signal of the X decoder XDEC. Therefore, the level conversion circuit LSP operates at the high voltage VCH and the ground potential VSS of the circuit as described above, but the inverter circuit IV1 has the internal step-down voltage VDL and the ground potential VSS as in the X decoder XDEC. It can be operated with.

  The level change circuit LSN has the same circuit configuration as the level conversion circuit LSP. However, the P-channel MOSFET and the N-channel MOSFET are reversed, a latch-type MOSFET is provided on the N-channel MOSFET side, and the high-level operation voltage is replaced with the internal high voltage VCH instead of the internal high voltage VCH. The difference is that the operating voltage on the low level side is set to the internal negative voltage VNN instead of the ground potential VSS of the circuit. That is, the level conversion circuit LSN operates with the internal step-down voltage VDL and the internal negative voltage VNN, and a pair of CMOS inverter circuits composed of the same P-channel MOSFET and N-channel MOSFET as described above, and the P-channel. Each of the n-type MOSFETs is connected in series with each other, and an n-channel type MOSFET whose gate is latched so that the output signals of the other CMOS inverter circuit are supplied to each other is provided to supply the internal negative voltage VNN.

  As described above, the output signal N1 of the X decoder XDEC is supplied to the gate of the MOSFET constituting one CMOS inverter circuit, inverted by the inverter circuit, and supplied to the gate of the MOSFET constituting the other CMOS inverter circuit. The output signal N2 of the one inverter circuit is supplied to the input of a CMOS inverter circuit that operates as a driver, and the output signal N3 of the inverter circuit is supplied to the gate of the N-channel output MOSFET MN1 to drive the output MOSFET MN1. Is.

  In this embodiment, in order to reduce the voltage applied between the gates and drains of the output MOSFETs MP1 and MN1, in other words, to alleviate the stress applied to the gate insulating films of the MOSFETs MP1 and MN1, the word line Wi P-channel type MOSFET MP2 and N-channel type MOSFET MN2 are connected in series with each other to the output terminal to which is connected. A ground potential VSS is applied to the gate of the P-channel MOSFET MP2 to be constantly turned on, and the internal step-down voltage VDL is applied to the gate of the N-channel MOSFET MN2 to be constantly turned on. The

  The level conversion circuit LSP forms the drive signal N5 having signal amplitudes such as VCH and VSS as described above, and controls the on / off state of the output MOSFET MP1. The P-channel MOSFET MP2 keeps the drain voltage of the output MOSFET MP1 at the ground potential VSS + VT (where VT is the threshold voltage of the MOSFET MP2) even when the word line Wi is the negative voltage VNN.

  As a result, as shown in the operation waveform diagram of FIG. 7, even when the output terminal is the negative voltage VNN corresponding to the non-selection level of the word line Wi due to the ON state of the N-channel output MOSFET MN1, the P channel in the OFF state. Only a voltage of VCH− (VSS + VT) is applied between the gate and drain of the type output MOSFET MP1.

  The level conversion circuit LSN controls the on / off state of the output MOSFET MN1 by generating the drive signal N3 having signal amplitudes such as VDL and VNN as described above. The N-channel MOSFET MN1 keeps the drain voltage of the output MOSFET MN1 at the internal step-down voltage VDL-VT (where VT is the threshold voltage of the MOSFET MN2) even when the word line Wi is at the high voltage VCH. As a result, as shown in the operation waveform diagram of FIG. 7, even when the output terminal is the internal high voltage VCH corresponding to the selection level of the word line Wi due to the ON state of the P-channel MOSFET MP1, the N-channel in the OFF state. Only a voltage such as (VDL-VT) -VNN is applied between the gate and drain of the type output MOSFET MN1.

  That is, as shown in the operation waveform diagram of FIG. 7, the signal amplitude limiting action such as the drive voltages N5 and N3 by the two types of level conversion circuits LSP and LSN as described above, and the MOSFET MP2 provided in series, Although the applied voltage dividing action by MN2 acts synergistically, the selection level / non-selection level of the word line Wi is a large voltage corresponding to the internal high voltage VCH and the internal negative voltage VNN as described above. The voltages applied to the output MOSFETs MP1 and MN1 can be small and limited. As for the memory cell, since the storage capacitor Cs holds the circuit ground potential VSS or the internal step-down voltage VDL, when the word line Wi is set to a negative voltage VNN that is not selected, VNN− A maximum voltage such as VSS-VCH is applied immediately after the maximum voltage such as VDL is applied and the word line Wi is set to the selection voltage VCH.

  The outline of the level conversion operation of the level conversion circuit LSP is as follows. When the output signal N1 of the gate circuit G1 constituting the X decoder XDEC is at a low level corresponding to the ground potential VSS, the P channel MOSFET Q19 of one of the CMOS inverter circuits (Q17 and Q19) is turned on. In the other CMOS inverter circuit (Q16 and Q18), the N-channel MOSFET Q16 is turned on by the high level of the output signal of the inverter circuit IV1, and the output signal is set to the low level. As a result, the P-channel MOSFET Q21 is turned on, and the output signal N4 is set to a high level like the high voltage VCH through the MOSFET Q19 in the on state. As a result, while forming a high level corresponding to the high voltage VCH, the P-channel MOSFET Q20 is turned off so that no direct current flows through the other CMOS inverter circuit.

  When the output signal N1 of the gate circuit G1 constituting the X decoder XDEC is at a high level such as the internal step-down voltage VDL, the N-channel MOSFET Q17 of one of the CMOS inverter circuits (Q17 and Q19) is turned on. In the other CMOS inverter circuit (Q16 and Q18), the output signal of the inverter circuit IV1 becomes low level, and the P-channel type MOSFET Q18 is turned on. Since the output signal N4 is set to the low level by turning on the MOSFET Q17 and the P-channel type MOSFET Q20 is turned on, the output signal of the other CMOS inverter circuit is set to the high level corresponding to the high voltage VCH. As a result, the P-channel MOSFET Q21 is turned off so that no direct current flows through one of the CMOS inverter circuits forming the low-level output signal N4.

  Since the level conversion operation of the level conversion circuit LSN is almost the same as described above, only the operation when the output signal N1 of the gate circuit G1 constituting the X decoder XDEC is at a low level corresponding to the ground potential VSS will be described below. It is as follows. The P-channel MOSFET of one CMOS inverter circuit to which the output signal N1 is supplied is turned on. The other CMOS inverter circuit is supplied with an inverted high level signal, so that the N-channel MOSFET is turned on. The ON state of the P channel MOSFET of the one CMOS inverter circuit causes the output signal N2 to be at a high level like the internal step-down voltage VDL, and the N channel MOSFET of the other CMOS inverter circuit is turned on. As a result, the output signal of the other CMOS inverter circuit outputs the negative voltage VNN with the two N-channel MOSFETs turned on. As a result, a high-level output signal N2 corresponding to the internal step-down voltage VDL is formed, and the corresponding N-channel MOSFET on the negative voltage VNN side is turned off, and a direct current flows through the one CMOS inverter circuit. It is something to prevent.

  FIG. 8 shows a circuit diagram of another embodiment of the word driver WD. In this embodiment, the X decoder is divided into two circuits. In the first decoder XDEC, a selection signal N1 for four word lines is formed. This selection signal is supplied to the corresponding word driver WDi through switch MOSFETs M10 to M13 which are switch-controlled by selection signals X00, X01, X10 and X11 formed by a second decoder (not shown).

  The word driver WDi is configured to have both a level conversion function and a word drive function so that one circuit is exemplarily shown as a representative. The P-channel type output MOSFETs M3 and M4 and the N-channel type MOSFETs M6 and M5 constitute the word driver as described above. The N-channel output MOSFET M6 is latched with the N-channel MOSFET M7 so as to have the level conversion function as described above. As described above, the MOSFET M7 is connected in series with the N-channel MOSFET M8 for reducing the breakdown voltage, and the internal step-down voltage VDL is supplied to the gate together with the MOSFET M5.

  The P-channel output MOSFET M3 is provided with a P-channel MOSFET M2 that is latched for level conversion. The gate of the output MOSFET M3 is precharged to a high voltage VCH through a P channel type MOSFET M1 controlled by a precharge signal WPH. A selection signal N5 is supplied to the input point through the switch MOSFET M10.

  FIG. 9 is a timing chart for explaining the operation of the word driver. When the precharge signal WPH is at a low level such as the circuit ground potential GND, the P-channel MOSFET M1 is turned on and the input terminal is precharged to the high voltage VCH. By this precharge operation, the MOSFET M3 is turned off, and at the same time, the gate potential N3 of the N-channel output MOSFET M6 is set to a high level like VDL-VT through the MOSFET M9 and MOSFET M8 which are turned on. For this reason, the MOSFET M6 is turned on, and the word line Wi is set to a non-selection level such as the negative voltage VNN.

  When the MOSFET M6 is turned on, the negative voltage VNN is supplied to the gate of the MOSFET M7 which is latched with the MOSFET M6 to be turned off. Therefore, it is possible to prevent a through current from flowing through a series path including the precharge MOSFET M1 that is turned on, the MOSFETs M9 and M8 that are constantly turned on to relax the voltage, and the MOSFET M7.

  By the operation of the X decoder, the output signal N1 of the first decoder XDEC1 is set to the low level. When the MOSFET M10 is turned on by the high level of the selection signal X00 among the four word lines, the selection signal N5 of the input terminal is pulled out to the low level. As a result, the output MOSFET M3 changes from the off state to the on state, and the word line Wi is raised from the negative voltage VNN to the high voltage VCH. Due to the rise of this voltage, the MOSFET M7 is turned on, and the gate voltage N3 of the MOSFET M6 is lowered from VDL-VT to the negative voltage VNN. For this reason, the MOSFET M6 is turned off, and the potential of the word line Wi rises to the high voltage VCH at high speed. In the other non-selected word lines, in order to maintain the precharge voltage in the corresponding word driver, the P-channel output MOSFET is turned off, the N-channel output MOSFET is turned on, and the negative voltage is applied. Maintain a non-selection level such as VNN.

  When the selection operation of the word line Wi is completed, the decode signal X00 is set to the low level, and the MOSFET M10 is turned off. Further, the output signal N1 of the first decoder XDEC1 returns to the high level. Thereafter, the precharge signal WPH changes to a low level to turn on the MOSFET M1. For this reason, the voltage N5 at the input terminal is precharged to the high voltage VCH. By this precharge operation, the P-channel output MOSFET M3 is turned off, and the gate voltage N3 of the N-channel MOSFET M6 is set to a high level limited by the MOSFET M8 as VDL-VT. Due to the ON state of the MOSFET M6, the selection level (VCH) of the word line Wi is lowered to the negative voltage VNN corresponding to the non-selection level. Also in this configuration, the voltage applied to the output MOSFETs M3 and M6 is limited as described above, and the high reliability of the device can be ensured.

  In this embodiment, the first X decoder circuit XDEC is shared by word drivers corresponding to four word lines. Thereby, the number of MOSFETs required per one word line can be reduced. In other words, the pitch of the word lines arranged at a high density can be matched with the pitch of the X decoder that forms the selection signal, thereby enabling high integration.

  FIG. 10 is a block diagram showing an embodiment in which the present invention is applied to a hierarchical (divided word line type) word driver. The hierarchical word line is a word line divided into a main word line and a sub word line, and a memory cell is connected to the sub word line. The hierarchical word system as described above is for relaxing the layout pitch of the metal wiring layer in the so-called word shunt system in which a high resistance word line is lined with a low resistance metal wiring layer. By using such divided word lines, high integration can be realized while increasing the storage capacity.

  FIG. 2 shows a schematic configuration for explaining the relationship between the main word line and the sub word line of the memory mat. In the figure, two main word lines MW0 and MWi are shown as representatives. The main word lines MW0, MWi, etc. are selected / unselected by the drivers MDRV0, MDRVi, etc. provided in the main word driver MWD. The one main word line MW0 is provided with a plurality of sets of sub word lines SWL in the extending direction thereof. In the drawing, three sets of sub word lines SWL are illustratively shown. In the sub word lines SWL, a total of eight sub word lines of even numbers 0 to 6 and odd numbers 1 to 7 are alternately arranged in one memory mat MAT0 and MAT1. Thus, by assigning eight sub word lines in the arrangement direction to one main word line, the pitch of the main word lines can be reduced to 1/8.

  Arranged between memory mats except for even numbers 0 to 6 adjacent to the main word driver MWD and odd numbers 1 to 7 disposed on the far end side (opposite side of the word driver) of the main word line MW0 (not shown). The sub word driver SWD1 and the like form a selection signal for a pair of sub word lines such as the left and right memory mats MAT0 and MAT1 around the driver. Thus, by dividing the length of the sub word line with respect to the extending direction of the main word line, the number of memory cells connected to one sub word line can be reduced, and the memory cell selection operation is accelerated. be able to.

  In the configuration in which the sub word lines are divided into even numbers 0 to 6 and even numbers 1 to 7 as described above, and the sub word drivers SWD0 and SWD1 are arranged on both sides of the memory mat, respectively, the sub word lines are arranged at high density according to the arrangement of the memory cells. The substantial pitch of the sub word lines SWL can be relaxed to twice that of the sub word drivers SWD0 and SWD1, and the driver SDRV provided in the sub word drivers SWD0 and SWD1 and the corresponding sub word lines SWL can be efficiently laid out. . The driver SDRV selects / deselects the sub word line SWL by the logical product (AND) of the main word line MWi and the sub word selection line FX1.

  A selection signal formed by the gate circuits AN3, AN4, etc. constituting the X decoder XDEC is supplied to the main word driver MWD. The main word driver MWD is composed of drivers MDRV0, MDRVi and the like that receive the selection signal, and a main word as a selection signal corresponding to four sub word lines 0-6 (1-7) in each of the memory mats MAT0, MAT1. The lines MW0, MWi, etc. are driven to be selected / unselected. A sub word selection line FXi for selecting one sub word line from among the four sub word lines 0 to 6 or 1 to 7 is provided. The sub word selection lines FXi are composed of eight lines such as FX0 to FX7, and a selection signal is formed by the gate circuits AN1, AN2, etc. included in the X decoder XDEC.

  The even numbered subword selection lines FX0 to FX6 are supplied to the even numbered subword drivers SDRV0 to SDRV0 through the drivers FDRV0 and the like included in the main word driver MWD, and the odd numbered subword selection lines FX1 to FX7 are supplied to the even numbered subword drivers SDRV1 and the like through the driver FDRV1 and the like. The odd-numbered column sub-word drivers FDRV1 to FDRV7 are supplied. Although not particularly limited, the sub word selection lines FX0 to FX7 are formed by the second metal wiring layer M2 which is the same as the main word line MW0 and the like in the periphery of the array. The sub word selection lines FX0 to FX7 are branched at a portion corresponding to the sub word driver, and at a portion intersecting with the main word lines MW0 to MWi constituted by the second metal wiring layer M2, the third layer is selected. The metal wiring layer M3 is extended in a direction perpendicular to the main word line and led to the input of the sub word driver.

  FIG. 11 shows a circuit diagram of an embodiment of a sub word driver SDRV corresponding to the above hierarchical word driver system. In this embodiment, in order to ensure the high reliability as described above, the sub word selection line and the main word line are constituted by a pair of signal lines. That is, the signals FXiB and FXi of the pair of sub word selection lines are such that when the signal FXiB is at a high level such as the internal high voltage VCH, the signal FXin is at a low level such as the negative voltage VNN, and the signal FXiB is at the ground potential VSS of the circuit. At such a low level, the signal FXin is a substantially complementary signal that is set to a high level such as the internal step-down voltage VDL.

  The signals FXi and FXiB of the sub word selection lines are inverted by drivers DV1 and DV2, respectively, at branch portions where the sub word drivers are provided, and become signals FXiBn and FXin of the sub word selection lines corresponding to the corresponding sub word drivers. The branched signal FXin of the sub word selection line is used as an operating voltage of a sub word driver SDRV described below. That is, the selected one is set to the internal high voltage VCH as described above, and the non-selected one is set to the circuit ground potential VSS (0 V). The signal FXiBn of the branched sub word selection line is used to set the sub word line SWL to the negative voltage VNN when the signal FXin is at the non-selected ground potential 0V.

  When the main word line MWiBP is at a high level such as the internal high voltage VCH, the main word line MWiBN is at a high level such as the internal step-down voltage VDL, and the main word line MWiBP is grounded. The main word line MWiBN is supplied with a substantially in-phase selection / non-selection signal indicating a low level such as the internal negative voltage VNN when it is at a low level such as the potential VSS.

  Such two signals MWiBP and MWiBN drive a P-channel output MOSFET M14 and an N-channel output MOSFET M17 similar to those shown in FIG. 6 to set the sub word line SWL to a select / non-select level such as VCH and VNN. . However, the difference from the circuit of FIG. 6 is that the operating voltage is supplied by the sub-word selection line FXin as described above. Therefore, when the sub word selection line FXin is at a non-selection level such as 0V and the signals MWiBP and MWiBN of the main word line are at the selection level, MOSFETs M18 and M19 are used to set the sub word line SWL to the non-selection negative voltage VNN. The internal step-down voltage VDL of the sub word selection line FXiBn is supplied to the gate of the MOSFET M19. As a result, when the sub word selection line FXin is at a non-selection level such as 0V and the main word line signals MWiBP and MWiBN are at the selection level, the MOSFET M19 is turned on and the sub word line SWL is set to the negative voltage VNN. This is a non-selection level.

  The MOSFETs M15, M16, and M18 share and lower the voltage applied to the gate insulating film applied to the output MOSFETs M14, M17, and M19 as described above. It is possible to ensure the high reliability of the device as described above by synergistically acting as small as VSS to VCH.

  FIG. 12 is a circuit diagram showing one embodiment of a driver for driving the sub word selection line and the main word line. As shown in the waveform diagram of FIG. 13, the driver FDRV receives signals FXi and FXiB supplied to the subword selection line in response to the subword selection line FSXi having a small amplitude such as 0 to VDL formed by the X decoder XDEC. Form. That is, the small amplitude signal FSXi is level-converted into signal amplitudes such as VNN to VDL and 0 to VCH by the level conversion circuits LSN and LSP similar to those described with reference to FIG. The sub-word selection lines FXi and FXiB are output via the drivers DV3 and DV4.

  As shown in the waveform diagram of FIG. 13, the main word driver MDRV receives a small-amplitude main word line selection signal varying from 0 to VDL formed by the X decoder, and supplies it to the main word lines MWiBN and MWiBP. The selected / unselected signal is formed. That is, the small amplitude signal XDEC is level-converted into signal amplitudes such as VNN to VDL and 0 to VCH by the level conversion circuits LSN and LSP similar to those described with reference to FIG. The main word lines MWiBN and MWiBP are driven through the drivers DV5 and DV6.

  Also in such a hierarchical word system, the output MOSFETs constituting each driver as described above are provided with the above-described MOSFET for voltage sharing, and the signal amplitude thereof is set to the P-channel MOSFET side and the N-channel type. High reliability of the device can be ensured by dividing it for the MOSFET side and transmitting it as two relatively small signal amplitudes.

  FIG. 14 is a schematic block diagram showing another embodiment of the power supply circuit in the dynamic RAM according to the present invention. The dynamic RAM of this embodiment has a plurality (four in the figure) of memory arrays MCA. These memory arrays MCA are each composed of a plurality of memory mats as will be described later when the hierarchical word driver method is adopted. In this embodiment, a plurality of constant voltage circuits RGN and RGP are provided for the charge pump circuit VPPG for high voltage and the charge pump circuit VBBG for negative voltage. Although not particularly limited, a plurality of these constant voltage circuits RGN and RGP are provided in one-to-one correspondence with the above-described plurality of memory arrays MCA. In each memory array MCA, since the voltages VCH and VNN are the same, a common circuit is used for the reference voltage generation circuits RGFP and RGFN that correspond to the VCH and VNN and form the reference voltages VRH and VRN.

  In this configuration, the constant voltage circuits RGP and RGN can be arranged close to the word line selection circuits XDEC and WD of the memory array MCA as a load, the wiring between them is shortened, and the power source impedance is lowered. In addition, since the charge pump circuits VPPG and VBBG and the reference voltage generation circuits RGFP and RGFN can be used in common, the circuit scale can be reduced. The voltage formed by the charge pump circuits VPPG and VBBG is formed large in advance in absolute value so that there is no problem even if voltage fluctuation occurs when the word line changes to the selected state or the non-selected state, Since the reference voltage generation circuit is used only as a reference voltage for the differential circuit and almost no current flows, it is provided in common for a plurality of circuits as described above, and there is almost no problem even if the wiring length between them becomes long. Absent.

  FIG. 15 shows a circuit diagram of another embodiment of a subword selection line driver and subword driver corresponding to the hierarchical word driver system. In this embodiment, the sub-word line can be selected by one main word line MWiB and one sub-word selection line FXiB. Such a single sub word selection line and main word line make it possible to reduce the number of wirings and the number of circuit elements.

  As described above, when the sub-word selection line and the main word line are configured by one, the selection / non-selection signal level is a large signal such as VNN to VCH as shown in the waveform diagram of FIG. Amplitude. A driver for forming an inversion signal is provided at the branch portion of the sub word selection line as described above. This driver operates with the voltages of VCH and VNN, forms a subword selection line FXin inverted from the signal FXiBn as shown in the waveform diagram of FIG. 16, and is used as the operating voltage of the subword driver. .

  In the branch driver, the signal of the sub-word selection line FXiB is transmitted to the gate of the N-channel output MOSFET M25 that outputs the negative voltage VNN through the N-channel MOSFET M21 to which VDL is supplied to the gate. The voltage is transmitted to the gate of the P-channel output MOSFET M22 that outputs the high voltage VCH via the P-channel MOSFET M20 to which the ground potential VSS is supplied. Between the P-channel type output MOSFET M22 and the output terminal, a P-channel type MOSFET M24 with the VSS applied to the gate is inserted in series, and between the N-channel type output MOSFET M25 and the output terminal, An N-channel MOSFET M24 is provided in which VDL is applied to the gate.

  Although the sub-word selection line FXiB has a large signal amplitude such as VCH and VNN as described above, a relatively small voltage is applied to the output MOSFETs M22 and M25 constituting the driver as in FIG. Only the voltage is applied and the high reliability of the device can be ensured.

  The subword driver is the same as the above driver. However, when the main word line MWiB is at a selection level such as VNN and the sub word selection line FXin is at a non-selection level such as VNN, the sub-word line SWLi is set to a non-selection level such as the negative voltage VNN. Further, a MOSFET 27 having the gate connected to the sub-word selection line FXiBn is provided, and the high level (VCH) is transmitted to the gate through the voltage dividing MOSFET in which VDL is applied to the gate in the same manner as described above. Thus, the sub word line SWLi is set to the negative voltage VNN. Also at this time, the voltage dividing MOSFET M26 in which the VDL is applied to the gate is connected in series between the output terminal to which the sub word line SWLi is connected.

  Since the driver for driving the sub word selection line FXiB and the main word line MWiB generates output signals such as VNN to VCH, the word driver as shown in FIG. 6 is used.

  FIG. 17 shows a circuit diagram of an embodiment of the reference voltage generating circuit. In this embodiment circuit, reference voltages VRN and VRP corresponding to the VCH and VNN are generated. The reference voltage generation circuit includes a reference voltage circuit BGG that uses the silicon band gap of the bipolar transistor, a voltage / current conversion circuit IVCON that converts a voltage formed by the reference voltage circuit into a current signal, and a current mirror circuit that converts the current signal into a current mirror circuit. A circuit for generating the reference voltages VRN and VRP is used.

The bipolar transistors T1 and T2 are formed so that their emitter areas A _E are different as 1 and 8, and their collectors and bases are connected in common to form a diode, and the emitter is connected via a high resistance such as 1 MΩ. Thus, a constant voltage is generated by applying a difference voltage corresponding to the silicon band gap to a resistor such as 88 KΩ so that the same current flows. That is, the voltage supplied to the high resistance is controlled by the differential amplifier circuit composed of the differential MOSFETs Q21 and Q22 so that the emitter voltage of the transistor T1 and the emitter voltage of the transistor T2 through 88 KΩ are equal. As a result, a reference voltage VREF such as 1.26 V is generated at the high resistance.

  The transistors T1 and T2 use a source / drain diffusion region of a P-channel MOSFET as an emitter, an n-type well region nWELL in which it is formed, and a p− type substrate as a collector. The collector and the base are connected in common and set to the ground potential applied to the p-type substrate. The differential voltage generated in the 88 KΩ resistor is set to a voltage of 1.26 V corresponding to the resistance ratio with the high resistance through which the same current flows.

  The P-channel MOSFET Q23, which acts as a resistance element with the ground potential supplied to the gate, constitutes a start-up circuit. The BGG composed of the transistors T1 and T2 and the difference image amplifier circuit is provided with the start-up circuit in order to be stable even when VREF is 0 V, that is, when the transistors T1 and T2 are off and the differential MOSFETs Q21 and Q22 are off. Thus, a reference voltage such as 1.26V is formed. The reference voltage VREF is more stabilized because the capacitor C1 is provided.

  The voltage / current conversion circuit IVCON forms a voltage follower circuit by the differential circuit composed of the differential MOSFETs Q24 and Q25 and the output MOSFET Q26, and causes the reference voltage VREF to flow through the resistor RF to form a constant current. Since this constant current flows to the output MOSFET Q26, P channel type MOSFETs Q27 and Q30 having a common gate and source are provided to form a current mirror circuit, and the reference current converted from the drains of the MOSFETs Q27 and Q30 is used as a current mirror circuit. Take out. Although not particularly limited, the reference voltage VREF0 formed by the resistor RF is not particularly limited, but is used for a level sensor described later.

  The reference current output from the drain of the MOSFET Q27 is supplied to a current mirror circuit composed of N-channel MOSFETs Q28 and Q29 whose source is connected to a substrate voltage VBB such as −1.0 V formed by the charge pump circuit VBBG. Then, the output current is passed through a resistor RL1 provided between the ground potential and a reference voltage VRN such as -0.75V is generated. The resistor RL1 is provided with a capacitor C3 in parallel to stabilize the voltage.

  The reference current output from the drain of the MOSFET Q30 is supplied to a current mirror circuit composed of N-channel MOSFETs Q31 and Q32 whose sources are connected to the ground potential of the circuit, and the reference current via the current mirror circuit is the charge current. A high voltage VPP generated by the pump circuit VPPG is supplied to P-channel MOSFETs Q33 and Q34 whose sources are connected, and a resistor RL2 is provided between the output and the internal voltage VDD (VDL), and the above VDD is used as a reference. A reference voltage VRP such as about 2.25V is formed. The capacitor C4 is provided to stabilize the reference voltage VRP.

When the P-channel MOSFET and the N-channel MOSFET constituting the current mirror circuit have the same element size and form a current equal to the reference voltage formed by the resistor RF, the reference voltages VRP and VRN Is expressed by the following equations (1) and (2).
VRP = VREF × RL2 / RF + VDD (VDL) (1)
VRN = −VREF × RL1 / RF (2)

  As described above, in the circuit of the embodiment, the reference voltage VREF is formed using the silicon band gap, and the reference voltages VRP and VRN are formed by the resistance ratios RL2 / RF and RL1 / RF. Even if a circuit element formed in a semiconductor circuit having large variations is used, the resistance ratio is not affected by the circuit element, so that the reference voltages VRP and VRN can be formed with high accuracy.

  FIG. 18 shows a circuit diagram of an embodiment of the constant voltage generation circuit RGP. In this embodiment, the differential amplifier circuit is composed of two circuits. A circuit composed of the differential MOSFETs Q40 and Q41 and the MOSFET Q44 acting as a variable resistance element is steadily operated by constantly applying a constant voltage such as VDL to the gate of the MOSFET Q48 forming the operating current. That is, only a small current flows through the MOSFET Q48 in order to reduce current consumption in the constant voltage generation circuit itself when the memory circuit is in a standby state.

  In order to have a relatively large current supply capability in response to switching of the word line selection / non-selection operation by memory access, the N-channel MOSFET Q47 is turned on by the control signal ACTH to perform differential operation during the memory access. A constant voltage circuit comprising MOSFETs Q42 and Q43 and MOSFET Q45 acting as a variable resistance element is operated. In this circuit, when the signal ACTH is in a low level non-operating state, the P-channel type MOSFET Q46 is turned on to turn off the MOSFET Q45 as the variable resistance element.

  FIG. 19 shows a circuit diagram of an embodiment of the constant voltage generating circuit RGN. In this embodiment, the differential amplifier circuit is composed of two circuits as described above. The circuit comprising the differential MOSFETs Q50 and Q51 and the MOSFET Q52 acting as a variable resistance element is steadily operated by applying a ground potential such as VSS to the gate of the MOSFET Q43 that forms the operating current. That is, in order to reduce current consumption in the constant voltage generation circuit itself when the memory circuit is in a standby state, only a small current flows through the MOSFET Q53 as described above.

  In order to have a relatively large current supply capability in response to switching of the word line selection / non-selection operation by memory access, the P-channel MOSFET Q58 is turned on by the low level of the control signal ACTN, and the memory access is performed. Sometimes, a constant voltage circuit composed of differential MOSFETs Q54 and Q44 and MOSFET Q56 acting as a variable resistance element is operated. This circuit turns on the N-channel MOSFET Q57 and turns off the MOSFET Q56 as the variable resistance element when the signal ACTN is in a high level non-operating state.

  FIG. 20 shows a circuit diagram of an embodiment of the VBB charge pump circuit 7. In this embodiment, although not particularly limited, P-channel MOSFETs Q59 to Q66 are used. These P-channel MOSFETs are formed in the N-type well region. Therefore, it can be electrically separated from the P-type well region in which the memory cell is formed, and minority carriers are generated in the N-type well region in the charge pump operation. Therefore, the memory cell formed in the P-type well region Will not have any effect.

  A basic circuit of a pumping circuit that generates the negative voltage VBB is configured by the capacitor C13 formed using the MOS capacitor and the MOSFETs Q61 and Q63. The capacitor C14 and the MOSFETs Q62 and Q64 are similar basic circuits, but the input pulses OSC and OSCB are in a reverse phase relationship that their active levels do not overlap with each other, and alternately correspond to the input pulses OSC and OSCB. It operates to perform an efficient charge pump operation.

  MOSFETs Q61 and Q63 may basically be in the form of a diode, but if this is done, level loss will occur by the threshold voltage. When the high level of the pulse signal OSC is a low voltage such as 3.3V, the pulse signal OSC substantially does not operate. Therefore, focusing on the fact that the MOSFET Q61 only needs to be turned on when the input pulse OSC is at a low level, the inverter Q61 is provided with an inverter circuit N10 that forms a pulse similar to the input pulse, a capacitor C11, and a switch MOSFET Q59 to be a negative voltage. Forming a control voltage. Thus, the negative potential of the capacitor C13 can be transmitted to the substrate voltage VBB side without level loss. The MOSFET Q59 is turned on when a negative voltage is formed by the other input pulse OSCB to charge up the capacitor C11. The capacitor C11 is a small-sized capacitor sufficient to form the control voltage for the MOSFET Q61.

  The MOSFET Q63 is turned off at an early timing by receiving the high level output signal of the driving inverter circuit N13 that receives the other input pulse OSCB at the back gate (channel portion), and efficiently pulls out the substrate potential. Similarly, the output signal of the drive inverter circuit N12 is supplied to the back gate of the MOSFET Q61, so that when charging the capacitor C13, the MOSFET Q61 is turned off at an early timing to minimize the leakage of the substrate potential VBB. . The control voltage supplied to the gate of the MOSFET Q62 corresponding to the other input pulse OSCB and the back gate voltage of the MOSFETs Q64 and Q62 are based on the pulse signal and the input pulse OSC formed by the inverter circuit N13 and the capacitor C14 that perform the same operation. The pulse signal formed in this way is used.

  A MOSFET Q65 (Q66) for pulling out the gate voltages of the MOSFETs Q59 and Q63 (Q60 and Q64) at an early timing is provided. This MOSFET Q65 (Q66) has a gate and drain connected in common to form a diode and is supplied with an output signal of a driving inverter circuit N12 (N13) receiving its input pulse OSC (OSCB) at its back gate. As a result, the switch is complementarily controlled with the MOSFET Q63 (Q64). As a result, the MOSFET Q63 (Q64) can be quickly switched from the on state to the off state when the output signal of the driving inverter circuit N12 (N13) changes to the low level in response to the input pulse OSC (OSCB), so that it is efficient. The substrate potential can be extracted to a negative potential.

  FIG. 21 shows a circuit diagram of an embodiment of an oscillation circuit 6 for forming an oscillation pulse supplied to the VBB charge pump circuit 7. In this embodiment, a P-channel MOSFET Q68 and an N-channel MOSFET Q69 acting as resistance elements are connected in series to a P-channel MOSFET Q67 and an N-channel MOSFET Q70 constituting the CMOS inverter circuit, respectively, and the input capacitance of the CMOS inverter circuit at the next stage is connected. In addition, a time constant circuit is configured to delay the signal. An odd number of these CMOS inverter circuits (5 in the figure) are connected in cascade to form a ring oscillator.

  In order to operate these ring oscillators intermittently, in other words, when the substrate voltage VBB reaches a desired negative voltage (about −1.0 V), the operation of the oscillation circuit is stopped to stabilize the substrate voltage VBB. A control circuit is provided to reduce power consumption and power consumption. The signal DETA is a signal formed by a level sensor to be described next, and is set to a low level when it is determined that the substrate voltage VBB has reached a desired potential. Due to the low level of the signal DETA, the output signal that has passed through the inverter circuits N15 and N16 becomes a low level, and the N-channel MOSFET that is provided in the final stage CMOS inverter circuit constituting the ring oscillator and functions as a resistance element is turned off. At the same time, the P-channel type MOSFET provided at the output terminal is turned on to forcibly fix the final stage output to the high level. Then, the outputs of the gate circuits G1 and G2 are set to high level, the output signal of the gate circuit G3 is set to low level, and the oscillation pulse OSC is fixed to low level and the oscillation pulse OSCB is fixed to high level.

  The signal VBOSCSW is a signal that is set to a high level when the memory is in a standby state. The high level of the signal VBOSCSW causes the gate circuit G1 to close the gate and open the gate circuit G2, and is formed by the ring oscillator. Instead of the relatively high frequency, a built-in self-refresh timer oscillation pulse SLOSC is used as oscillation pulses OSC and OSCB for supplying the charge pump circuit. Also in the operation of the charge pump circuit at such a low frequency, the oscillation pulse OSC is fixed to the low level and the oscillation pulse OSCB is fixed to the high level so that the gate G2 closes the gate by the low level of the signal DETA. .

  FIG. 22 shows a circuit diagram of an embodiment of the level sensor 8 for VBB. A constant current is formed by an N-channel MOSFET Q72 to which the constant voltage VREF0 is applied between the gate and source, and a reference current i1 is formed by a current mirror circuit based on the constant current. A substrate voltage VBB is supplied by connecting a plurality of N-channel MOSFETs in series in the current path. The plurality of series MOSFETs are provided with adjustment terminals and are used for adjustment of process variations of devices. That is, when the substrate voltage VBB is −1.0 as described above, the current i2 flowing through the series MOSFET is balanced with the current i1. That is, the balance adjustment of the current i2 flowing through the MOSFET Q76 and the current i1 is performed so that the source potential of the MOSFET Q76 coincides with the ground potential VSS. Two MOSFETs Q73 and Q74 are also connected in series to the N-channel current mirror circuit to enable adjustment of the reference current i1, and the mirror current ratio is adjusted by selective short-circuiting of the source and drain. Is.

  When the substrate voltage VBB is smaller in absolute value than the set voltage, the source potential of the MOSFET Q76 becomes higher than the ground potential and the current i2 <i1 is satisfied. As a result, no current flows through the P-channel MOSFET Q77 provided in parallel with the P-channel MOSFET Q76 that supplies the reference current i1, and this corresponds to the current difference from the N-channel MOSFET Q78 that supplies the current corresponding to the current i1. Thus, the voltage vs is set to the low level. This low level signal vs is amplified by a CMOS inverter circuit composed of MOSFETs Q68 to Q71, and further output as a sense output DETA through the inverter circuit and the gate circuit G4.

  Due to the high level of the sense output DETA, a current path is formed in parallel with the MOSFET Q78 so that the signal vs is pulled out to the lower level side. When the substrate potential VBB becomes larger than the desired voltage in absolute value, the current i2> i1 is reversed, and the difference between the currents flows to the P-channel MOSFET Q77 to raise the voltage vs to the high level side. To do. When the potential vs becomes higher than the logic threshold of the CMOS inverter circuit, the sense output DETA changes to a low level, which is fed back to turn off the N-channel MOSFET that pulls down the voltage vs to the low level side. The voltage vs is raised to a high level rapidly. With such a feedback circuit, the level determination by the CMOS inverter circuit has a hysteresis characteristic. By providing such hysteresis characteristics, the intermittent operation of the oscillation circuit can be stably controlled, and the substrate voltage VBB can be stably set within a range of about 10% with respect to the set value.

  The signal SETB is a signal that is temporarily set to high level immediately after the power is turned on, and the sense output DETA is forcibly set to high level by the high level of the signal SETB to start the oscillation circuit. The voltages VSN and VSP are used as bias voltages for operating with low current consumption, such as a CMOS inverter circuit for determining the high level / low level of the voltage vs.

  FIG. 23 shows a circuit diagram of an embodiment of the VPP charge pump circuit 2. In this embodiment, the internal step-down voltage VDL is used as an operating voltage in order to stably generate the high voltage VPP without being affected by fluctuations in the power supply voltage supplied from the external terminal. When the oscillation pulse OSCH is at a high level, the capacitors C8, C9, and C10 are charged up to the internal step-down voltage VDL. At the time of this charge-up, the boosted voltage charge-up MOSFET formed by the capacitor C7 is turned on, so that the charge up to the VDL is performed without level loss due to the threshold voltage.

  When the oscillation pulse OSCH changes to a low level, the capacitor C7 is charged up and a boosted voltage of 2VDL is generated in the capacitor C10. The 2VDL boosted voltage is obtained by supplying the 2VDL voltage to the capacitor C8 because the operating voltage of the CMOS inverter circuit composed of the MOSFETs Q71 and Q72 is the 2VDL boosted voltage formed by the capacitor C9. Then, a boosted voltage VPP ′ of 3 VDL is formed to turn on the output MOSFET. As a result, the 2VDL boosted voltage formed by the capacitor C10 is output as the boosted voltage VPP without any level loss.

  As described above, since the internal step-down voltage VDL is about 1.5V, the boost voltage VPP of about 3V at the maximum can be formed by the charge pump circuit of the above embodiment. In this embodiment, since the boosted voltage VPP only needs to be about 2.6V as described above, the boosted voltage VPP such as 2.6V is generated by the intermittent operation of the oscillation circuit described later.

  FIG. 24 shows a circuit diagram of an embodiment of the VPP oscillation circuit 1. The oscillation circuit 1 of this embodiment uses substantially the same circuit as the VBB oscillation circuit 6. However, it differs in that only one pulse is output like the oscillation pulse OSCH corresponding to the charge pump circuit as described above.

  FIG. 25 shows a circuit diagram of an embodiment of the level sensor 3 for the VPP. In this embodiment, the boosted voltage VPP is applied to the source of the P-channel MOSFET Q72 that receives the internal step-down voltage VDL. The MOSFET Q72 is provided with a MOSFET Q73 to which an activation signal NSENB that is temporarily set to a low level when power is turned on is supplied. In the steady state, the MOSFET Q73 is turned on, and the boosted voltage VPP is divided by the resistance ratio with the N-channel MOSFET Q74. This divided voltage is determined by the logic threshold of the inverter circuit composed of the N-channel MOSFETs Q76 and Q77 and the N-channel MOSFET Q78.

  That is, when the boosted voltage VPP is higher than the set value, the divided voltage becomes higher than the logic threshold voltage to form a low level output signal, which is amplified through a two-stage CMOS inverter circuit and the sense output DETH is set to low level. To do. As a result, the operation of the oscillation circuit is stopped. When the boosted voltage VPP becomes lower than the set value, the divided voltage becomes lower than the logic threshold voltage to form a high level output signal, which is amplified through a two-stage CMOS inverter circuit and the sense output DETH is set to high level. To do. Thereby, the operation of the oscillation circuit is resumed. When the power is turned on, the signal NSENB is set to the high level to turn off the P-channel MOSFET Q73 in the VPP sense path, and the N-channel MOSFET Q75 is turned on to turn off the amplification MOSFET Q76. As a result, the sense output DETH is forcibly set to a high level to operate the oscillation circuit.

  FIG. 26 shows a schematic overall configuration diagram of an embodiment of the dynamic RAM according to the present invention. The dynamic RAM includes a memory cell array MCA in which memory cells for storing information are arranged in a matrix state, one memory cell for accessing in one bit unit, and a plurality of memory cells for accessing in multiple bit units. X decoder XDEC, word driver WD and Y decoder YDEC for selecting memory cells, external control signals / RAS (row address strobe), / CAS (column address strobe), / WE (write enable) and / OE (output) Control circuit for controlling them in response to (enable enable).

  As described above, the memory cell of the dynamic RAM is composed of one capacitor and one transistor (MOSFET). In the figure, WD is a word driver as described above, and word lines Wi (i = 1 to n) are output. The word driver WD is selected by the previous X decoder XDEC. SA is a sense amplifier, bit and / bit are bit lines, and AC is an array control circuit. The AC outputs the equalize signal EQ and sense amplifier activation signal of the bit lines. The IOC is provided with a read amplifier (main amplifier) RA and a write amplifier WA that perform I / O line selection and data amplification during reading and writing.

  The memory read operation starts when the signal EQ becomes high level (VCH) and the bit line is equalized. The signal EQ becomes low level (VNN) and equalization is canceled, and the word line rises from the negative voltage VNN to a selection level such as VCH. Thereby, a signal appears on the bit line from the memory cell connected to the word line. Next, the sense amplifier is activated by the sense amplifier activation signals SAP and SAN. As a result, the signal on the bit line is set to a high level such as the external voltage Vext or the internal step-down voltage VDL as shown above and a low level such as the ground potential VSS. The row selection switch added to the bit line is selected by the output of the Y decoder YDEC, the bit line is connected to the input / output line I / O, and the data is sent out of the chip through the read amplifier RA and the output buffer included in the input / output buffer. Is output.

  In the memory write operation, the input buffer included in the input / output buffer is set in the operation state in the selection operation as described above, and the write data input from the outside of the chip is written into the write amplifier WA-input / output line I / O and row selection. Data is written to the capacitor of the memory cell through the switch-bit line.

  In this embodiment, a charge pump circuit VBBG for forming a negative back bias voltage VBB in a p-type well region where a memory cell is formed by a substrate voltage generation circuit as an internal power supply circuit, and the voltage VBB not shown in the drawing. The negative voltage VNN as the non-selection level of the word line is formed by the constant voltage circuit as described above. Further, the boosted voltage VPP is generated by the charge pump circuit VPPG, and a high voltage corresponding to the word line selection level VCH is generated by the constant voltage (not shown) based on the boosted voltage VPP. The high voltage VCH causes the capacitor to fully write the high level of the bit line as it is without being affected by the threshold voltage of the MOSFET constituting the memory cell. The substrate voltage VBB reduces the pn junction capacitance of the bit line and sense amplifier, or raises the threshold voltage of the MOSFET of the memory cell to improve the data retention characteristics, and absorbs minority carriers induced by α rays. And acts to reduce soft errors.

  The address signal Ai for selecting the memory cell is supplied to the decoders XDEC, YDEC, etc. via an address buffer. In the dynamic RAM, the X-system address signal is input in synchronization with the / RAS signal and the Y-system address signal is input in synchronization with the signal / CAS by the address multiplex method. The address buffer is provided with an address latch circuit and holds the address signal input in time series. Although omitted in the figure, in the dynamic memory cell, the information charge held in the capacitor is lost with time. Therefore, it is necessary to perform a refresh operation in which the charge is read out before being lost and returned to the original charge state. Although not shown in the figure, an automatic refresh control circuit for performing the refresh operation at regular time intervals is also provided in the control circuit.

  FIG. 27 is a circuit diagram showing another embodiment of the word driver in the dynamic RAM according to the present invention. The feature of this embodiment is that the above-mentioned hierarchical word line type sub-word driver is applied to a non-hierarchical word driver. That is, the decode signal X0 is used as the operating voltage of the word driver WDi. With this configuration, the switch MOSFET can be omitted, and the number of elements of the word driver WDi is as small as six in total despite the addition of a high breakdown voltage MOSFET, so that the pitch of the word lines is further increased. It can also be applied to small memory arrays.

  In this embodiment, a word circuit corresponding to four word lines is assigned to a logic circuit that forms a selection signal as the X decoder XDEC and two level conversion circuits LSP and LSN that perform level conversion of the output signal. On the other hand, the decode signal Xi may be expanded from the above four types to eight types and used in common for word drivers for eight word lines. In this case, since the layout pitch of the X decoder is further relaxed, the vertical dimension of the layout pattern (the direction in which the word lines extend) can be reduced by expanding the level conversion circuits LSP and LSN in the horizontal direction.

  FIG. 28 is a voltage characteristic diagram of one embodiment for explaining the relationship between the external voltage and the internal voltages VCH, VNN, and VDL in the dynamic RAM according to the present invention. In general, a semiconductor memory is subjected to an aging test or a burn-in test in which a defective element is removed by applying a voltage higher than a voltage normally used for identifying an initial defect before shipping. In this embodiment, this test is facilitated and the yield in the test is further improved. In this embodiment, two types of gate insulating films are used as described above, and both VCH and VDL are increased with a certain level difference in proportion to the external power supply voltage, and the level difference between the standard operating region and the burn-in region is reduced. It is intended to switch.

  On the other hand, the negative voltage VNN is kept constant regardless of the external power supply voltage. You may make it enlarge at the time of a burn-in. The VCH may increase the difference from the VDL by increasing the slope of the voltage change. However, in the above method, the VCH increases the resistance value of the resistor RL2 in FIG. There is an advantage that it can be easily realized simply by switching to. By switching the voltage as described above, the voltage can be set with high precision in the standard operation region and the burn-in region, so that the device can be prevented from being damaged due to excessive stress, and as a result, the yield can be increased. The VDL is equal to the external voltage Vext.

  FIG. 29 is a voltage characteristic diagram of another embodiment for explaining the relationship between the external voltage and the internal voltages VCH, VNN, and VDL in the dynamic RAM according to the present invention. In this embodiment, when the external power supply voltage is 2.5 V, the voltage is stepped down by using a voltage limiter so that the same type and thickness of the gate insulating film as in the embodiment of FIG. The internal voltage VDL in the region is set to 1.5V. Of the two types of MOSFETs, a thick gate insulating film MOSFET is used for an input buffer and an output buffer in addition to the word driver and memory cell, and a thin gate insulating film MOSFET is a peripheral circuit. And sense amplifier.

  The VCH and VDL are set at a constant level in the vicinity of the standard operation region regardless of the external power supply voltage, while they are increased in correspondence with the external power supply voltage in the vicinity of the burn-in region. The switching is performed between the standard operation area and the burn-in area, as in the embodiment of FIG. Negative voltage VNN is constant regardless of the external power supply voltage. Also in this embodiment, the VCH generates the reference voltage VRP based on the VDL as described above, and the resistance value of the resistor RL2 is switched in two stages to increase the difference voltage from the VDL in the burn-in region. . As a result, the voltage applied to the MOSFET can be set with high accuracy in both the standard operating region and the burn-in region, and the number of elements that become defective due to excessive stress can be reduced, so that the product yield can be increased.

  In the standard operation region, the VDL is generated by the same constant voltage circuit using the reference voltage VREF0. In the burn-in operation region, the VDL is changed to a voltage that changes depending on the external power supply voltage instead of the voltage VREF0. What is necessary is just to switch. As the voltage that changes depending on the external voltage, one end of the resistor is connected to VDL and the other end is connected to the ground potential VSS to a current mirror circuit by a reference N-channel MOSFET, and the voltage generated there is used. do it.

  FIG. 30 is a schematic layout diagram showing one embodiment of a dynamic RAM on which the power supply circuit according to the present invention is mounted. In this embodiment, although not particularly limited, the memory array is divided into four vertical and horizontal chips, and 16 memory cell arrays are formed in the entire chip. A central portion in the longitudinal direction of the chip is an indirect circuit region, and is provided with a peripheral circuit including a bonding pad indicated by □ arranged vertically and a power supply circuit. In the indirect circuit area, an address buffer circuit, a data input buffer, and a data output buffer are appropriately formed corresponding to the bonding pads.

  As described above, in each of the memory arrays consisting of a total of 16 pieces divided into 4 pieces in the vertical direction and 2 pieces in the left and right direction with respect to the longitudinal direction of the semiconductor chip, The main word selection circuit MWL is provided in the center portion divided into two. Although not shown, main word drivers are formed on the upper and lower sides of the main word selection circuit MWL adjacent to the memory cell arrays so as to drive the main word lines of the memory arrays divided in the upper and lower directions. A Y selection circuit YD is provided between two memory cell arrays arranged side by side in the horizontal direction of the chip.

  In the memory cell array, a plurality of memory mats are arranged in the longitudinal direction and in a direction perpendicular to the longitudinal direction (lateral direction). That is, one memory cell is divided into 8 in the longitudinal direction to provide 8 memory mats, and is divided into 16 in the perpendicular direction to provide 16 memory mats. In other words, the word line is divided into 8 and the bit line is divided into 16. As a result, the number of memory cells provided in one memory mat is divided into the above-mentioned 8 divisions and 16 divisions, and the memory access speed is increased. As will be described later, the memory mat has a sense amplifier region arranged on the left and right and a sub word driver region arranged on the top and bottom in the figure. The sense amplifier provided in the sense amplifier area is configured by a shared sense system, and except for the sense amplifiers arranged at both ends of the memory cell array, complementary bit lines are provided on the left and right with the sense amplifier as the center, and either the left or right Are selectively connected to complementary bit lines of the memory mat.

  As described above, the main memory selection circuit MWL and the main word driver are arranged in the central portion of the two memory arrays arranged in groups of two. The main word selection circuit MWL is provided in common corresponding to two memory arrays distributed up and down around the main word selection circuit MWL. The main word driver generates a selection signal for a main word line that extends so as to penetrate the one memory array. The main word driver is also provided with a sub word selection driver, which is extended in parallel with the main word line to form a selection signal for the sub word selection line, as will be described later.

  Although not shown, one memory mat has 256 sub-word lines, and 512 complementary bit lines (or data lines) orthogonal to the sub-word lines. In the one memory array, since 16 memory mats are provided in the bit line direction, the sub word lines as a whole are provided for about 8K, and the whole chip is provided for 16K. Further, in the one memory array, since eight memory mats are provided in the word line direction, a total of about 4K complementary bit lines are provided. Since four such memory arrays are provided in total, 16K complementary data lines are provided as a whole, and the overall storage capacity is set to have a large storage capacity such as 16K × 16K = 256M bits. The

  The one memory cell array is divided into eight in the main word line direction. A sub word driver (sub word line drive circuit) is provided for each of the divided memory cell arrays 15. The sub word driver forms a selection signal of a sub word line which is divided into a length of 1/8 with respect to the main word line and extends in parallel therewith. In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. 4 sub word lines are arranged. In order to select one sub word line from the sub word lines divided into eight in the main word line direction and four each in the complementary bit line direction, the sub word selection driver Be placed. This subword selection driver forms a selection signal for selecting one of the four subword selection lines extended in the arrangement direction of the subword drivers.

  Focusing on the one memory cell array, in the sub word driver corresponding to one memory mat including a memory cell to be selected among the eight memory cell arrays assigned to one main word line, one sub word selection line is provided. As a result of selection, one sub word line is selected from 8 × 4 = 32 sub word lines belonging to one main word line. Since 4K (4096) memory cells are provided in the main word line direction as described above, 4096/8 = 512 memory cells are connected to one sub word line. Although not particularly limited, in a refresh operation (for example, self-refresh mode), eight sub word lines corresponding to one main word line are set in a selected state.

  As described above, one memory array has a storage capacity of 4K bits in the complementary bit line direction. However, if 4K memory cells are connected to one complementary bit line, the parasitic capacitance of the complementary bit line increases, and a read signal level cannot be obtained due to the capacitance ratio with a fine information storage capacitor. In addition, it is divided into 16 in the complementary bit line direction. In other words, the complementary bit lines are divided into 16 divisions by the sense amplifiers arranged between the memory mats. Although not particularly limited, the sense amplifier is configured by the shared sense method as described above, and except for the sense amplifiers arranged at both ends of the memory cell array, complementary bit lines are provided on the left and right with the sense amplifier 16 as the center, It is selectively connected to either the left or right complementary bit line.

  In this embodiment, although not particularly limited, a total of four sets of constant voltage circuits RGP and RGN are provided corresponding to the embodiment of FIG. That is, two pairs (RGP and RGN) are assigned in the vertical direction across the bonding pad row. As a result, one set of constant voltage circuits (RGP and RGN) is responsible for four memory cell arrays. Although not particularly limited, the charge pump circuits VPPG and VBBG are provided in the center portion of the chip, and supply charge-pump voltages VPP and VBB to the four constant voltage circuits RGP and RGN. A reference voltage generation circuit RGFN provided in the center also supplies a constant voltage to each of the four sets of constant voltage generation circuits. In this configuration, the distances between the charge pump circuits VPPG and VBBG and the reference voltage generation circuit RGFN and each constant voltage circuit can be made uniform and short.

  FIG. 31 is a block diagram showing an embodiment of a single chip microcomputer to which the present invention is applied. Although not particularly limited, the single-chip microcomputer MCU of this embodiment is incorporated in an automobile or an industrial machine and functions as its control device.

  The microcomputer MCU shown in the figure is a central processing unit CPU of a so-called stored program system. The central processing unit CPU includes, but is not limited to, a read-only memory ROM, a random access memory RAM, an analog / digital conversion circuit A / D, a watchdog timer WDT, a timer circuit TIM, and a serial communication interface SCI via an internal bus IBUS. Combined. A predetermined clock signal CLK is supplied from the clock generation circuit CLKG to each part of the microcomputer MCU including the central processing unit CPU. The microcomputer MCU further controls a clock controller for controlling the operation of the clock generation circuit CLKG. CLKC and a power-on reset circuit POR for resetting each part of the microcomputer MCU to the initial state when the power is turned on.

  The watchdog timer WDT is supplied with the internal signal PR from the central processing unit CPU, and its output signal, that is, the abnormality detection signal TD is supplied to the clock controller CLKC. One input terminal of the clock generation circuit CLKG is coupled to one electrode of the crystal oscillator XTAL via the external terminal EXTAL, and the clock output signal CG of the clock controller CLKC is supplied to the other input terminal. The other electrode of the crystal oscillator XTAL is coupled to the clock controller CLKC via the external terminal XTAL.

  The power-on reset circuit POR is supplied with the power supply voltage VCC and the ground potential VSS, which are the operation power supply of the single-chip microcomputer MCU, via the external terminals VCC and VSS, respectively. It is supplied to the controller CLKC. The clock controller CLKC is further supplied with an output signal RSTP of the complete stop control register RSTP and an output signal RCMD of the mode control register RCMD from the central processing unit CPU. The output signal, that is, the normal reset signal RS is sent to the central processing unit CPU. It is supplied to each part of the microcomputer MCU.

  The central processing unit CPU performs step operations according to a user program stored in a read-only memory ROM, executes predetermined arithmetic processing, and controls and supervises each part of the microcomputer. In this embodiment, the central processing unit CPU includes a complete stop control register and a mode control register which can be written by an instruction, and output signals RSTP and RCMD are supplied to the clock controller CLKC as described above. Further, the internal signal PR indicating the program execution status of the central processing unit CPU is constantly monitored by the watchdog timer WDT and used for detecting an abnormality of the microcomputer MCU. The read-only memory ROM is composed of, for example, a mask ROM having a predetermined storage capacity, and stores programs and fixed data necessary for controlling the central processing unit CPU. The random access memory RAM is composed of, for example, a static RAM having a predetermined storage capacity, and temporarily stores calculation results and control data of the central processing unit CPU. The flash EPEOM is an electrically rewritable ROM and stores data to be held when the power is turned off.

  The analog / digital conversion circuit A / D converts an analog input signal input from various external sensors into a digital signal of a predetermined bit and transmits it to the central processing unit CPU or the like via the internal bus IBUS. In this embodiment, the reference voltage Vref used to form the precharge / discharge voltage as described above is supplied. This reference voltage Vref is also supplied to the A / D converter and may be used as a reference voltage for the A / D conversion operation. Sampling clocks and precharge / discharge clocks used for the sample-and-hold means, precharge / discharge means, etc., included in the analog / digital converter A / D are formed based on the clock formed by the clock generation circuit CPG. The The same applies to the clock signal used for the A / converter ADC itself.

  The timer circuit TIM measures time according to the clock signal supplied from the clock generation circuit CPG, and the serial communication interface SCI is a high-speed connection between the serial input / output device coupled to the outside of the microcomputer and the random access memory RAM, for example. Support data transfer.

  The watchdog timer WDT monitors the internal signal PR output from the central processing unit CPU. In response to the fact that the internal signal PR is not formed over a predetermined time, in other words, the instruction fetch by the central processing unit CPU is long. In response to not being performed over a period of time, an abnormality of the central processing unit, that is, the microcomputer is detected, and its output signal, that is, the abnormality detection signal TD is selectively set to the high level. The power-on reset circuit POR monitors the potential of the power supply voltage VCC and the ground potential VSS supplied via the external terminals VCC and VSS, and when the operation power is turned on, its output signal, that is, the power-on reset signal POR. Is temporarily set to the high level for a predetermined period. The abnormality detection signal TD from the watchdog timer WDT and the power-on reset signal POR from the power-on reset circuit POR are supplied to the clock controller CLKC.

  A clock that can selectively stop the operation of a clock generation circuit in response to detection of an abnormality by a watchdog timer or writing of a predetermined register by a command from a central processing unit in a single chip microcomputer incorporated in an automobile or industrial machine A controller is provided, and this complete stop state can be released only by a power-on reset signal when the power is turned on again. When an abnormality occurs, the operating power is turned off and then turned on again. The operation can be stopped completely.

  The above power supply circuit POW for generating internal voltages such as the internal voltages + V and + V ′ and −V and −V ′ of the microcomputer as described above is mounted. This power supply circuit generates a stable internal voltage + V, + V ′ and −V, −V ′ by combining a charge pump circuit and a constant voltage circuit. The voltages + V and −V are not particularly limited, but are high voltages such as 12V and −12V, and are used as write and erase voltages of the FEPROM.

  As a result, rewriting is possible with the FEPROM mounted in the system. −V and −V ′ are operating voltages of the A / D converter. Since the A / D converter is operated with two positive and negative voltages in this way, an analog signal can be directly supplied from an external terminal. In other words, an analog signal can be input without providing a DC blocking coupling capacitor as in the case of an A / D converter circuit operated by a single power supply, so that an input signal of a low frequency can be received and a large capacity externally attached. Capacity is useless.

  FIG. 32 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, a P-channel MOSFET is used as an input transistor so that a sufficient current flows through the differential amplifier even when the threshold voltage of the MOSFET becomes high, and a P-channel output buffer can be driven as usual. A push-pull conversion circuit having a double-end configuration is provided.

  The potentials of the nodes (a) and (b) formed by the base-emitter voltages of the transistors T3 and T4 are as low as 0.6V to 0.7V. For this reason, in the embodiment circuit shown in FIG. 17, in the MOSFET for the power supply voltage of 3.3V to 5V, the threshold voltage is almost the same as the potentials of the nodes (a) and (b), and sufficient. Since no current can flow, power-on characteristics, stability, and the like deteriorate. In particular, when the power is turned on, the potentials of the nodes (a) and (b) are 0 V, so that there is a possibility that the differential amplifier cannot operate and the reference voltage Vref does not rise.

  In this embodiment, since the relatively low voltages at the nodes (a) and (b) are received by the P-channel MOSFETs MP1 and MP2, the threshold voltages of the MOSFETs MP1 and MP2 are set high as described above. In this case, a sufficient gate-source voltage can be secured, and a larger amount of current can flow. As a result, the power-on characteristics and stability can be improved.

  In order to make the reference voltage Vref based on the ground potential VSS, it is necessary to connect the base or emitter terminal of the bipolar transistor to the ground potential VSS. In order to operate this from a low power supply voltage, a driver for a P-channel MOSFET is required. When this is driven by a normal P-channel MOSFET input current mirror load type amplifier, the high level is not sufficiently obtained, and the P-channel type MOS driver cannot be cut off. In this embodiment, in order to solve this problem, a push-pull conversion circuit having a double-end configuration is provided to ensure a sufficiently high level.

  That is, the N-channel MOSFET Q80 in the form of a diode and the N-channel MOSFET Q81 in the form of a current mirror are connected between the drain of one P-channel MOSFET MP1 constituting the differential amplifier and the circuit ground potential. The MOSFET Q81 drives a diode-shaped P-channel MOSFET Q82 provided on the power supply voltage side. A diode-shaped N-channel MOSFET Q83 and an N-channel MOSFET Q84 in the form of a current mirror are also connected between the drain of the other P-channel MOSFET MP2 constituting the differential amplifier and the ground potential of the circuit. A double-end push-pull conversion circuit is configured by connecting the drain of the MOSFET Q84 and the drain of the P-channel MOSFET Q85 that is current-mirror connected to the P-channel MOSFET Q82. This push-pull circuit drives the P-channel MOSFET MP3 and drives the transistors T3 and T4. The P-channel MOSFET Q87 has a gate that is steadily connected to the circuit ground potential and acts as a resistance element to raise the potential of the nodes (a) and (b) at power-on. Therefore, the on-resistance value is set sufficiently large.

  In this embodiment, even if the threshold voltage of the MOSFET increases, it can be stably operated from a sufficiently low power supply voltage. In addition, the start-up at power-on is fast and the stability can be enhanced.

  FIG. 33 is a circuit diagram showing another embodiment of the power supply circuit according to the present invention. In this embodiment, the frequency of the oscillation pulse for operating the charge pump circuit is devised so as to change in accordance with the load current.

  As a charge pump circuit, in order to reduce current consumption, it is conceivable to set the frequency of the oscillation circuit to two types according to operation and standby. However, in this configuration, it is necessary to determine the oscillation frequency according to the maximum current in each mode. As described above, in a circuit that operates with a low power supply voltage, it is necessary to lower the threshold voltage of the MOSFET in order to achieve high-speed operation. For this reason, a relatively large subthreshold leakage current flows even when the circuit is not operating as in the standby state, that is, in the off-state MOSFET. Since this current changes exponentially with respect to temperature, it is necessary to set the oscillation frequency to be high accordingly, and there is a problem that the current consumption becomes larger than necessary.

  In this embodiment, a P-channel type current detection MOSFET M2 is provided in parallel with a P-channel type output MOSFET M1 that forms a boosted voltage VCH. In this MOSFET M2, a detection current kIL corresponding to the size ratio k with the output MOSFET M1 is formed, and the current kIL is passed through a diode-shaped N-channel type MOSFET M3, and a voltage signal CFB corresponding thereto is supplied. This is supplied to the oscillation circuit so that the oscillation frequency is continuously changed. That is, the oscillation circuit is controlled so that the oscillation frequency becomes higher in response to the increase in the detection current kIL.

  FIG. 34 shows a circuit diagram of an embodiment of an oscillation circuit used in the embodiment circuit of FIG. As the oscillation circuit, a ring oscillator in which inverter circuits are cascade-connected in a ring shape is used. The N-channel MOSFETs M5 to M9 through which the operation current of each inverter circuit flows are made into a current mirror form with the N-channel MOSFET M3 that performs the current detection. That is, the signal CFB is supplied to the gates of the MOSFETs M5 to M9.

  The signal CFB is converted into an aIL current by the N-channel MOSFET M4 supplied to the gate, and the current CFB is supplied to the P-channel MOSFET M10 in the form of a diode. M15 and a current mirror form are used, the delay time of each inverter circuit is controlled in accordance with the signal CFB, the delay time is changed in inverse proportion to the increase in current, and the oscillation frequency is controlled.

  When the load current IL of the power supply circuit increases, the oscillation frequency increases and the number of charge pumps per unit time increases, so that the power supply circuit has a current supply capability corresponding to the increase of the load current. At this time, since the duty ratio of the oscillation output pulse is kept substantially constant, the efficiency of the charge pump circuit is also substantially constant.

  According to this embodiment, even if the threshold voltage of the MOSFET decreases or the load current increases due to high temperature, the oscillation frequency of the oscillation pulse input to the charge pump circuit automatically responds accordingly. The current supply capacity will not be insufficient. In addition, since the oscillation frequency is automatically lowered and the current consumption is reduced at a low temperature, it is suitable for a power supply circuit mounted on a portable electronic device in which low current consumption is important.

  In the above embodiment, the booster circuit has been described as an example, but it goes without saying that the present invention can be similarly applied to a negative charge pump circuit that forms a negative voltage.

  FIG. 35 is a circuit diagram showing one embodiment of the output circuit according to the present invention. This embodiment is directed to a push-pull output circuit devised so as to enhance the driving capability while reducing the leakage current. In the circuit of this embodiment, like the sense amplifier driving circuit shown in FIG. 1, the N-channel type driving MOSFET MO1 and the P-channel type driving MOSFET MO2 have a low threshold voltage in order to enhance the driving capability. In order to reduce the direct current (through current) flowing through both MOSFETs MO1 and MO2 due to the subthreshold leakage current when these MOSFETs MO1 or MO2 are in the off state, the MOSFETs MO1 and MO2 are supplied in the off state. Level conversion circuits LSN and LSP are provided for generating an input signal such that the source and gate are in a reverse bias state.

One level conversion circuit LSN receives an input signal such as VSS-VDD and converts the level to VDD-VNN. As a result, in a state where VNN is output, a reverse bias voltage of VNN-VSS is applied between the gate and source of the MOSFET MO1. The other level conversion circuit LSP receives an input signal such as VSS-VDD and converts the level to VCH-VSS. Therefore, when VCH is output, a reverse bias voltage of VDD-VCH is applied between the gate and the source of MOSFET MO2.
The VDD may be formed inside the semiconductor integrated circuit device, or may be an operation voltage supplied from an external terminal as it is.

  In this embodiment, in the CMOS (push-pull) circuit, the threshold voltage of the output MOSFET is reduced to enhance the driving capability, and the level conversion circuit is used for the driving circuit for driving the signal to turn it off. By setting the level to a voltage that causes the gate and source of the MOSFET to be in a reverse bias state, it is possible to suppress the through current due to the subthreshold leakage current. Therefore, it is suitable for a circuit or system that operates at a low voltage of 3 V or less.

  FIG. 36 is a circuit diagram showing one embodiment when the output circuit according to the present invention is applied to an output buffer. Even in the output buffer of this embodiment, it is possible to suppress the through current due to the subthreshold leakage current while enhancing the driving capability. In this embodiment circuit, resistors Rg1 and Rg2 and gate protection MOSFETs ME2 and ME1 are inserted between the level conversion circuits LSP and LSN and the gates of the output MOSFETs MO2 and MO1.

  The resistors Rg1 and Rg2 act to prevent overshoot and undershoot by lengthening the change time of the gate voltage of the drive MOSFET and dulling the rising and falling waveforms of the output.

  The gate protection MOSFETs ME1 and ME2 function to prevent the gate insulating films (oxide films) of the output MOSFETs MO1 and MO2 from being destroyed when a high voltage is applied to the output terminal DO from the outside. That is, when the potential of the output terminal DO is raised to the power supply voltage VDD or higher, the P-channel MOSFET ME1 is turned on to short-circuit the gate of the output MOSFET MO2 and the output terminal DO, and the potential of the output terminal DO is equal to or lower than the ground potential VSS. In this case, the N-channel MOSFET ME2 is turned on to short-circuit the gate of the output MOSFET MO1 and the output terminal DO so that a high voltage is not applied to the gate insulating film.

  In this embodiment, different input signals are input to the level conversion circuits LSN and LSP via a control circuit such as a gate circuit or an inverter circuit controlled by an output control signal HIZ. By this control circuit, the through current of the output buffer is prevented, and both the output MOSFETs MO1 and MO2 are both turned off to make an output high impedance state.

  In the circuit of this embodiment as described above, in the push-pull type output buffer, it is possible to suppress the through current due to the subthreshold leakage current while enhancing the driving capability. Therefore, it is suitable for a circuit or system that operates at a low voltage of 3 V or less.

The effects obtained from the above embodiment are as follows.
(1) In a semiconductor integrated circuit device comprising a first circuit block operated by a power supply voltage supplied from an external terminal and a second circuit block operated by an internal voltage formed by the power supply circuit, A voltage that is large in absolute value with respect to the internal voltage is formed by the charge pump circuit, variable impedance means is provided between the output voltage and the internal voltage, and the output voltage formed by the charge pump circuit is used as the operating voltage. By comparing the reference voltage and the internal voltage by the differential amplifier circuit, and controlling the variable impedance means so that the two coincide with each other, the internal voltage is formed to stably generate an arbitrary internal voltage. The effect of being able to be obtained.

(2) By providing two types of the power supply circuit, it is possible to stabilize a voltage having the same polarity as the voltage supplied from the external terminal by the power supply circuit and having a large absolute value or a voltage different from the voltage supplied from the external terminal. The effect that it can generate | occur | produce automatically is acquired.

(3) By forming the word line selection level and negative voltage non-selection level of the dynamic RAM with the power supply circuit, it is possible to improve the data retention characteristics of the memory cells and to ensure the high reliability of the device. The effect is obtained.

(4) As a differential amplifier circuit provided in the power supply circuit, one that is steadily operated with a current that is small enough to maintain the internal voltage, and one that corresponds to when the internal circuit is brought into an operating state. By combining with the one that can be operated with a large current required to maintain the internal voltage, an effect that a necessary voltage can be formed with low power consumption can be obtained.

(5) An output voltage formed by the charge pump circuit of the first power supply circuit is applied to a deep N-type well region where a P-type well region where the dynamic memory cell is formed is formed. As a result, it is possible to use the parasitic capacitance there and to eliminate the need for special measures for latch-up.

(6) The output voltage formed by the charge pump circuit of the second power supply circuit is also used as a substrate back bias voltage applied to the P-type well region where the dynamic memory cell is formed. In addition to being able to use the junction capacitance, it is possible to improve the soft error due to α rays and to simplify the circuit by sharing it.

(7) The internal circuit includes a third power supply circuit that steps down the power supply voltage supplied from the external terminal to form a constant voltage, and a circuit that is operated by the stepped down voltage formed by the third power supply circuit. By comprising the part, the effect that the internal circuit can be stably operated without the dependence of the external power supply can be obtained.

(8) An output circuit that constitutes the internal circuit and outputs a high level formed by the first power supply circuit and a low level formed by the second power supply circuit, and is formed by the first power supply circuit. The ground potential is supplied to the gates for the first conductivity type output MOSFET that outputs the internal voltage and the second conductivity type output MOSFET that outputs the internal voltage formed by the second power supply circuit. Since the first conductivity type MOSFET and the second conductivity type MOSFET whose internal voltage is supplied to the gate are provided in series, the voltage applied to each MOSFET can be divided to ensure high reliability. The effect that it can do is acquired.

(9) As a first drive circuit for forming a drive signal to be supplied to the first conductivity type output MOSFET gate constituting the output circuit, the internal circuit operated by the power supply voltage or the internal step-down voltage and the ground potential of the circuit A first level conversion circuit that converts an input signal formed by the circuit into a first signal level corresponding to the output voltage of the first power supply circuit and the ground potential of the circuit, and the second that constitutes the output circuit. As a second drive circuit for forming a drive signal supplied to a conductive type output MOSFET gate, the input signal is converted into a second signal level corresponding to the internal voltage and the output voltage of the second power supply circuit. By using the second level conversion circuit, it is possible to obtain an effect that it is possible to secure a high reliability that can suppress the voltage applied to the output MOSFET.

(10) The gate insulating film of the address selection MOSFET that constitutes the dynamic memory cell and the gate insulating film of the output MOSFET that forms the word line selection signal are set to the same first film thickness, By setting the gate insulating film of the MOSFET constituting the address selection circuit to the second film thickness that is made thinner than the first film thickness, it is possible to achieve high reliability and high speed operation. Is obtained.

(11) The internal circuit includes a plurality of geometrically separated circuits, and the power supply circuit corresponds to the plurality of circuits on a one-to-one basis, and has the same polarity as the voltage supplied from the external terminal and is absolute A plurality of first power supply circuits for generating a large voltage, and a plurality of second power supply circuits for generating a voltage having a polarity different from the voltage supplied from the external terminal, and the first and second charge pump circuits. By providing a plurality of the variable impedance means and the differential amplifier circuit adjacent to each of the plurality of circuits in common, it is possible to supply an efficient operating voltage while simplifying the circuit. An effect is obtained.

(12) A memory array in which a plurality of the dynamic memory cells are arranged in a matrix is divided into a plurality of sets, and the first and second charge pump circuits are shared as the first and second power supply circuits. Thus, by providing a plurality of variable impedance means and differential amplifier circuits corresponding to each set of memory arrays, efficient operation voltage supply and storage capacity can be achieved while simplifying the circuit. The effect that it can be made large is obtained.

(13) The internal circuit is applied to a one-chip microcomputer including a central processing unit, a flash EPROM, and an analog / digital conversion circuit. The first power supply circuit and the second power supply circuit are connected to the flash EPROM and the analog / digital By forming positive and negative voltages used for the operation of the conversion circuit, it is possible to input analog signals as they are without erasing stored information on-chip and using a coupling capacitor.

(14) As the internal circuit, a P-channel MOSFET that outputs the power supply voltage or lower voltage, an N-channel MOSFET that outputs the ground potential of the circuit, and an output voltage or charge pump output of the first power supply circuit And a circuit used for a signal level for turning off the P-channel MOSFET by a voltage, and for a signal level for turning off the N-channel MOSFET by an output voltage of the second power supply circuit or a charge pump output voltage. As a result, the MOSFET can be turned off in the reverse bias state between the source and the gate, so that the effect of greatly reducing the threshold leak current can be obtained.

(15) As the reference voltage, a constant voltage formed using a silicon band gap formed corresponding to a difference in emitter current density is converted into a constant current by a voltage-current conversion circuit, and a current mirror including one or a plurality of current mirrors. By converting the constant current from the current mirror circuit to which the charge pump voltage constituting the power supply circuit is applied through the circuit and flowing it to one end of the resistor, and connecting the other end of the resistor to a predetermined internal voltage terminal It is possible to obtain an effect that a highly accurate and highly stable voltage setting can be easily performed.

(16) One end of the first resistor having a large resistance value is connected to the emitter of the first transistor in which the emitter area is small and the common base and collector are connected to the ground potential of the circuit. The emitter of the second transistor having a large emitter area and having a common base and collector connected to the ground potential of the circuit is made to be negligibly small compared to the resistance value of the first resistor. One end of the resistor is connected, and the other end is connected to one end of a third resistor having a resistance value substantially the same as that of the first resistor, and the emitter potential of the first transistor, the second resistor, and the third resistor are connected. A differential amplifier circuit including a P-channel type differential MOSFET that receives the potential at the connection point of the resistor forms a voltage so that the two voltages are the same, and the first resistor and the third resistor By forming the constant voltage is supplied to the commonly connected other end, the effect of being able to form a stable constant voltage to a low voltage is obtained.

(17) In the power supply circuit, a current sense MOSFET is provided in which a gate and a source are commonly connected to the MOSFET constituting the variable impedance means, and a sense current corresponding to a load current is formed by a small MOSFET corresponding to the size ratio. By controlling the pumping cycle of the charge pump circuit with an oscillation pulse formed by an oscillation circuit whose oscillation frequency is changed in response to the sense current, an effect that the efficiency of the charge pump circuit can be increased is obtained. It is done.

  The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the specific configuration of each circuit constituting the dynamic RAM and the layout configuration thereof can take various embodiments. The constant voltage circuit can take various embodiments, such as a differential amplifier circuit and a MOSFET as a variable resistance element, as well as a source follower MOSFET in which a constant voltage is applied to the gate. The input / output interface of the dynamic RAM can take various embodiments such as one corresponding to the synchronous DRAM or one corresponding to the Rambus specification.

  The present invention can be widely used in various semiconductor integrated circuit devices that require an internal voltage different from the voltage supplied from an external terminal, such as the above-described dynamic RAM and one-chip microcomputer. It is.

1 is a schematic circuit diagram showing one embodiment of a memory array portion of a dynamic RAM according to the present invention. 1 is a schematic circuit diagram showing an embodiment of a power supply circuit section of a dynamic RAM according to the present invention. FIG. 5 is a waveform diagram for explaining a schematic operation of the dynamic RAM according to the present invention. 1 is a schematic device sectional view showing an embodiment of a dynamic RAM according to the present invention. FIG. 5 is a schematic element cross-sectional view showing another embodiment of the dynamic RAM according to the present invention. 3 is a circuit diagram showing one embodiment of a word driver WD in the dynamic RAM according to the present invention. FIG. FIG. 7 is a waveform diagram for explaining the operation of the word driver of FIG. 6. It is a circuit diagram showing another embodiment of the word driver WD in the dynamic RAM according to the present invention. It is a wave form diagram for demonstrating operation | movement of the word driver of FIG. It is a block diagram which shows one Example at the time of applying this invention to a hierarchical word driver. FIG. 11 is a circuit diagram showing one embodiment of a sub word driver SDRV corresponding to the hierarchical word driver system of FIG. 10. FIG. 12 is a circuit diagram showing an embodiment of a driver for driving the sub word selection line and the main word line of FIG. 11. It is a wave form diagram for demonstrating operation | movement of the circuit of FIG. FIG. 6 is a schematic block diagram showing another embodiment of the power supply circuit in the dynamic RAM according to the present invention. FIG. 12 is a circuit diagram showing another embodiment of a sub word selection line driver and sub word driver corresponding to the hierarchical word driver system. FIG. 16 is a waveform diagram for explaining the operation of the circuit of FIG. 15. It is a circuit diagram which shows one Example of a reference voltage generation circuit. FIG. 3 is a circuit diagram showing an embodiment of the constant voltage generation circuit RGP of FIG. 2. FIG. 3 is a circuit diagram showing an embodiment of the constant voltage generation circuit RGN of FIG. 2. FIG. 3 is a circuit diagram showing one embodiment of a VBB charge pump circuit 7 of FIG. 2. FIG. 3 is a circuit diagram showing an example of the VBB oscillation circuit 6 of FIG. 2. FIG. 3 is a circuit diagram showing an example of the VBB level sensor 8 of FIG. 2. FIG. 3 is a circuit diagram showing an embodiment of the VPP charge pump circuit 2 of FIG. 2. FIG. 3 is a circuit diagram showing an embodiment of the VPP oscillation circuit 1 of FIG. 2. FIG. 3 is a circuit diagram showing an example of the VPP level sensor of FIG. 2. 1 is a schematic configuration diagram showing an example of an entire dynamic RAM according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the word driver in the dynamic RAM according to the present invention. FIG. 6 is a voltage characteristic diagram showing an embodiment for explaining the relationship between an external voltage and internal voltages VCH, VNN, and VDL in the dynamic RAM according to the present invention. It is a voltage characteristic diagram showing another embodiment for explaining the relationship between the external voltage and the internal voltages VCH, VNN, and VDL in the dynamic RAM according to the present invention. 1 is a schematic layout diagram showing one embodiment of a dynamic RAM on which a power supply circuit according to the present invention is mounted. 1 is a block diagram showing an embodiment of a single chip microcomputer to which the present invention is applied. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. It is a circuit diagram which shows another Example of the power supply circuit which concerns on this invention. It is a circuit diagram which shows one Example of the oscillation circuit used for the power supply circuit of FIG. 1 is a circuit diagram showing an embodiment of an output circuit according to the present invention. 1 is a circuit diagram showing an embodiment in which an output circuit according to the present invention is applied to an output buffer. FIG.

Explanation of symbols

MCA ... memory cell array, XDEC ... X decoder, WD ... word driver, AC ... array control circuit, SAND, SAPD ... sense amplifier driver, W1-Wn ... word lines,
DESCRIPTION OF SYMBOLS 1 ... VPP oscillation circuit, 2 ... VPP charge pump circuit, 3 ... VPP level sensor, 5 ... Internal step-down circuit, 6 ... VBB oscillation circuit, 7 ... VBB charge pump circuit, 8 ... VBB level sensor,
RGFP, RGFN, reference voltage generation circuit, RGP, RGN, constant voltage circuit, DWELL, deep n-type well region, pWELL, p-type well region, nWELL, n-type well region,
LSP, LSN ... level conversion circuit, AN1 to AN4 ... logic circuit, FDRV0 to MDRVi ... driver, MAT0 to MAT1 ... memory mat, SWD0 to 2 ... subword driver,
VBBG ... VBB generation circuit, VPPG ... VPP generation circuit,
T1, T2 ... Transistor, Q1-Q78 ... MOSFET, MP1, MP2 ... MOSFET, MN1, MN2 ... MOSFET, M1-M9 ... MOSFET, C1-C14 ... Capacitor, RF, RL1, RL2 ... Resistance,
MWL ... Main word driver, YD ... Y driver,
MCU ... Single-chip microcomputer, CPU ... Central processing unit, IBUS ... Internal bus, POW ... Power supply circuit, ROM ... Read only memory, FEPROM ... Flash EPROM, RAM ... Random access memory, A / D (ADC) ... Analog / digital conversion Circuit, WDT ... watchdog timer, TIM ... timer circuit, SCI ... serial communication interface, POR ... power-on reset circuit, CLKC ... clock controller, CLKG ... clock generation circuit, XTAL ... crystal oscillator.

Claims (11)

The external power supply operates with an external power supply voltage supplied from an external terminal, and has the same polarity as the external power supply voltage and an absolute value larger than the external power supply voltage, and the same polarity as the external power supply voltage. A first power supply circuit that generates a second internal voltage that is larger in absolute value than the voltage and smaller in absolute value than the first internal voltage;
A third internal voltage that operates with the external power supply voltage, has a polarity different from that of the external power supply voltage, and is absolute greater than that of the external power supply voltage, and an absolute value that is different from that of the external power supply voltage and that has an absolute value greater than that of the external power supply voltage A second power supply circuit that generates a fourth internal voltage that is significantly larger than the third internal voltage and absolutely smaller than the third internal voltage;
An internal circuit to which the second and fourth internal voltages formed by the first and second power supply circuits are applied,
The first internal voltage is applied to an N-type well region in which a P-type well region in which elements constituting the internal circuit are formed is formed,
3. The semiconductor integrated circuit device according to claim 1, wherein the third internal voltage is also used as a substrate back bias voltage applied to the P-type well region in which elements constituting the internal circuit are formed. In claim 1,
The first power supply circuit includes:
A first charge pump circuit for forming the first internal voltage;
First variable impedance means for outputting the second internal voltage provided between the output voltage formed by the first charge pump circuit and the external power supply voltage;
The output voltage formed by the first charge pump circuit is used as an operating voltage, the first reference voltage is compared with the second internal voltage, and the first variable impedance means is controlled so that they match. A first differential amplifier circuit comprising:
The second power supply circuit includes:
A second charge pump circuit for forming the third internal voltage;
A second variable impedance means provided between the output voltage formed by the second charge pump circuit and the external power supply voltage for outputting the fourth internal voltage;
The output voltage formed by the second charge pump circuit is used as an operating voltage, the second reference voltage is compared with the fourth internal voltage, and the second variable impedance means is controlled so that they match. A second differential amplifier circuit comprising:
A semiconductor integrated circuit device. In claim 1,
The internal circuit includes an output circuit that outputs a high level formed by the first power supply circuit and a low level formed by the second power supply circuit,
The output circuit is
An output MOSFET of a first conductivity type that outputs the second internal voltage formed by the first power supply circuit;
A second conductivity type output MOSFET for outputting the fourth internal voltage formed by the second power supply circuit;
A first conductivity type MOSFET in which a source-drain path is connected between the first conductivity type output MOSFET and an output terminal, and a ground potential is supplied to the gate;
A semiconductor comprising: a second conductivity type MOSFET having a source-drain path connected between the second conductivity type output MOSFET and an output terminal, and an internal step-down voltage supplied to the gate. Integrated circuit device. In claim 3,
The first conductivity type output MOSFET gate constituting the output circuit is provided with a first drive circuit for forming a drive signal thereof,
In the first driving circuit, an input signal formed by an internal circuit operated by the external power supply voltage or the internal step-down voltage and the ground potential of the circuit corresponds to the second internal voltage and the ground potential of the circuit. A first level conversion circuit for converting to a first signal level;
The second conductivity type output MOSFET gate constituting the output circuit is provided with a second drive circuit for forming a drive signal thereof,
The second drive circuit comprises a second level conversion circuit for converting the input signal into a second signal level corresponding to the internal step-down voltage and the fourth internal voltage. . In claim 1,
The internal circuit includes a dynamic memory cell including an address selection MOSFET and a storage capacitor as a storage cell, a word line to which a gate of the address selection MOSFET is connected, a bit line to which a drain of the address selection MOSFET is connected, A sense amplifier that amplifies a signal read to the bit line; an output MOSFET that forms a selection signal for the word line; and a memory circuit that includes an address selection circuit that forms the selection signal.
The gate insulating film of the address selection MOSFET and the gate insulating film of the output MOSFET that forms the selection signal of the word line to which the gate of the address selection MOSFET is connected are set to the same first film thickness,
The gate insulating film of the MOSFET that constitutes the sense amplifier that amplifies the read signal of the dynamic memory cell and the address selection circuit is set to a second film thickness that is thinner than the first film thickness. A semiconductor integrated circuit device, comprising: In claim 2 ,
The internal circuit is composed of a plurality of circuits,
Said first and second power supply circuit, the first and by the second charge pump circuit in common, the variable impedance means and the first and second of to the first and second adjacent each said plurality of circuits the semiconductor integrated circuit device, characterized in that the second differential amplifier circuit is one that is provided. In claim 6,
Each of the plurality of circuits comprises a memory array in which a plurality of dynamic memory cells are arranged in a matrix, a sense amplifier, and an address selection circuit corresponding to the memory array. In claim 1,
The internal circuit is
Central processing unit,
Flash EPROM,
Including analog / digital conversion circuit,
The semiconductor integrated circuit device, wherein the first power supply circuit and the second power supply circuit form positive and negative voltages used for the operation of the flash EPROM and the analog / digital conversion circuit. In claim 1,
The internal circuit is
A P-channel MOSFET for outputting the external power supply voltage or lower voltage; an N-channel MOSFET for outputting the ground potential of the circuit;
And a circuit used for a signal level for turning off the P-channel MOSFET by the second internal voltage and used for a signal level for turning off the N-channel MOSFET by the fourth internal voltage. A semiconductor integrated circuit device.
In claim 2 ,
The first reference voltage is
A voltage-current conversion circuit that converts a constant voltage formed using a silicon band gap formed corresponding to the emitter current density difference into a constant current;
The constant current is converted into a constant current from a current mirror circuit to which a charge pump voltage constituting the first power supply circuit is applied via a current mirror circuit composed of one or a plurality of currents, and the constant current is supplied to one end of the resistor. A semiconductor integrated circuit device, wherein the other end is connected to a predetermined internal voltage terminal. In claim 2 ,
The first power supply circuit includes:
A current sense MOSFET is provided in which a gate and a source are commonly connected to the MOSFET constituting the first variable impedance means, and a sense current corresponding to a load current is formed by a small MOSFET corresponding to the size ratio,
A semiconductor integrated circuit device, wherein the pumping cycle of the first charge pump circuit is controlled in response to an oscillation pulse formed by an oscillation circuit whose oscillation frequency is changed corresponding to the sense current .

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