JPH06325568A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain an output reference voltage equal to a constant voltage being fed between gate and source by connecting a plurality of MOSFETs, for receiving the constant voltage and forming a constant current, in series between the gate and the source and then feeding a constant current. CONSTITUTION:A MOSFET M1 receives, at the gate thereof, the ground voltage of the circuit and forms a reference current. The reference current is fed to a MOSFET M2 constituting a diode connected with two MOSFETs M3, M8 constituting a current mirror. A constant current is fed between the gate and source using a MOSFET having the same structure as the M1 which receives a constant voltage to form a constant current and a plurality of MOSFETs are connected in series to constitute a diode. Consequently, the voltage between the gate and source of the plurality of MOSFETs is equalized to the constant voltage being fed between the gate and source of the MOSFET and an output reference voltage is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a RAM (random access memory) used as an operating voltage of an internal circuit by stepping down a power supply voltage supplied from the outside by an internal step-down voltage circuit. It is related to effective technology.

[0002]

2. Description of the Related Art A RAM using a dynamic memory cell composed of an information storage capacitor and an address selection MOSFET (insulated gate field effect transistor).
As (random access memory), there is “VLSI LSI Dictionary” page 495 issued by Sanence Forum Co., Ltd.

[0003]

The applicant of the present application has previously developed a dynamic RAM capable of being operated by a plurality of types of batteries. In this case, in order to maintain compatibility with the conventional RAM, it is necessary to operate the internal circuit even when supplied with a relatively high voltage such as 5V. Therefore, it is considered that an internal voltage down converter is provided and a constant voltage of about 3 V is generated to operate the internal circuit. In this case, it is necessary to form a stable constant voltage over a wide range from a relatively high voltage such as about 5V to a low voltage such as a battery voltage. An object of the present invention is to provide a semiconductor integrated circuit device provided with a reference voltage generating circuit capable of obtaining a stable reference voltage for a relatively wide range of power supply voltages. Another object of the present invention is to provide a semiconductor integrated circuit device including a RAM that operates stably with respect to a wide range of external power supply voltages. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0004]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a MOSFET having the same structure as the first MOSFET that receives a constant voltage between the gate and the source to form a constant current is used, and the above constant current is flown to the MOSFET and one or more of them are connected in series in a diode form. The gate-source voltage of one to a plurality of series MOSFETs is used as the output reference voltage.

[0005]

According to the above means, one or a plurality of MOs are provided.
Since the gate-source voltage of each SFET becomes equal to the constant voltage supplied between the gate and source of the MOSFET that forms the above-mentioned constant current, it is possible to obtain an output reference voltage that is the same or an integral multiple thereof.

[0006]

1 is a circuit diagram of an embodiment of a reference voltage generating circuit according to the present invention. Each circuit element in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. In the figure, the MOSFET with an arrow added to the channel portion (back gate) is a P-channel MOSF.
ET (hereinafter the same). Further, in the present invention, the MOS
FET is used to mean IGFET (insulated gate field effect transistor).

A reference current is formed in the P-channel MOSFET M1 by applying a circuit ground voltage to its gate. This reference current is supplied to the N-channel MOSFET M2 in the form of a diode. This M
OSFET M2 has two Ns in current mirror form.
Channel MOSFETs M3 and M8 are provided. MO
SFET M3 has P-channel MOSFETs M4 and M5
Is provided. MOSFETM
In order to form the pushing current i which is half the current value of the sink current flowing in 8 to 2i, the above M
The size ratio of OSFET M3 and M8 is 1: 2, and MO
Either make the size ratio of SFET M4 and M5 equal, or make the size ratio of MOSFET M3 and M8 equal and
The size ratio of the OSFETs M4 and M5 is set to 2: 1. In this way, the push-out current i having a half current value is formed from the MOSFET M5.

The current i formed by the MOSFET M5 is a diode-connected P-channel MOSFET.
MO so as to flow to the MOSFET M8 via M6
The SFETs M5, M6 and M8 are connected in series. M above
At the connection point between the OSFETs M6 and M8, the MOSFET
A diode-type P-channel MOSFET M7 having a threshold voltage higher than that of M6 is connected. This P
The channel MOSFET M7 has an impurity concentration increased on the surface of the channel region by introducing N-type which is the same conductivity type as the channel region into the surface of the channel region by an ion implantation technique. This makes MO
The threshold voltage of SFET M7 is set higher than that of MOSFET M6. In this case, P channel MOSFE
The TM7 increases the impurity concentration on the channel surface by the ion implantation technique based on a P-channel MOSFET formed similarly to the P-channel MOSFET M6. Therefore, the difference in the threshold voltage is caused by the process variation. It is possible to cancel out each other and make it relatively stable corresponding to the ion implantation amount. Although not particularly limited, the threshold voltage of MOSFET M6 is about 0.3.
Formed as small as ~ 0.4V, MOSFET M7
The threshold voltage is set to a large voltage of about 1.4V.

By providing the MOSFET M7 at the connection point between the MOSFETs M6 and M8 as described above, the MOSF
The ETM7 has a MOS from the current flowing in the MOSFET M8.
The difference current i obtained by subtracting the current flowing through the FET M6 is made to flow. As described above, the current i is allowed to flow through the MOSFET M6 and the current 2i is allowed to flow through the MOSFET M8.
A current i similar to 6 is made to flow. in this way,
By making the same current i flow in the MOSFETs M6 and M7, the diode-formed MOSFET M is formed.
The potential of the node N4 on the drain side of 6 is
It may be a constant voltage corresponding to the difference voltage (Vth7-Vth6) between the threshold voltage Vth6 of the SFET M6 and the threshold voltage Vth7 of M7. When the source of the MOSFET M7 is connected to the power supply voltage VCC, the voltage of the node N4 becomes VCC- (Vth7-Vth6).

The source of this constant voltage is the above-mentioned power supply voltage VC.
It is supplied to the gate of a P-channel MOSFET M9 connected to C. As a result, the constant current ir is made to flow from the source of the MOSFET M9. This constant current i
r is the same structure as the MOSFET M9 and is a diode-connected series MOSFET M10 to M12.
It is made to flow to. That is, MOSFETM10
The M12 is a P-channel MOSFET of the same conductivity type as the MOSFET M9, and is formed to have the same size. Thus, MOSFETs M10 to M12 having the same structure
In accordance with the constant current ir that is the same as that of the MOSFET M9, the source-gate voltage is the source-gate voltage of the MOSFET M9, in other words, the constant voltage (Vth7-Vth6). Will be equal. Then, by connecting the drain side of the MOSFET M12 to the ground potential point of the circuit,
A reference voltage VREF of 3 (Vth7-Vth6) can be formed from the source side of M10. A capacitor C is provided between the output terminal and the ground potential point of the circuit for removing power supply ripples and the like. As described above, the threshold voltage of the MOSFET M6 is about 0.3 to
If it is formed as small as 0.4V and the threshold voltage of the MOSFET M7 is set as large as about 1.4V, the reference voltage VREF such as about 3V can be obtained. The reference voltage VREF becomes a stable constant voltage that is not affected by the fluctuation of the power supply voltage VCC. If the power supply voltage VCC drops below the reference voltage VREF, the MO
The SFETs M10 to M12 are turned off due to insufficient operating voltage. On the other hand, since the MOSFET M9 operates to form the constant current ir by the constant voltage of the node N4, it becomes substantially saturated and the reference voltage VREF becomes the power supply voltage VC.
The voltage changes following C.

FIG. 2 shows a circuit diagram of an embodiment of the internal voltage down converting circuit using the reference voltage. Although the circuit symbols given to the circuit elements in the figure overlap with those in FIG. 1, it should be understood that each has a separate circuit symbol. The output reference voltage VREF formed by the reference voltage generating circuit does not have a current supply capability by itself. Therefore, the following voltage follower circuit is used to perform the power amplification operation, in other words, to convert it into a low impedance so as to operate as a voltage source. The ground potential of the circuit is supplied to the gate of the P-channel MOSFET M1 to generate a reference current as described above. This current is supplied to a diode-type N-channel MOSFET M2, and a node N1 of the common gate and drain of the MOSFET M2 has an N-channel MOS constituting a current source.
FETs M7, M9 and M12 are connected in a current mirror configuration.

The MOSFET M7 as a current source supplies a bias current to the next differential circuit. N-channel MOSF
The ETMs 5 and M6 are connected in a differential form, and the current source MOSFET M7 is provided at a common source thereof.
The drains of the differential MOSFETs M5 and M6 are provided with P-channel MOSFETs M3 and M4 in a current mirror form as loads. A reference voltage VREF is supplied as an input voltage to the gate of the differential MOSFET M5. The output voltage obtained from the drain of the MOSFET M6 is a P-channel MOSFET that constitutes an inverting amplifier circuit.
It is supplied to the gate of M8. A current source MOSFET M9 is provided as a load at the drain of the MOSFET M8. The output signal from the inverting amplifier circuit is P channel M
Output voltage VCL via a CMOS inverter circuit composed of OSFET M10 and N-channel MOSFET M11
Is output and is fed back to the gate of the differential MOSFET M6 to form a voltage follower circuit. In the differential amplification output circuit, the feedback loop acts so that the reference voltage VREF and the output voltage VCL are equal to each other, and the output voltage VCL corresponding to the reference voltage VREF is formed.

The N-channel MOSFET is used to form a difference voltage between a MOSFET having a high threshold voltage and a MOSFET having a normal threshold voltage with reference to the ground potential of the circuit, and the DC voltage is amplified. It is also conceivable to obtain a desired output voltage by amplifying with a circuit. However, when using such an amplifier circuit, in order to reduce the current consumption, it is necessary to set the resistance value of the feedback resistor that sets the gain to a large value such as several megohms. If formed, the parasitic capacitance may increase and oscillation may occur in the amplifier circuit. In addition, the open gain of this amplifier circuit changes according to the change of the power supply voltage VCC,
It is extremely difficult to suppress oscillation with a wide range of operating voltage VCC. On the other hand, in the reference voltage generating circuit as in the above embodiment, the required voltage is directly obtained. Therefore, since the reference voltage VREF need only be output through the voltage follower circuit as in the above-described embodiment, the above-described fear of oscillation can be eliminated.

FIG. 3 shows a circuit diagram of another embodiment of the internal voltage down converting circuit using the reference voltage. Although the circuit symbols given to the circuit elements in the figure overlap with those in FIGS. 1 and 2, it should be understood that each has a different circuit symbol. In the embodiment circuit of FIG. 2, there is a problem that the current supply capability becomes insufficient when the power supply voltage VCC drops to around the step-down voltage VCL.
As a result, the operating voltage range becomes narrow, and it becomes impossible to perform the battery backup operation with the battery voltage that is approximately the same as or lower than the step-down voltage VCL. Therefore, in this embodiment, the following circuit is added in order to provide a sufficient current supply capability even when the power supply voltage VCC drops to around the step-down voltage VCL or lower.

In the figure, MOSFETs M1 to M12
Is a P-channel MOSFET similar to the circuit of FIG.
The ground potential of the circuit is supplied to the gate of the M1 to generate a reference current as in the above. This current is supplied to an N-channel MOSFET M2 in the form of a diode, and N-channel MOSFETs M7, M9 and M12 forming a current source are connected in a current mirror form to a common gate and drain node N1 of the MOSFET M2. MOSFET M7 as current source
Applies a bias current to the common sources of the differential N-channel MOSFETs M5 and M6. The drains of the differential MOSFETs M5 and M6 are provided with P-channel MOSFETs M3 and M4 in a current mirror form as loads. A reference voltage VREF is supplied as an input voltage to the gate of the differential MOSFET M5.
The output voltage obtained from the drain of MOSFET M6 is
P-channel MOSFET M1 forming an inverting amplifier circuit
4 gates. A current source MOSFET M9 is provided as a load at the drain of the MOSFET M14 via the differential MOSFET M16.
The output signal from the inverting amplifier circuit is P channel MOSFE.
C consisting of TM10 and N-channel MOSFET M11
The voltage follower circuit is configured by being output as the output voltage VCL via the MOS inverter circuit and being fed back to the gate of the differential MOSFET M6 on the other side. The CMOS inverter circuit has the above current source MOSFE.
A bias current is made to flow by TM12. In this embodiment, the newly provided differential MOSFET is
A dummy P-channel MOSFET M13 is provided in the differential MOSFET M15 paired with M16. The output voltage VCL is supplied to the gate of the differential MOSFET M15, and the reference voltage VREF is supplied to the gate of the differential MOSFET M16.

When the power supply voltage VCC is sufficiently higher than the output voltage VCL, the common source node N3 and the drain node N of the differential MOSFETs M5 and M6 are used.
There is a predetermined potential difference between 2 and N4. This also applies to the potential relationship between the sources and drains of the similar differential MOSFETs M15 and M16. Therefore,
The internal step-down circuit in FIG. 3 operates like the equivalent circuit shown in FIG. Strictly speaking, the differential MOSFETs M15 and M
Since the bias current generated by the current source MOSFET M9 is shunted by half by 16, the amplification MOSF
A half of the bias current formed by the current source MOSFET M9 flows through the ETM14. Figure 4
2 is substantially the same as the circuit of FIG. 2 and has the same impedance conversion operation as the reference voltage VREF.
In accordance with the above, the step-down operation of stepping down the power supply voltage VCC is performed.

When the power supply voltage VCC is equal to or lower than the output voltage VCL, the differential MOSFETs M5 and M6 operate in the saturation region as the power supply voltage VCC is lowered, and the common source side node N3 is connected. , The potentials of the drain side nodes N2 and N4 are made approximately equal. This means that similar differential MOSFETs M15 and M1
The same applies to the potential relationship between the source and drain of No. 6. Therefore, the internal step-down circuit in FIG. 3 operates like the equivalent circuit shown in FIG. That is, differential MO
The source and the drain of the SFETs M5 and M6 are short-circuited, and the bias current of the current source MOSFET M7 is in a parallel form.
It will flow to SFET M34. Similarly, differential MOS
The sources and drains of the FETs M15 and 1M6 are short-circuited, and the bias current of the current source MOSFET M9 flows to the MOSFET M134 composed of the MOSFETs M13 and M14 arranged in parallel. Where M
If the OSFETs M7 and M9 are formed to have the same size so that the same bias current flows and the conductance of the equivalent MOSFET M34 is set to a sufficiently large ratio with respect to the conductance of the equivalent MOSFET M134, the node N4
Is set to the high level and the node N5 is set to the low level. As a result, the P-channel output MOSFET M10 has the maximum conductance in response to the node N5 being brought to a low level such as the ground potential of the circuit,
The output voltage VCL having a large current supply capability is formed according to the power supply voltage VCC. The N-channel MOSFET M11 is practically turned off according to the low level of the node N5, and the output MOSFET M10 operates as an open drain type output MOSFET.

FIG. 6 shows an operation characteristic diagram for explaining the operation of the internal voltage down converting circuit shown in FIG. The power supply voltage VCC is the output voltage VCL as shown by the broken line in the figure.
When the level is sufficiently higher than the reference voltage VREF or the reference voltage VREF, the output voltage VCL becomes a constant voltage regardless of the level. On the other hand, when the power supply voltage VCC coincides with the output voltage VCL and drops below the output voltage VCL, the potential of the node N5 drops sharply to the low level, and the P-channel output MOSF
The ETM 10 is turned on under the maximum conductance to supply current. As a result, the output voltage VCL decreases following the power supply voltage VCC. That is,
When the voltage drops below the step-down voltage set by the reference voltage VREF, the step-down operation is automatically stopped and the power supply voltage VCC supplied from the outside is directly transmitted to the internal circuit. As a result, in the normal operation state, the operation is performed by the power supply voltage VCC of about 5V, and when the system enters the standby mode such as when the system power is cut off, the voltage drop voltage of about 1. It can be backed up by using a battery voltage of about 5V.

7 to 9 are circuit diagrams showing an embodiment of a pseudo static RAM to which the present invention is applied. FIG. 7 shows a circuit diagram of the memory array and row system selection circuit, FIG. 8 shows a circuit diagram of the sense amplifier and column system selection circuit, and FIG. 9 shows a block diagram of the control system and the power supply system. It is shown. In the following, the circuit symbol attached to the MOSFET is Q in order to distinguish it from those in FIGS.
Is using. The structure of the integrated circuit is roughly described as follows. Of the surface portion of the semiconductor substrate made of single crystal P-type silicon and having the N-type well region formed therein,
Other than the surface portion which is the active region, in other words, the semiconductor wiring region, the capacitor forming region, the N channel and the P
A relatively thick field insulating film formed by a known selective oxidation method is formed on the source and drain of the channel MOSFET and a surface portion which is a channel forming region (gate forming region). The capacitor formation region is not particularly limited, but is formed on the capacitor formation region via an insulating film (oxide film) having a relatively thin thickness.
A second polysilicon layer is formed. The first polysilicon layer extends to above the field insulating film. 1
A thin oxide film formed by thermal oxidation of itself is formed on the surface of the second polysilicon layer. A channel is formed on the surface of the semiconductor substrate in the capacitor formation region by forming an N-type region by an ion implantation method or by supplying a predetermined voltage. As a result, a capacitor composed of the first polysilicon layer, the thin insulating film and the channel region is formed. The first polysilicon layer on the field oxide film is regarded as one kind of wiring. A second polysilicon layer for forming a gate electrode is formed on the channel formation region via a thin gate oxide film. This second polysilicon layer is
It extends over the field insulating film and the first polysilicon layer. Although not particularly limited, the word line in the memory array described later is composed of the second polysilicon layer. Source, drain and semiconductor wiring regions are formed on the surface of the active region which is not covered with the field insulating film, the first and second polysilicon layers, by a known impurity introduction technique using them as an impurity introduction mask. . A relatively thick interlayer insulating film is formed on the surface of the semiconductor substrate including the first and second polysilicon layers, and a conductor layer made of aluminum is formed on the interlayer insulating film. . The conductor layer is a polysilicon layer through a contact hole provided in the insulating film thereunder,
Electrically coupled to the semiconductor region. The complementary data lines in the memory array described later are not particularly limited,
It is composed of a conductor layer extended on the interlayer insulating film.
The surface of the semiconductor substrate including the interlayer insulating film and the conductor layer is covered with a final passivation film composed of a silicon nitride film and a phosphine silicate glass film.

Although not particularly limited, the memory array MARY illustrated in FIG. 7 is of a two-intersection (folded bit line) system. In the figure, the pair of rows is exemplarily shown as a representative. A pair of complementary data lines (bit line or digit line) D0 arranged in parallel,
Input / output nodes of a plurality of memory cells each composed of an address selection MOSFET Qm and an information storage capacitor Cs are distributed and coupled to D 0 with a predetermined regularity as shown in FIG.

In FIG. 8, the precharge circuit PC is
As in the MOSFETQ5 shown as a representative, the switch MOSFET provided between the complementary data lines D0, D 0
It is composed of The MOSFET Q5 is turned on in the chip non-selected state or before the memory cell is selected by supplying the gate with the precharge signal pc generated in the chip non-selected state.
Thus, in the previous operation cycle, the complementary data lines due to the amplification operation of the sense amplifier SA to be described later D0, D 0
Of the complementary data line D by shorting the high level and the low level of
0 and D 0 are precharge voltages of about VCL / 2 (HVC). Although not particularly limited, when the chip is left in a non-selected state for a relatively long time, the precharge level is lowered due to a leak current or the like. Therefore, in this embodiment, the switch MOSFETs Q45 and Q46 are provided to supply the half precharge voltage HVC. The voltage generating circuit for forming the half precharge voltage HVC has a relatively small current supply capability so as to compensate for the leak current and the like, although its specific circuit is not shown. This suppresses an increase in power consumption.

Before the precharge MOSFET Q5 or the like is turned on by the chip non-selection state of the RAM or the like, the sense amplifier SA is deactivated. In this case, the complementary data lines D0, D 0 has become to hold the high and low levels in a high impedance state. In addition, when the RAM is put into operation, the precharge MO before the sense amplifier SA is put into operation.
The SFETs Q5, Q45, Q46, etc. are turned off. Thus, the complementary data lines D0, D 0 is the half precharge level at a high impedance state HVC
Is to hold. Since In such a half precharge scheme is merely formed by short-circuiting high and low levels of the complementary data lines D0, D 0,
Low power consumption can be achieved. Further, in the amplifying operation of the sense amplifier SA, since the precharge level complementary data lines around the D0, D 0 is changed in the common mode, as high and low levels, can be reduced the noise level generated by the capacitive coupling Will be things.

The sense amplifier SA has its unit circuit USA.
Is shown as an example, and a P-channel MOSFET Q
7 and Q9 and N-channel MOSFETs Q6 and Q8, and a pair of input / output nodes are coupled to the complementary data lines D0 and D0. The latch circuit is not particularly limited,
Power supply voltage VCL and P-channel MOSFET Q1 through N-channel MOSFETs Q12 and Q13 in parallel form.
4, the boosted voltage VCH is supplied, and the ground voltage VSS of the circuit is supplied through parallel N-channel MOSFETs Q10 and Q11. These power switches M
OSFETs Q10 and Q11 and MOSFETs Q12 to Q
14 is commonly used for latch circuits (unit circuits) provided in other similar rows in the same memory array (or memory mat). In other words, a P-channel MOSFET in a latch circuit in the same memory array
And N-channel MOSFETs have their sources P
S and SN are commonly connected. The MOSFET Q1
A clock pulse sc1 for activating the sense amplifier SA in the operation cycle is applied to the gates of 0 and Q12, and a clock pulse sc2 formed later than the clock pulse sc1 is applied to the gates of the MOSFETs Q11 and Q13. .

As a result, the operation of the sense amplifier SA is first divided into two stages. When the clock pulse sc1 is generated, that is, in the first stage, MOSFETs Q10 and Q12 having a relatively small conductance are used.
The minute read voltage applied between the pair of data lines from the memory cell due to the current limiting action of is amplified without undergoing an undesired level fluctuation. The clock pulse sc2 is generated after the difference between the complementary data line potentials is increased to some extent by the amplification operation in the sense amplifier SA, in other words, MOSFETs Q11 and Q13 having relatively large conductances in the second stage.
Is turned on. The amplification operation of the sense amplifier SA is
It is accelerated by turning on the MOSFETs Q11 and Q13. And, although not particularly limited,
In the step, the clock pulse sc3 is generated to switch the operating voltage on the high level side of the sense amplifier to the boost voltage VCH. As a result, the potential of the data line to be set to the high level can reach the high level such as VCL within a short time. By thus performing the amplifying operation of the sense amplifier SA in three stages, it is possible to prevent an undesired level change in the complementary data line and finish high-speed reading of data and its rewriting at an early timing. it can.

In this embodiment, as shown in FIG. 8, a power switch MOSF for supplying a high level to the sense amplifier.
When an N-channel MOSFET is used as ET, its element size can be reduced to about 1/3 of that when a P-channel MOSFET is used. However, when the N-channel MOSFET is used, the voltage VCL-V
Voltage can be supplied only up to th. Here, Vth is the threshold voltage of the N-channel MOSFET. However, using the P-channel MOSFET, the boosted voltage VC
In the case of adopting the configuration of supplying H, it is not necessary to set the amplification high level of the sense amplifier in the first and second stages to VCL, so that there is practically no problem. This allows
The occupied area of the power switch MOSFET can be reduced.

In FIG. 7, the X (row) address decoder is not particularly limited, but the first address decoder circuit including the gate circuits G1 to G4 and the unit circuit UXDC.
It is configured by being divided into two so as to include a second address decoder circuit such as R. In the figure, one circuit (unit circuit) UXDCR forming the second address decoder circuit is shown.
And a NOR (NO) forming the first address decoder circuit.
R) Gate circuits G1-G4 are shown. The circuit symbols of the gate circuits G2 and G3 are omitted. The unit circuit UXDCR forms a decode signal for four word lines. The four gate circuits G1 to G4 forming the first X decoder circuit have four different word line selection timing signals φx0 to φx3 depending on the combination of the word line selection signals x0 and x1 corresponding to the address signal of the lower 2 bits.
To form. These word line selection timing signals φx0
~ Φx3 is the transmission gate above MOSFETQ20 ~ Q23
Is input to the unit word line drivers UWD0 to UWD3.

The word line driver WD is a unit circuit UWD.
0 is representatively shown as a typical example, and P-channel MOSFET Q26 and N-channel MOSFET Q
CMOS drive circuit composed of 27 and P-channel MOSFE provided between its input and operating voltage terminal VCH
It is composed of TQ24 and Q25. P channel MOS
The gate of the FET Q24 is supplied with the precharge signal wph level-converted by the level conversion circuit as described above. The drive output of the word line W0 is supplied to the gate of the P-channel MOSFET Q25. That is, MO
When the word line selection timing signal φx0 formed according to the internal step-down voltage VCL is set to a high level and the word line W0 is set to a non-selection level such as the ground potential, the SFET Q25 receives the low level and receives the input level of the CMOS circuit. Is pulled up to the high voltage VCH to surely turn off the P-channel MOSFET Q26. This prevents the direct current from being consumed between the P-channel MOSFETs Q26 and Q27 forming the CMOS drive circuit corresponding to the non-selected word line. A unit circuit UXD that constitutes a second X address decoder circuit by dividing the X address decoder into two as described above.
The pitch (spacing) of CR and the pitch of word lines can be matched. As a result, useless space can be prevented from being generated on the semiconductor substrate.

Switch MOSFETs Q1 to Q4 and the like are provided between the far end side of the word line and the ground potential of the circuit.
Signals WC0 to WC3 having a phase opposite to the selection signal supplied to the corresponding word lines W0 to W3 are supplied to the gates of these switch MOSFETs Q1 to Q4. Thereby, the switch MO corresponding to the selected word line
Only SFET turned off, other switch MOSFET
Is turned on. As a result, it is possible to prevent the unselected word line from being undesirably raised to the intermediate potential due to capacitive coupling due to the rising of the selected word line.

In FIG. 8, the row (X) address buffer R-ADB is in an operating state by a clock pulse (not shown) formed by a control circuit CONT described later based on the chip enable signal CE supplied from the external terminal. In this operating state, the address signals A0-Am supplied from the external terminals are taken in and held, and the internal complementary address signals a0-am whose levels are converted corresponding to the step-down voltage VCL as described above are stored. It is formed and transmitted to the first and second row address decoders. The internal complementary address signals a0-am are composed of a pair of in-phase signal and anti-phase signal with respect to the address signals A0-Am supplied from the external terminals. The column (Y) address buffer C-ADB receives the chip enable signal CE.
Is operated by a clock pulse (not shown) formed on the basis of the address signal A0-An supplied from an external terminal in the operating state, and it is held at the step-down voltage VCL as described above. Corresponding level-converted internal complementary address signals a0-an are formed and transmitted to the column address decoder C-DCR.
The internal complementary address signals a0 to an are composed of a pair of an in-phase signal and an anti-phase signal with respect to the address signals A0 to An supplied from the external terminals as described above.

The column decoder C-DCR is basically composed of an address decoder circuit similar to the above X address decoder, is activated by a clock pulse C2 ', and is supplied with a complementary address signal supplied from the column address buffer C-ADB. It decodes a0 to an to form a selection signal to be supplied to the column switch C-SW. The column switch C-SW, like the representatively shown N-channel MOSFETs Q42 and Q43, has a complementary data line D.
0, D 0 and the common complementary data lines CD, CD are selectively coupled. A selection signal from the column decoder C-DCR is supplied to the gates of these MOSFETs Q42 and Q43. Between the common complementary data lines CD, CD ,
An N-channel type precharge MOSFET Q44 forming a precharge circuit similar to the above is provided.
A pair of input / output nodes of a main amplifier MA having a circuit configuration similar to that of the sense amplifier USA described above is coupled to the common complementary data lines CD, CD .

A pair of output nodes MO of the main amplifier MA,
The MO read signal is sent to the outside from the external terminal Dout via the data output buffer DOB. In the read operation mode, the data output buffer DOB is activated by the activation signal doc, amplifies the amplified output signal of the main amplifier MA which is activated at this time, and sets the level to a level corresponding to the external power supply voltage VCC. It is converted and sent to the external terminal Dout. In the write operation mode, the data output buffer DO is generated by the signal doc.
The output terminal Dout of B is in a high impedance state.

The output terminals of the data input buffer DIB are coupled to the common complementary data lines CD, CD . In the write operation mode, the data input buffer DIB is activated by its activation pulse dic and level-converts the complementary write signal according to the write signal supplied from the external terminal Din to a level corresponding to the internal step-down voltage VCL. Then, by transmitting to the common complementary data lines CD, CD , writing to the selected memory cell is performed. In the read operation mode, the output of the data input buffer DIB is brought to a high impedance state by the signal dic.

In FIG. 9, the various timing signals described above are formed by the control circuit CONT. Control circuit C
The ONT forms various timing signals necessary for the operation of the RAM, such as the main timing signals shown as the representative above. That is, the control circuit CONT receives the chip enable signal CE and the write enable signal WE supplied from the external terminal and forms the above-mentioned series of various timing pulses. Although not particularly limited, when the chip enable signal CE is fixed to the low level and the memory access is continuously performed by the change of the address signal,
An address signal change detection circuit is provided. That is, the internal address signal formed by the address buffers R-ADB and C-ADB is input to the address signal conversion detection circuit configured by using the exclusive OR circuit, and any one bit address signal is changed. In that case, the detection pulse is used instead of the chip enable signal to form the internal precharge (reset) and the clock pulse necessary for the operation of the RAM as described above.

The circuit symbol REFC is an automatic refresh circuit, which includes a refresh address counter and the like. This automatic refresh circuit REF
C is not particularly limited, but the refresh control signal RF
A logic circuit that receives SH and the chip enable signal CE distinguishes between auto-refresh and self-refresh and performs auto-refresh using CE as a clock and self-refresh by an internal timer circuit.

The internal step-down circuit VCLG is constituted by the circuit shown in FIGS. 1 to 3, receives the power supply voltage VCC supplied from the external terminal, and receives a stabilized internal step-down voltage VCL of about 3V. Generate. In this case, the power supply voltage VCC supplied from the external terminal is about 3 above.
When the voltage drops below V, the internal step-down circuit VCLG automatically stops the step-down operation as described above and outputs the power supply voltage VCC as it is as the output voltage VCL. As a result, a battery voltage as low as about 1.5 V is supplied to the internal circuit as it is without being further reduced by the internal voltage down converter, so that the battery backup operation can be efficiently performed. The internal booster circuit VCHG receives a pulse signal formed based on the stabilized internal step-down voltage VCL and forms a boosted voltage required for the word line selection operation and the sense amplifier. The substrate voltage generating circuit VBG is not particularly limited, but the stabilized internal step-down voltage VCL is used.
A negative bias voltage -Vbb applied to the substrate is generated by receiving a pulse signal formed based on the above.

The functions and effects obtained from the above-mentioned embodiment are as follows. (1) A MOSFET having the same structure as the first MOSFET that receives a constant voltage between a gate and a source to form a constant current is used. However, the gate-source voltage of these one or more series MOSFETs is used as the output reference voltage. In this configuration, the gate-source voltage of each of the one or more MOSFETs is the gate of the MOSFET forming the constant current,
Since it is equal to the constant voltage supplied between the sources, it is possible to obtain an output reference voltage that is equal to or an integral multiple of the constant voltage. (2) As a circuit for forming a constant voltage, by adopting a structure in which impurities are introduced into the channel region surface of one of the pair of MOSFETs having the same structure by the ion implantation technique and the difference voltage is used,
It is not affected by the process variation of forming the OSFET,
The effect that a relatively high-precision constant voltage controlled by the amount of ion implantation can be obtained is obtained. (3) By supplying the reference voltage to an internal voltage down converter in the form of voltage follower to obtain the down voltage, the amplifier circuit forming the voltage follower circuit operates without oscillating against a wide range of power supply voltages. The effect that can be obtained is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
In FIG. 1, the conductivity type of the gate electrodes of MOSFETs M6 and M7 may be changed to give a difference in threshold voltage to generate a constant voltage in accordance with the silicon band gap. The circuit for generating the constant voltage supplied to the gate of the MOSFET M9 that forms the constant current ir can adopt various embodiments. The number of MOSFETs that generate the reference voltage VREF may be 1 to a plurality depending on the required output voltage VREF. In the RAMs of FIGS. 7 to 9, the address buffers and address decoders are MOSFs such as CMOSs.
Besides ET, a Bi-CMOS circuit in which a CMOS circuit is combined with a bipolar transistor may be used. The RAM may be a dynamic RAM that inputs X-system and Y-system address signals in time series in synchronization with the address strobe signal. The present invention provides various types of semiconductor integrated circuit devices including a dynamic RAM having an internal voltage down converter, a pseudo static RAM, and a circuit that requires a constant reference voltage such as an analog / digital conversion circuit or a digital / analog conversion circuit. It is widely available.

[0038]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a MOSFET having the same structure as the first MOSFET that receives a constant voltage between the gate and the source to form a constant current is used, and the above constant current is flown to the MOSFET and one or more of them are connected in series in a diode form. The gate-source voltage of one to a plurality of series MOSFETs is used as the output reference voltage. In this configuration, the gate-source voltage of each of the one to a plurality of MOSFETs forms the constant current M.
Since it becomes equal to the constant voltage supplied between the gate and the source of the OSFET, it is possible to obtain an output reference voltage that is equal to or a multiple of the constant voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a reference voltage generating circuit according to the present invention.

FIG. 2 is a circuit diagram showing an embodiment of an internal step-down circuit according to the present invention.

FIG. 3 is a circuit diagram showing another embodiment of the internal voltage down converter according to the present invention.

FIG. 4 is an equivalent circuit diagram for explaining an example of the operation of the internal step-down circuit shown in FIG.

5 is an equivalent circuit diagram for explaining another example of the operation of the internal step-down circuit shown in FIG.

FIG. 6 is an operating characteristic diagram for explaining the operation of the internal voltage down converting circuit shown in FIG.

FIG. 7 is a pseudo static RA to which the present invention is applied.
FIG. 7 is a circuit diagram of a memory array and a row selection circuit according to an embodiment of M.

FIG. 8 is a pseudo static RA to which the present invention is applied.
7 is a circuit diagram of a sense amplifier and column system selection circuit showing an embodiment of M. FIG.

FIG. 9 is a pseudo static RA to which the present invention is applied.
3 is a block diagram of a control system and a power supply system showing an embodiment of M. FIG.

[Explanation of symbols]

M1 to M16, Q1 to Q46 ... MOSFET, MARY
... memory array, WD ... word line driver, PC ... precharge circuit, USA ... sense amplifier unit circuit, SA ...
Sense amplifier, MA ... Main amplifier, C-SW ... Column switch, ADB ... Address buffer, R-DCR ... X
System address decoder, C-DCR ... Y system address decoder, CONT ... Control circuit, REFC ... Automatic refresh circuit, DOB ... Data output buffer, DIB ... Data input buffer, VBG ... Substrate bias generation circuit, G1-G
4 ... Gate circuit, UWD0 to UWD3 ... Word line driver unit circuit, VCLG ... Internal step-down circuit, VCHG ... Internal step-up circuit.

Claims (4)

[Claims] 1. A first MOSFET for receiving a constant voltage between a gate and a source to form a constant current, and the first MOS.
A MOSFET having the same structure as the FET, including one or a plurality of diode-type series MOSFETs configured to flow the constant current, and the one or a plurality of series MOSs.
A semiconductor integrated circuit device comprising a reference voltage generating circuit using a gate-source voltage of an FET as an output reference voltage. 2. The constant voltage supplied to the gate and the source of the first MOSFET is the same conductivity type MOSFET as the first MOSFET, and the same current is applied to two MOSFETs having different threshold voltages. 2. The semiconductor integrated circuit device according to claim 1, wherein a differential voltage of the threshold voltage formed by flowing the liquid crystal is used. 3. The output reference voltage is used as a reference voltage of an internal step-down circuit which receives a power supply voltage supplied from an external terminal and forms an operating voltage necessary for operating an internal circuit. 3. The semiconductor integrated circuit device according to claim 1 or 2. 4. The semiconductor integrated circuit device according to claim 3, wherein the internal step-down voltage is used for a RAM having a battery backup function while using a dynamic memory cell.