JP3157697B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a static RAM semiconductor memory device having means for boosting the potential of a word line to a power supply voltage or higher.

[0002]

2. Description of the Related Art A conventional example of this type of semiconductor memory device will be described with reference to FIG. FIG. 4 is a diagram showing an example of a conventional static RAM semiconductor memory device.

As shown in FIG. 4, a memory cell of a conventional static RAM includes: a first n-channel M connecting a source to a ground potential point;
OSFET (Q ₁ ), source connected to ground potential point, gate connected to drain of n-channel MOSFET (Q ₁ ), drain connected to n
The second connected to the gate of the channel MOSFET (Q ₁ )
An n-channel MOSFET (Q ₂ ) having one end connected to the drain of the n-channel MOSFET (Q ₁ ) and the other end connected to a power supply source of a power supply potential (Vcc); _1), the - end connected to the drain of the n-channel MOSFET (Q _2), a second load resistor of high resistance connected to the power source of the power supply potential and the other end (Vcc) (R _2), and - The drains of the first and second n-channel MOSFETs (Q ₁ , Q ₂ ) are used as first and second data input / output terminals (N ₁ , N ₂ ) to capture and store data, and Remembered data
And a flip-flop circuit for outputting data.

Then, the first and second memory cells
Data input / output terminals (N ₁ , N ₂ ) are respectively connected via switching n-channel MOSFETs (Q ₃ , Q ₄ ).
Connected to digit line pair (DG ₁ , DG ₂ ). Further, n-channel MOSFET (Q _3, Q ₄₎ for Suitchingu the gate -
The word line (W ₁ ) is supplied with an output signal of a "word line selection circuit" for decoding a column address input signal and selecting a predetermined word line.

Further, between the digit line pair (DG ₁ , DG ₂ ) and the power supply potential (Vcc), a gate whose gate is connected to the ground potential is provided.
A “digit line load circuit 1” composed of channel MOSFETs (Q ₅ , Q ₆ ) is connected. On the other hand, the digit line pairs (DG _1, DG ₂₎ the de - between the buses line (DB _1, DB _2),
n-channel MOSFET (Q ₇ , Q ₈ ) and p-channel M
"C" in which the OSFETs (Q ₉ , Q ₁₀ ) are connected in parallel with each other
A MOS data transfer circuit 2 "is provided.

The gate of the n-channel MOSFET (Q ₇ , Q ₈ ) of the “CMOS data transfer circuit 2” has a digit line which decodes a row address input signal and selects a predetermined digit line pair. The output signal (Y) of the selection circuit is applied, and the gate of the p-channel MOSFET (Q ₉ , Q ₁₀ ) receives the output signal (−) of the “inverter circuit 3” which receives the output signal (Y).
Y) (-Y indicates that Y is overlined as shown in FIG. 4; the same applies hereinafter).

A plurality of digit line pairs and word lines exist in a row direction and a column direction, respectively, and constitute a memory cell array. The data bus lines (DB ₁ , DB ₂ ) have a “write circuit” for controlling write data to the memory cell and a “read circuit” for controlling the read of data read from the memory cell. Circuit "is connected.

The operation of the conventional semiconductor memory device having the above configuration will be described below with reference to FIG. First, during a read operation, when a column address input signal is decoded and a predetermined word line (W ₁ ) is selected, the switching n-channel MOSFETs (Q ₃ , Q ₄ ) are turned on, and the memory cell is turned on. Depending on the stored contents, one (eg, “DG ₂ ”) of the digit lines (DG ₁ , DG ₂ ) goes low and the other (eg, “DG ₁ ”) goes high.

A digit line pair selection signal (Y and -Y) output by decoding the row address input signal is supplied to a predetermined "CMO".
Activate the S data transfer circuit 2 ″ and set the digit lines (DG ₁ ,
De of DG ₂₎ - it is transmitted to the data bus (DB _1, DB ₂₎ - the data de. The "readout circuit" is de - buses (DB _1, DB ₂₎ de from - to amplify the data, to transmit the stored information of the memory cell to the output circuit.

On the other hand, during a write operation, a column address input signal is decoded, a predetermined word line (W ₁ ) is selected, and a digit line pair selection signal (Y,-) output after decoding a row address input signal. A predetermined "CMOS data transfer circuit 2" is activated by Y). The write circuit is de - de from data input circuit - receiving the data, de - buses (DB _1, DB ₂₎ while forcibly set to the ground potential of one of the digit lines (DG _1, DG ₂₎ Is a ground potential, and a switching n-channel MOSF connected to a selected word line (W ₁ ).
The data is stored in the memory cell via ET (Q ₃ , Q ₄ ).

Next, the potentials of the _first and _{second data} input / output terminals (N ₁ , N ₂ ) at the time of writing to a memory cell will be described. De to the memory cell as described above - when writing data, predetermined digit lines (DG ₁₎ to the power supply potential (Vcc), also applies a ground potential to the digit line (DG _2), and a predetermined word - Line is in the selected state. At this time, the word line is connected to the power supply potential.
(Vcc), the first data
The high-level potential of the data input / output terminal (N ₁ ) becomes “power supply potential (Vcc) −Vth” immediately after writing. (Note that "Vt
h ″ is the threshold voltage of the switching n-channel MOSFET.)

Here, if the power supply potential (Vcc) is set to "5.0 V" in consideration of normal operation, Vth is "about 1.5 V" depending on manufacturing conditions. Data input / output terminal
The high-level potential of (N ₁ ) is “about 3.5 V”. Also,
The resistance elements (R ₁ , R ₂ ) having a high resistance have extremely high resistance values in order to realize low current consumption of the memory cell. Resistance element
(R ₁ , R ₂ ) has such a high resistance value as to prevent information charges accumulated at the data input / output terminal (N ₁ or N ₂ ) from being discharged.

Therefore, the data of the memory cell immediately after the writing is performed.
High level potential "about 3.5 V" of data input and output ends, the charge by the charge supply from the resistive element of high resistance to the power supply potential (Vcc), for example resistive element is about 10 ¹² Omega, de - data input When the capacity of the data storage node at the output end is about 10 ^-15 F, the time constant is about several ms, and it takes more than several ms. This time is the same as the normal static type R
The operation cycle of the read and write operations of the AM semiconductor memory device is longer than “up to several hundred ns”.

As described above, the high level of the data input / output terminal of the memory cell immediately after the writing is equal to the power supply voltage (Vc
c) lower. Therefore, when a low power supply voltage operation is performed, for example, when "Vcc = 2.0 V", only "about 0.5 V" is supplied to the data input / output node of the memory cell at the time of writing. Does not exceed the threshold voltage "about 0.7 V" of the inverter n-channel MOSFET paired with the gate-input flip-flop circuit, so that stable data writing and reading in the flip-flop circuit can be performed. It becomes difficult. That is, this becomes the operation limit of the semiconductor memory device of the static RAM at a low power supply voltage.

In recent years, demands from users have forced semiconductor manufacturers to commercialize low-voltage operation. Therefore, in a conventional static RAM semiconductor memory device, in order to realize an operation at a low power supply voltage, the potential of a selected word line is raised to a power supply voltage or higher, and the data input / output terminal of the memory cell is increased. Is raised to the power supply potential to expand the operating margin of the memory cell.

A conventional technique for increasing the potential of the word line to a level equal to or higher than the power supply voltage will be described with reference to FIGS. FIG. 5 is a diagram showing an example of a conventional static RAM semiconductor memory device having means for boosting a word line to a power supply voltage or higher, and FIG. 6 is a diagram showing a conventional word line blade.
FIG. 7 is a circuit diagram showing a conventional word line driving circuit.

FIG. 5 shows a configuration in which a "word line boost circuit" is provided in the conventional static RAM semiconductor memory device shown in FIG. As shown in FIG. 5, in the prior art, in order to raise the potential of the word line to the power supply voltage or higher, the "boosted voltage raised to the power supply voltage or higher" generated from the "word line boost circuit" is used. (Vbst) "is - supplied to the" word word line drive circuit ", its output is boosted memory cell word than the supply voltage - is supplied to the word line (W _1, W _2). (In addition, each code | symbol in FIG. 5 is the same as that of the above-mentioned FIG. 4, and since it overlaps, the description is abbreviate | omitted.)

As shown in FIG. 6, the "word line boost circuit" includes: an inverter 4 for inputting a signal (φbst); and a gate (input) of a signal (φbst). N-channel MOSFET (Q ₁₁ ) whose source is connected to the ground potential; p-channel M to which the signal (φbst) is gated
OSFET (Q _12), · source - scan is connected to the power supply potential (Vcc), gate - DOO is p-channel MOSFET (Q ₁₂₎ and the n-channel MOSFE
P-channel MO connected to the drain of T (Q ₁₁ )
One end is connected to the output of the inverter 4 and the other end is connected to the SFET (Q ₁₃ ).
Channel MOSFET (Q ₁₂₎ of the source - scan and p-channel MOSFET (Q ₁₃₎ drains into the connected component of -
And a strap capacity (C ₁ ). The capacitance (C ₂ ) is the boost voltage (V
bst).

The "word line driving circuit" is shown in FIG.
As shown in (1), a combination of internal complementary column address signals formed by an address buffer receiving a plurality of external column address input signals is input to the input terminal of the NAND gate 5.

On the other hand, the output of the NAND gate 5 is an n-channel MOSFET whose gate is connected to the power supply potential (Vcc).
(Q ₁₄₎ of the Soviet Union - are connected to the scan. The drain of the n-channel MOSFET (Q ₁₄ ) is connected to the power supply voltage (V
cc) or more as a power supply potential source, the output of which is connected to a word line (WL) of a memory cell, a p-channel MOSFET (Q ₁₅ ) and an n-channel MOSFET ( Q ₁₆ ) and the source receives the boosted voltage (Vbs).
t) and the gate is connected to the drain of a p-channel MOSFET (Q ₁₇ ) connected to the word line (WL).

Next, the operation of FIGS. 6 and 7 will be described. The signal (φbst) is at the power supply potential, the p-channel MOSFET (Q ₁₂ ) is off,
OSFET (Q ₁₁ ) and p-channel MOSFET (Q ₁₃ )
Since is turned on, the boosted voltage (Vbst) is precharged to the power supply voltage (Vcc) (see FIG. 6).

When the signal (φbst) changes from the power supply potential to the ground potential, the p-channel MOSFET (Q ₁₂ ) turns on, the n-channel MOSFET (Q ₁₁ ) and the p-channel MOSFET (Q ₁₃ ) turn off, At the same time
The bootstrap capacitance (C ₁ ) connected to the output of the inverter 4 is charged by changing the output of the inverter 4 from the ground potential to the power supply potential, so that the bootstrap effect starts. The potential of the boosted voltage (Vbst) further increases from the power supply voltage level (Vcc) (see FIG. 6).

When the word line is now in the selected state, that is, all the internal complementary column address signals input to the NAND gate 5 are at the high level, and the output of the NAND gate 5 is at the low level. the word line (WL) - voltage composed p-channel MOSFET (Q ₁₅₎ and the n-channel MOSFET of the (Vbst) is a power supply potential supply source (Q ₁₆₎ CMOS inverter - output of data 6, i.e., the memory cell word The level is raised to a voltage equal to the boost voltage (Vbst) (FIG. 7).
reference).

[0024]

In the above-mentioned conventional static RAM type semiconductor memory device, the data storage node (N ₁ ) of the memory cell and the ground potential are caused by, for example, a defect or variation in a process at the time of manufacturing. An abnormal leak occurs between the points. In this case, even if an attempt is made to store a high level in the data storage node (N ₁ ), the high level data will be lost via this leak. Therefore, a data holding test is performed to remove the data holding defect.

The data retention time "t" at the time of this test is as follows: for example, the data storage node capacitance (C) between the data storage node (N ₁ ) of the memory cell and the ground potential point. "C [F]".-The leak resistance is "R [Ω]."-The high level voltage when stored in the memory cell is "Vn."
[V] ". If the potential of the high-level data storage node falling to the ground potential is" V [V] ", it is expressed by the following equation (1).

[0026]

(Equation 1)

For example, when the potential of the high-level data storage node (N ₁ ), which is lowered by the leak, is “V ₁ ”, the data of the memory cell is lost, and the data holding failure occurs. when the sum - when the potential of the word line is equal to the power supply voltage "Vcc" is data of high level, as described above - data storage node (N ₁₎ for is "Vcc-Vth", removing defective The data holding time (t ₁ ) required to perform this operation is expressed by the following equation (2).

[0028]

(Equation 2)

When low power supply voltage operation is realized,
As described above, since the potential of the word line is boosted to the power supply voltage (Vcc) or more, the high-level data storage node becomes "Vcc", and as a result, the data necessary for removing the defect is removed. The data holding time (t ₂ ) is represented by the following equation (3).

[0030]

(Equation 3)

For example, "Vcc = 4.5 [V]", "Vth = 1.5
When [t ₂ / t ₁ ] is calculated with [V] ”and“ V ₁ = 0.7 [V] ”, it is expressed by the following equation (4).

[0032]

(Equation 4)

In particular, when the voltage is low, "Vcc = 2.7
[V] ", as" Vth = 1.5 [V] "," V ₁ = 0.7 [V] ",
When “t ₂ / t ₁ ” is calculated, it is expressed by the following equation (5).

[0034]

(Equation 5)

Therefore, when testing a static type semiconductor memory device which realizes a low power supply voltage operation by boosting the word line of the memory cell to a power supply voltage or higher, the holding time of the data holding test is as follows. Since the potential of the word line of the cell is increased by 1.28 times compared with the case where the power supply voltage is equal to that of the power supply voltage and further increased by 2.50 times at a lower voltage, the static RAM is increased.
It has been found that a problem arises in that the test efficiency of the semiconductor memory device is reduced.

Japanese Patent Laid- Open Publication No. 3-156792 discloses a semiconductor memory device of a dynamic RAM comprising one transistor and one capacitor. A method of boosting the voltage equal to or higher than the power supply voltage when operating in the normal mode. "

In the above-mentioned semiconductor memory device of a dynamic RAM, after a row address is fetched, a trigger signal of a word line generating circuit is generated, and the trigger signal and the booster circuit are used to generate the original word line signal. The signal is boosted, and in the test mode, the boosting of the original word line signal is suppressed by the test signal (see the above-mentioned publication). Therefore, this dynamic RAM semiconductor memory device has a drawback that it cannot be applied to a static RAM semiconductor memory device that operates asynchronously.

The present invention has been made in view of the above problems and disadvantages, and has the following objects. First, a data holding test is carried out in a test mode to thereby hold data. It is an object of the present invention to provide a semiconductor memory device capable of shortening a data holding time in a test, reducing a test cost and improving a production efficiency. Second, in particular, a potential of a word line is higher than a power supply voltage. In a static RAM semiconductor memory device provided with a step-up means, the holding time in a data holding test can be reduced,
As a result, an object of the present invention is to provide a semiconductor memory device in which the test efficiency of the semiconductor memory device does not decrease.

[0039]

According to the present invention, there is provided a semiconductor memory device comprising: a flip-flop circuit in which an inverter composed of a high-resistance resistor and an n-channel MOSFET is paired with each other as a memory cell; A booster circuit for boosting the potential of the word line of the memory cell to a power supply voltage or higher; and further comprising: an inverter and a plurality of n-channel transistors
It formed using a OSFET and p-channel MOSFET and a capacitor, the boosting circuit, the boosting motion by the clock signal
The internal test signal formed from the external test signal.
Logic circuit that stops supplying the clock signal by
When the internal test signal is at the first level, the potential of the selected word line is raised to the power supply voltage or higher to perform a normal operation, and when the internal test signal is at the second level, The potential of the word line is controlled to be equal to the power supply voltage so that the operation is performed in the test mode.

[0040]

Next, an embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 1 shows one embodiment of the present invention.
FIGS. 2 and 3 are diagrams for explaining (Embodiment 1); FIGS.
FIG. 10 is a diagram for explaining another embodiment (Example 2) of the present invention.

(Embodiment 1) FIG. 1 shows an embodiment of the present invention.
FIG. 2 is a circuit diagram of a word line boost circuit showing (Embodiment 1). The difference between the first embodiment and the "word line boost circuit of the conventional static semiconductor memory device" shown in FIG. 6 is as follows.

That is, in the first embodiment, as shown in FIG. 1, an external test signal input pad (PD) is provided to control an input level of an external terminal in a test in a wafer state. When it is at the high level, the internal test signal is in the normal mode as the first level (low level in this case),
In other words, the operation is performed with the potential of the word line of the memory cell raised to the power supply voltage (Vcc) or more. On the other hand, when the level is low, the internal test signal is at the second level (in this case, high level) The operation is performed in a test mode, that is, in a state where the potential of the word line of the memory cell is equal to the power supply voltage.

Also, in the first embodiment, as shown in FIG. 1, a high-resistance resistor (R ₃ ) is connected between the external test signal input pad (PD) and the power supply potential. (PD) generates an internal test signal (TE) through the inverter 6;
This internal test signal (TE) takes a NOR logic with the signal "φbst", generates a signal "φbst '", and controls the word line boost circuit. (Note that in FIG. 1, reference numeral 7 denotes a nogate, reference numeral 8 denotes an inverter, and other portions common to FIG. 6 described above are indicated by the same reference numerals as in FIG. And to avoid duplication,
The description is omitted. )

Therefore, in the test in the wafer state, the external test signal is maintained at a low level when the data holding test is performed, the test is performed in the test mode, and when the other tests are performed, the external test signal is output. It is carried out at a high level.
Also, after the test process in the wafer state, the external test signal input pad (PD) is used so that it does not operate in the test mode.
The power supply potential is supplied to the section by a resistor (R ₃ ) without being externally controlled, and the internal test signal (TE) is set to the first level to perform the operation while maintaining the normal mode.

(Embodiment 2) FIG. 2 shows another embodiment of the present invention.
FIG. 9 is a circuit diagram of a word line boost circuit showing (Embodiment 2). In the second embodiment, the external terminal input signal is connected to the anodes of the diodes (D ₁ ) of two diode rows, and the cathode of the diode (D ₂ ) is “gate”. The source of a p-channel MOSFET (Q ₁₈ ) whose source is connected to the power supply potential (Vcc)
Connected. Also, this p-channel type MO
The drain of the SFET (Q ₁₈ ) indicates that the gate is at the power supply potential (Vc
c) shows an n-channel type M whose source is connected to the ground potential.
Connected to the drain of the OSFET (Q ₁₉ ).

The above p-channel MOSFET (Q ₁₈ )
And the drain of the n-channel MOSFET (Q ₁₉ )
The output of the inverter 9 is input to the inverter 9. The output of the inverter 9 is a p-channel type M having one end connected to the power supply voltage (Vcc).
OSFET (Q ₂₀ ) and n-channel MOSFET (Q ₂₁ )
The gate of the p-channel MOSFET (Q ₂₀ ) of the “CMOS transfer circuit 14” composed of

The output of the inverter 10 is the p-channel type M whose one end is connected to the power supply voltage (Vcc).
OSFET (Q ₂₀ ) and n-channel MOSFET (Q
₂₁ ) "CMOS transfer circuit 14"
Of the n-channel MOSFET (Q ₂₁ ).

At the other end of the "CMOS transfer circuit 14", the sizes of the transistors constituting the inverter 11 and the inverter 12 are adjusted so that the output (B) becomes high level when the power is turned on. , For level stability, are connected to the input (A) of the flip-flop circuit in which the coupling capacitors (C ₃ , C ₄ ) are inserted. The output (B) is connected to an inverter 13 and generates an internal test signal (TE ') via the inverter 13.

The above-mentioned external terminal input is, as shown in FIG.
5 ". In FIG. 2, parts common to FIGS. 1 and 6 described above are denoted by the same reference numerals as those in FIGS. 1 and 6, and dashes (double parts are common to FIG. 6). They are only shown with dashes, and descriptions thereof are omitted to avoid duplication.

Next, referring to FIG. 2 "Circuit diagram of a word line boost circuit showing the second embodiment" and FIG. 3 "Timing chart for explaining the second embodiment". The internal test signal generation circuit will be described.

In FIG. 2, the forward ON voltage of the diodes (D ₁ , D ₂ ) is “0.8 [V]” and the p-channel type MOS
Assuming that the threshold voltage of the FET (Q ₁₈ ) is “0.7 [V]”, when the voltage at the node (C) exceeds “Vcc + 0.7 [V]”, that is, when the external terminal input is “Vcc + 2” .3 [V] ”, the p-channel MOSFET (Q ₁₈ ) is turned on and the transistor size of the p-channel MOSFET (Q ₁₈ ) is larger than that of the n-channel MOSFET (Q ₁₉ ). , The node (D) rises. The threshold voltage of the n-channel MOSFET (Q ₁₉ ) is also “0.7
[V] ”, the voltage at node (D) is“ Vcc +
0.7 [V] ", and the inverter 9 outputs a low level.
The inverter 10 outputs a high level.

As a result, the CMOS transfer circuit 14 is turned on, the power supply potential (Vcc) is supplied to the input (A) of the flip-flop circuit, the data of the flip-flop circuit is inverted, and the output (B) is output. Becomes low level, the internal test signal (TE ') becomes high level via the inverter 13, and enters the test mode (see FIG. 2). Also, once in the test mode, the flip-flop circuit does not invert and the internal test signal (TE ') keeps the high level, no matter what input level is applied to the external terminal input thereafter. Operation in the test mode becomes possible.

On the other hand, in order to cancel the test mode,
By turning off the power and turning on the power again, the operation can be performed in a normal mode. That is, during the data retention test, after the power is turned on, the external terminal input is set to “Vcc +
2.3 [V] ”or more and the test mode is executed to perform the test. When testing other operation margins, etc., turn off the power once, turn on the power again, and perform the test in the normal mode. (See FIG. 3).

In the normal use state of the semiconductor memory device described above, since the high voltage of the power supply voltage "Vcc + 2.3 [V]" is not applied to the external terminal input, the test mode may be erroneously set. Absent. Also, as this external terminal,
It is also possible to double as an address input terminal, but in this case, it is not necessary to increase the number of terminals. Therefore, in this embodiment, the test can be performed in the test mode not only in the wafer state but also in the assembly process and thereafter.

[0055]

As described above, according to the present invention, the data holding test is performed in the test mode, so that the data
Since the data retention time in the data retention test can be shortened,
The effect that reduction in test cost and improvement in production efficiency can be attained, and the effect that the test efficiency of the semiconductor memory device does not decrease occur.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment (Embodiment 1) of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment (Embodiment 2) of the present invention.

FIG. 3 is a timing chart for explaining a second embodiment (Embodiment 2) of the present invention.

FIG. 4 is a diagram illustrating an example of a conventional static RAM semiconductor memory device.

FIG. 5 is a diagram showing an example of a conventional static RAM semiconductor memory device provided with a means for boosting a word line to a power supply voltage or higher.

FIG. 6 is a circuit diagram showing a conventional word line boost circuit.

FIG. 7 is a circuit diagram showing a conventional word line drive circuit.

[Explanation of symbols]

1 digit line load circuit 2 CMOS data transfer circuit 3, 4, 6, 8 to 13 Inverter 5 NAND gate 7 NOR gate 14 CMOS transfer circuit 15 Address buffer circuit Q _{1 to} Q ₄ , Q ₇ , Q _{8, Q 11, Q 14,} Q 16, Q 19, Q 21 n -channel _{MOSFET Q 5, Q 6, Q} 9, Q 10, Q 12, Q 13, Q 15, Q 17,
Q ₁₈ , Q ₂₀ p-channel MOSFETs W ₁ , W ₂ , WL word lines DG ₁ , DG ₂ digit lines DB ₁ , DB ₂ data bus line Y, -Y digit line pair selection signals R ₁ , R ₂ , R ₃ resistor _{C 1, C 2, C 3} , C 4 volume

Claims (3)

(57) [Claims] 1. A high-resistance resistance element and an n-channel MOS
A flip-flop circuit in which inverters composed of FETs are paired with each other is used as a memory cell, and the word line potential of the memory cell is raised to a power supply voltage or higher.
In a semiconductor memory device having a booster circuit, the booster circuit includes an inverter and a plurality of n-channel MOs.
The booster circuit is formed using an SFET and a p-channel MOSFET and a capacitor, and the booster circuit performs a boost operation by a clock signal.
The internal test signal formed from the external test signal
The logic circuit that stops supplying the clock signal is
When the internal test signal is at the first level, the potential of the selected word line is raised to the power supply voltage or higher to perform a normal operation, and when the internal test signal is at the second level, the selected word line is A potential of which is equal to a power supply voltage and operates in a test mode. 2. The internal test signal is supplied from an external terminal.
2. The semiconductor memory device according to claim 1, wherein the first level or the second level is supplied by an external test signal. 3. The internal test signal maintains a first level when power is turned on, and when the potential of an external test signal at an external terminal first exceeds the power supply voltage after power is turned on. Second
2. The semiconductor memory device according to claim 1, wherein the internal test signal is supplied from an internal test signal generation circuit which maintains the second level irrespective of the potential of the external test signal at the external terminal.