JPH08306198A - Semiconductor memory - Google Patents

Abstract

PURPOSE: To shorten a data holding time by boosting a potential of a word line higher than power supply voltage when a test signal is a first level and making it operate equalizing a potential of a word line to power supply voltage when a test signal is a second level. CONSTITUTION: A pad PD for inputting an external test signal is provided, an input level of an external terminal is controlled, when an input level is a high level, operation is performed in a normal mode in which a potential of a word line of a memory cell is boosted higher than power supply voltage Vcc. A resistor R3 having high resistance is connected between the pad PD for inputting an external test signal and a power supply potential, an internal is generated through the inverter 6, and a word line boosting circuit is controlled. A data holding test is performed in a test mode, and a data holding time can be shortened by providing a means boosting a potential of a word line higher than power supply voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a static RAM semiconductor memory device provided with a means for boosting the potential of a word line above a power supply voltage.

[0002]

2. Description of the Related Art A conventional example of this type of semiconductor memory device will be described with reference to FIG. FIG. 4 is a diagram showing an example of a conventional static RAM semiconductor memory device.

As shown in FIG. 4, a memory cell of a conventional static RAM has: a first n-channel M for connecting a source to a ground potential point.
OSFET (Q ₁ ), The source is connected to the ground potential point, the gate is connected to the drain of the n-channel MOSFET (Q ₁ ), and the drain is connected to n.
Second connection to the gate of the channel MOSFET (Q ₁ )
N-channel MOSFET (Q ₂ ), which has one end connected to the drain of the n-channel MOSFET (Q ₁ ) and the other end connected to the power supply source of the power supply potential (Vcc) ₁ ), a high resistance second load resistor (R ₂ ) having one end connected to the drain of the n-channel MOSFET (Q ₂ ) and the other end connected to a power supply source of the power supply potential (Vcc), and Using the drains of the first and second n-channel MOSFETs (Q ₁ , Q ₂ ) as the first and second data input / output terminals (N ₁ , N ₂ ), the data is fetched, stored, and Memorized data
And a flip-flop circuit that outputs the data.

Then, the first and second memory cells
The data input / output terminals (N ₁ , N ₂ ) of the above are respectively connected via n-channel MOSFETs (Q ₃ , Q ₄ ) for switching.
Connected to digit line pair (DG ₁ , DG ₂ ). In addition, the n-channel MOSFETs (Q ₃ , Q ₄ ) for switching are
DOO, i.e. word - the word line (W ₁₎ decrypts the column address input signals a predetermined word - to select state word line - the output signal of the "word word line selection circuit" is supplied.

Further, the gate is connected to the ground potential between the digit line pair (DG ₁ , DG ₂ ) and the power source potential (Vcc).
"Digit line load circuit 1 'is connected constituted by channel _{MOSFET (Q 5, Q 6)} . On the other hand, between the digit line pair (DG ₁ , DG ₂ ) and the data bus line (DB ₁ , DB ₂ ),
n-channel MOSFET (Q ₇ , Q ₈ ) and p-channel M
OSCET (Q ₉ , Q ₁₀ ) and "C
A MOS data transfer circuit 2 "is provided.

The gates of the n-channel MOSFETs (Q ₇ , Q ₈ ) of the "CMOS data transfer circuit 2" decode the row address input signal to bring a predetermined digit line pair into a selected state. The output signal (Y) of the selection circuit is given, and the gate of the p-channel MOSFETs (Q ₉ , Q ₁₀ ) receives the output signal (Y) from the output signal (-) of the "inverter circuit 3".
Y) (this -Y means that Y is overlined as shown in FIG. 4; the same applies hereinafter).

A plurality of digit line pairs and word lines described above exist in the row direction and the column direction, respectively, and form a memory cell array. In addition, the data bus lines (DB ₁ , DB ₂ ) have a "write circuit" for controlling the write data to the memory cell and a "read circuit" for controlling the read of the data read from the memory cell. Circuit "is connected.

The operation of the conventional semiconductor memory device having the above structure will be described below with reference to FIG. First, when the column address input signal is decoded and a predetermined word line (W ₁ ) is selected during the read operation, the n-channel MOSFETs (Q ₃ , Q ₄ ) for switching are turned on and the memory cell of the memory cell is turned on. Depending on the stored contents, one of the digit lines (DG ₁ , DG ₂ ) (for example, “DG ₂ ”) becomes low level and the other (for example, “DG ₁ ”) becomes high level.

The digit line pair selection signals (Y and -Y) output by decoding the row address input signal are the predetermined "CMO".
The S data transfer circuit 2 "is activated, and the digit line (DG ₁ ,
The data of DG ₂ ) is transmitted to the data bus (DB ₁ , DB ₂ ). The "readout circuit" is de - buses (DB _1, DB ₂₎ de from - to amplify the data, to transmit the stored information of the memory cell to the output circuit.

On the other hand, during the write operation, the column address input signal is decoded and a predetermined word line (W ₁ ) is selected, and the digit line pair selection signal (Y,-) is decoded and output. Y) activates a predetermined "CMOS data transfer circuit 2". Then, the write circuit receives the data from the data input circuit, forcibly sets _{one of} the data buses (DB ₁ , DB ₂ ) to the ground potential, and one of the digit lines (DG ₁ , DG ₂ ). Is a ground potential, and the selected word line (W ₁ ) is connected to an n-channel MOSF for switching.
Data is stored in the memory cell via ET (Q ₃ , Q ₄ ).

Next, the potentials of the _first and _{second data} input / output terminals (N ₁ , N ₂ ) at the time of writing to the memory cell will be described. De to the memory cell as described above - when writing data, predetermined digit lines (DG ₁₎ to the power supply potential (Vcc), also applies a ground potential to the digit line (DG _2), and a predetermined word - Line is selected. At this time, the word line is
If the potential is equal to (Vcc), the first data
The high level potential of the data input / output terminal (N ₁ ) becomes “power supply potential (Vcc) −Vth” immediately after writing. (In addition, "Vt
h "is the threshold voltage of the switching n-channel MOSFET.)

Here, if the power supply potential (Vcc) is set to "5.0 V" in consideration of normal operation, Vth becomes "about 1.5 V" depending on manufacturing conditions, so the first data Input / output terminal
The high-level potential of (N ₁ ) is “about 3.5V”. Also,
The resistance elements (R ₁ , R ₂ ) having a high resistance have a remarkably high resistance value in order to realize a low current consumption of the memory cell. Resistance element
(R ₁ , R ₂ ) has a high resistance value that prevents the information charges accumulated at the data input / output terminal (N ₁ or N ₂ ) from being discharged.

Therefore, the data of the memory cell immediately after writing is written.
In order to charge the high level potential "about 3.5V" at the input / output terminal to the power supply potential (Vcc) by the charge supplied from the high resistance element, for example, the resistance element has about 10 ¹² Ω If the capacity of the data storage node at the output end is about 10 ^-15 F, the time constant is about several ms, so it takes several ms or more. This time is a normal static type R
The operation cycle of the read and write operations of the semiconductor memory device of AM is longer than the operation cycle “up to several 100 ns”.

As described above, the high level at the data input / output terminal of the memory cell is the power supply voltage (Vc
Lower than c). Therefore, when performing a low power supply voltage operation, for example, when "Vcc = 2.0V", at the time of writing, the high level of the data input / output node of the memory cell is supplied only "about 0.5V". Does not exceed the threshold voltage "about 0.7 V" of the n-channel MOSFET of the inverter forming the pair of the gate input flip-flop circuits, so that stable writing and reading of data in the flip-flop circuits can be performed. It will be difficult. That is, this becomes an operation limit of the static RAM semiconductor memory device at a low power supply voltage.

By the way, in recent years, semiconductor manufacturing manufacturers have been forced to commercialize low-voltage operation because of the demands of users. Therefore, in the conventional static RAM semiconductor memory device, in order to realize operation at a low power supply voltage, the potential of the word line in the selected state is boosted above the power supply voltage and the data input / output terminal of the memory cell is The high level of the node is raised to the power supply potential to expand the operation margin of the memory cell.

A conventional technique for boosting the potential of the word line above the power supply voltage will be described with reference to FIGS. FIG. 5 is a diagram showing an example of a conventional static RAM semiconductor memory device provided with a means for boosting the word line above the power supply voltage, and FIG. 6 is a diagram showing a conventional word line boot.
FIG. 7 is a circuit diagram showing a storage circuit, and FIG. 7 is a circuit diagram showing a conventional word line drive circuit.

FIG. 5 shows a structure in which the conventional static RAM semiconductor memory device shown in FIG. 4 is provided with a "word line boost circuit". As shown in FIG. 5, in the prior art, since the potential of the word line is boosted to the power supply voltage or more, the "voltage boosted voltage boosted to the power supply voltage or more" generated from the "word line boost circuit" is generated. (Vbst) "is - supplied to the" word word line drive circuit ", its output is boosted memory cell word than the supply voltage - is supplied to the word line (W _1, W _2). (Note that each reference numeral in FIG. 5 is the same as that in FIG. 4 described above, and since it is duplicated, its description is omitted.)

As shown in FIG. 6, the "word line boost circuit" has: an inverter 4 for inputting a signal (φbst); a signal (φbst) for gate input; N-channel MOSFET (Q ₁₁ ) whose gate is connected to the ground potential, p-channel M to which the signal (φbst) is gate-inputted
OSFET (Q ₁₂ ), source connected to power supply potential (Vcc), gate p-channel MOSFET (Q ₁₂ ) and n-channel MOSFE
P-channel MO connected to the drain of T (Q ₁₁ )
SFET (Q ₁₃ ), one end of which is connected to the output of the inverter 4 and the other end of which is p
A circuit connected to the source of the channel MOSFET (Q ₁₂ ) and the drain of the p-channel MOSFET (Q ₁₃ ).
It consists of a tostrap capacitance (C ₁ ) ,. In addition, the capacitance (C ₂ ) is the boost voltage (V
bst) parasitic capacitance.

The "word line driving circuit" is shown in FIG.
As shown in FIG. 5, a combination of internal complementary column address signals formed by an address buffer receiving a plurality of external column address input signals is input to the input terminal of the NAND gate 5.

On the other hand, the output of the NAND gate 5 is an n-channel MOSFET whose gate is connected to the power supply potential (Vcc).
It is connected to the source of (Q ₁₄ ). The drain of this n-channel MOSFET (Q ₁₄ )
cc) boosted voltage (Vbst) is used as a power supply potential supply source, and its output is connected to the word line (WL) of the memory cell. A p-channel MOSFET (Q ₁₅ ) and an n-channel MOSFET ( composed of Q ₁₆₎ - "source is input to the" CMOS inverter motor 6 "" - scan the boosted voltage (Vbs
The gate is connected to the drain of a p-channel MOSFET (Q ₁₇ ) which is connected to the word line (WL).

Next, the operation shown in FIGS. 6 and 7 will be described. The signal (φbst) is at the power supply potential, the p-channel MOSFET (Q ₁₂ ) is in the off state, and the n-channel M
OSFET (Q ₁₁ ) and p-channel MOSFET (Q ₁₃ )
Is on, the boosted voltage (Vbst) is precharged to the power supply voltage (Vcc) (see FIG. 6).

When the signal (φbst) changes from the power supply potential to the ground potential, the p-channel MOSFET (Q ₁₂ ) is turned on and the n-channel MOSFET (Q ₁₁ ) and p-channel MOSFET (Q ₁₃ ) are turned off. At the same time
Since the bootstrap capacitance (C ₁ ) connected to the output of the inverter 4 is charged by changing the output of the inverter 4 from the ground potential to the power supply potential, the bootstrap effect begins. The potential of the boosted voltage (Vbst) further rises from the power supply voltage level (Vcc) (see FIG. 6).

When the word line is now in the selected state, that is, the internal complementary column address signals input to the NAND gate 5 are all at the high level and the output of the NAND gate 5 is at the low level, the boosting is performed. The output of the CMOS inverter 6 composed of the p-channel MOSFET (Q ₁₅ ) and the n-channel MOSFET (Q ₁₆ ) using the voltage (Vbst) as the power supply potential source, that is, the word line (WL) of the memory cell The level is raised to a voltage equal to the boost voltage (Vbst) (see FIG. 7).
reference).

[0024]

In the conventional static RAM semiconductor memory device described above, the data storage node (N ₁ ) and the ground potential of the memory cell may be affected by, for example, a process defect or a variation in the manufacturing process. An abnormal leak occurs between the point and the point. In this case, de - even data storage node (N ₁₎ in an attempt to store a high level, the Li - high level of de via click - data disappears. Therefore, a data retention test is carried out in order to remove this defective data retention.

The data holding time "t" at the time of this test is, for example, as follows: Data storage node capacity (C) between the data storage node (N ₁ ) of the memory cell and the ground potential point. "C [F]",-leak resistance is "R [Ω]",-high level voltage when stored in the memory cell is "Vn"
[V] ",-If the potential of the high-level data storage node that drops to the ground potential is" V [V] ", it is expressed by the following equation (1).

[0026]

[Equation 1]

For example, when the potential of the high-level data storage node (N ₁ ) that drops by a leak is "V ₁ ", the data of the memory cell disappears and the data retention is defective. when the sum - when the potential of the word line is equal to the power supply voltage "Vcc" is data of high level, as described above - data storage node (N ₁₎ for is "Vcc-Vth", removing defective The data holding time (t ₁ ) required for the operation is expressed by the following equation (2).

[0028]

[Equation 2]

When a low power supply voltage operation is realized,
As described above, since the potential of the word line is boosted to the power source voltage (Vcc) or higher, the high level data storage node becomes "Vcc", and as a result, the data necessary for eliminating the defect is generated. The data retention time (t ₂ ) is expressed by the following equation (3).

[0030]

(Equation 3)

For example, "Vcc = 4.5 [V]", "Vth = 1.5"
When [t ₂ / t ₁ ] is calculated with [V] and “V ₁ = 0.7 [V]”, it is expressed by the following equation (4).

[0032]

[Equation 4]

Further, especially when the voltage is low, “Vcc = 2.7
[V] ”,“ Vth = 1.5 [V] ”,“ V ₁ = 0.7 [V] ”,
Calculating the "t ₂ / t _1" is represented by the following formula (5).

[0034]

(Equation 5)

Therefore, when testing a static semiconductor memory device which realizes a low power supply voltage operation by boosting the word line of the memory cell above the power supply voltage, the holding time of the data holding test is the memory. Compared to the case where the potential of the word line of the cell is equal to the power supply voltage, it increases to "1.28 times" and to "2.50 times" when the voltage is low.
It has become clear that there is a problem that the test efficiency of the semiconductor memory device is deteriorated.

Regarding a semiconductor memory device of a dynamic RAM composed of one transistor and one capacitor, Japanese Unexamined Patent Publication No. 3-15679 discloses that "the level of a word line of a memory cell is a power supply in a test mode. The voltage is equal to the voltage, and when operating in the normal mode, the voltage is boosted above the power supply voltage. "

In the above-mentioned dynamic RAM semiconductor memory device, after the row address is fetched, the trigger signal of the word line generation circuit is generated, and the trigger signal and the booster circuit are used to generate the original word line signal. The signal is boosted, and the boosting of the original signal of the word line signal is suppressed by the test signal in the test mode (see the above-mentioned publication). Therefore, this dynamic RAM semiconductor memory device has a drawback that it cannot be applied to a static RAM semiconductor memory device that operates asynchronously.

The present invention has been made in view of the above problems and drawbacks, and its objects are: First, by holding a data holding test in a test mode, holding the data. It is to provide a semiconductor memory device capable of shortening the data holding time in the test, reducing the test cost and improving the production efficiency. Second, in particular, the potential of the word line is higher than the power supply voltage. In a static RAM semiconductor memory device having a means for boosting the voltage, a holding time in a data holding test can be shortened,
As a result, it is an object of the present invention to provide a semiconductor memory device in which the test efficiency of the semiconductor memory device does not decrease.

[0039]

A semiconductor memory device according to the present invention uses, as a memory cell, a flip-flop circuit composed of a high resistance resistance element and an inverter composed of an n-channel MOSFET paired with each other. , Equipped with a method of boosting the potential of the word line of this memory cell to the power supply voltage or more,
In addition, when the internal test signal is at the first level, the potential of the word line in the selected state is boosted to the power source voltage or more to perform normal operation, and at the second level, the selected word line is selected. It is characterized in that the potential of the negative line is controlled to be equal to the power supply voltage so that the operation is performed.

[0040]

Next, an embodiment of the present invention will be described with reference to FIGS.
Will be described with reference to. In addition, FIG. 1 shows an embodiment of the present invention.
FIG. 4 is a diagram for explaining (Example 1), and FIGS.
FIG. 8 is a diagram for explaining another embodiment (second embodiment) of the present invention.

(Embodiment 1) FIG. 1 shows an embodiment of the present invention.
It is a circuit diagram of a word line boost circuit showing (Embodiment 1). The first embodiment is different from the above-mentioned "word line boost circuit of a conventional static semiconductor memory device" shown in FIG. 6 in the following points.

That is, in the first embodiment, as shown in FIG. 1, an external test signal input pad (PD) is provided to control the input level of the external terminal in the wafer state test. At the high level, the internal test signal is in the normal mode as the first level (low level in this case),
In other words, the operation is performed with the word line potential of the memory cell boosted to the power supply voltage (Vcc) or higher. On the other hand, when the level is low, the internal test signal becomes the second level (high level in this case). In the test mode, that is, the potential of the word line of the memory cell is set to be equal to the power supply voltage.

In the first embodiment, as shown in FIG. 1, a high resistance resistor (R ₃ ) is connected between the external test signal input pad (PD) and the power supply potential. Internal test signal (TE) is generated from (PD) via inverter 6,
The internal test signal (TE) takes the NOR logic with the signal "φbst" to generate the signal "φbst '" and controls the word line boost circuit. (Note that in FIG. 1, 7 is a nogate, 8 is an inverter, and other parts common to those in FIG. 6 are shown by adding the same reference numerals as those in FIG. 6 with a dash. And to avoid duplication,
The description is omitted. )

Therefore, in the test in the wafer state, the external test signal is maintained at the low level when the data holding test is performed, and the external test signal is applied when the other test is performed. Maintain and implement at a high level.
In addition, after the test process in the wafer state, the external test signal input pad (PD) is used so that it does not operate in the test mode.
The portion is not controlled from the outside but is supplied with a power supply potential by a resistor (R ₃ ), the internal test signal (TE) is set to the first level, and the normal mode is maintained to operate.

(Embodiment 2) FIG. 2 shows another embodiment of the present invention.
FIG. 6 is a circuit diagram of a word line boost circuit showing a second embodiment. In the second embodiment, the external terminal input signal is connected to the node of the diode (D ₁ ) of the two diode rows, and the cathode of the diode (D ₂ ) is "gate". Source of the p-channel MOSFET (Q ₁₈ ) connected to the power supply potential (Vcc).
Is connected to the Also, this p-channel MO
The drain of the SFET (Q ₁₈ ) is "gate is the power supply potential (Vc
In c), n-channel type M whose source is connected to ground potential
The drain of the OSFET (Q ₁₉ ).

The above p-channel MOSFET (Q ₁₈ )
And the drain of the n-channel MOSFET (Q ₁₉ ) is
It is input to the inverter 9, and the output of the inverter 9 is: an inverter 10; a p-channel type M whose one end is connected to the power supply voltage (Vcc).
OSFET (Q ₂₀ ) and n-channel MOSFET (Q ₂₁ )
Connected to the gate of the p-channel MOSFET (Q ₂₀ ) of the "CMOS transfer circuit 14".

The output of the inverter 10 is the above-mentioned "p-channel type M whose one end is connected to the power supply voltage (Vcc)".
OSFET (Q ₂₀ ) and n-channel MOSFET (Q
₂₁ ) "CMOS transfer circuit 14""
Connected to the gate of an n-channel type MOSFET (Q ₂₁ ).

At the other end of the "CMOS transfer circuit 14", the size of the transistors forming the inverter 11 and the inverter 12 is adjusted so that the output (B) becomes high level when the power is turned on. , For the purpose of stabilizing the level, the coupling capacitors (C ₃ , C ₄ ) are connected to the input (A) of the flip-flop circuit. The output (B) is connected to the inverter 13 and generates an internal test signal (TE ') via the inverter 13.

The above-mentioned external terminal input is, as shown in FIG. 2, an "address buffer circuit 1" as an address input terminal.
5 "is also input. In addition, in FIG. 2, the same reference numerals as those in FIGS. 1 and 6 are used for the respective portions common to those in FIGS. It is only shown with a (dash) and its description is omitted to avoid duplication.

Next, referring to FIG. 2 "circuit diagram of a word line boost circuit showing the second embodiment" and FIG. 3 "timing chart for explaining the second embodiment", The internal test signal generation circuit will be described.

In FIG. 2, the forward ON voltage of the diodes (D ₁ , D ₂ ) is "0.8 [V]", and the p-channel type MOS is
Assuming that the threshold voltage of the FET (Q ₁₈ ) is “0.7 [V]”, the voltage at the node (C) exceeds “Vcc + 0.7 [V]”, that is, the external terminal input is “Vcc + 2”. .3 [V] ”, the p-channel MOSFET (Q ₁₈ ) turns on and the transistor size of the p-channel MOSFET (Q ₁₈ ) is made larger than that of the n-channel MOSFET (Q ₁₉ ). , The node (D) rises. The threshold voltage of the n-channel MOSFET (Q ₁₉ ) is also 0.7
[V] ”, the voltage at node (D) is“ Vcc +
0.7 [V] ”, the inverter 9 outputs a low level,
The inverter 10 outputs a high level.

As a result, the CMOS transfer circuit 14 is turned on, the power supply potential (Vcc) is supplied to the input (A) of the flip-flop circuit, the data of the flip-flop circuit is inverted, and the output (B) is output. Becomes low level, the internal test signal (TE ') becomes high level through the inverter 13, and becomes the test mode (see FIG. 2). Also, once in test mode, no matter what input level is applied to the external terminal input thereafter, the flip-flop circuit does not invert and the internal test signal (TE ') continues to maintain a high level. The operation in test mode is possible.

On the other hand, in order to cancel the test mode,
By turning off the power and then turning on the power again, the operation can be performed in the normal mode. In other words, during the data retention test, after turning on the power, the external terminal input is set to "Vcc +
2.3 [V] ”or more is applied to perform the test in the test mode. When testing other operation margins, etc., turn off the power and then turn on the power again to test in the normal mode. Is carried out (see FIG. 3).

In the normal use state of the semiconductor memory device described above, since a high voltage of “Vcc + 2.3 [V]” is not applied to the external terminal input, the test mode may not be mistaken. Absent. Also, as this external terminal,
It is also possible to serve as an address input terminal or the like, but in this case, it is not necessary to increase the number of terminals. Therefore, in this embodiment, not only the wafer state but also the test in the test mode can be performed after the assembly process.

[0055]

As described above, according to the present invention, the data retention test is carried out in the test mode to obtain the data.
Since the data retention time in the data retention test can be shortened,
There is an effect that the test cost can be reduced and the production efficiency can be improved, and an effect that the test efficiency of the semiconductor memory device is not lowered is brought about.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment (Embodiment 1) of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment (Embodiment 2) of the present invention.

FIG. 3 is a timing chart for explaining a second embodiment (Embodiment 2) of the present invention.

FIG. 4 is a diagram showing an example of a conventional static RAM semiconductor memory device.

FIG. 5 is a view showing an example of a conventional static RAM semiconductor memory device provided with a means for boosting a word line above a power supply voltage.

FIG. 6 is a circuit diagram showing a conventional word line boost circuit.

FIG. 7 is a circuit diagram showing a conventional word line drive circuit.

[Explanation of symbols]

1 Digit line load circuit 2 CMOS data transfer circuit 3, 4, 6, 8 to 13 Inverter 5 NAND gate 7 Nogate 14 CMOS transfer circuit 15 Address buffer circuit Q _{1 to} Q ₄ , Q ₇ , Q ₈ , Q ₁₁ , Q ₁₄ , Q ₁₆ , Q ₁₉ , Q ₂₁ n-channel MOSFETs Q ₅ , Q ₆ , Q ₉ , Q ₁₀ , Q ₁₂ , Q ₁₃ , Q ₁₅ , Q ₁₇ ,
Q ₁₈ , Q ₂₀ p-channel MOSFET W ₁ , W ₂ , WL word line DG ₁ , DG ₂ digit line DB ₁ , DB ₂ data bus line Y, -Y digit line pair selection signal R ₁ , R ₂ , R ₃ resistance C ₁ , C ₂ , C ₃ , C ₄ capacitance

Claims (3)

[Claims] 1. A high resistance resistance element and an n-channel MOS.
In a semiconductor memory device using a flip-flop circuit composed of FET inverters paired with each other as a memory cell and boosting the potential of a word line of the memory cell above a power supply voltage, When the internal test signal is at the first level, the potential of the word line in the selected state is boosted above the power supply voltage to perform normal operation, and when it is at the second level, the selected word line is in the selected state. A semiconductor memory device characterized in that the potential of the line is made equal to the power supply voltage and operates in a test mode. 2. The semiconductor memory device according to claim 1, wherein the internal test signal is supplied with a first level or a second level according to an input signal from an external terminal. 3. The internal test signal maintains the first level when the power is turned on, and becomes the second level when the potential of the input signal of the external terminal first exceeds the power supply voltage after the power is turned on. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is supplied from an internal test signal generation circuit which continues to maintain the second level thereafter regardless of the potential of the input signal of the external terminal.