KR100373223B1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
KR100373223B1
KR100373223B1 KR19960018651A KR19960018651A KR100373223B1 KR 100373223 B1 KR100373223 B1 KR 100373223B1 KR 19960018651 A KR19960018651 A KR 19960018651A KR 19960018651 A KR19960018651 A KR 19960018651A KR 100373223 B1 KR100373223 B1 KR 100373223B1
Authority
KR
South Korea
Prior art keywords
potential
memory cell
voltage
static memory
mos transistor
Prior art date
Application number
KR19960018651A
Other languages
Korean (ko)
Inventor
기요오 이또
고이찌로 이시바시
Original Assignee
가부시끼가이샤 히다치 세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP95-136349 priority Critical
Priority to JP13634995 priority
Priority to JP02757496A priority patent/JP4198201B2/en
Priority to JP96-027574 priority
Application filed by 가부시끼가이샤 히다치 세이사꾸쇼 filed Critical 가부시끼가이샤 히다치 세이사꾸쇼
Application granted granted Critical
Publication of KR100373223B1 publication Critical patent/KR100373223B1/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction for memory cells of the field-effect type
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/11Static random access memory structures
    • H01L27/1104Static random access memory structures the load element being a MOSFET transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/11Static random access memory structures
    • H01L27/1116Peripheral circuit region
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903FET configuration adapted for use as static memory cell

Abstract

A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit operating at a low voltage, in particular a semiconductor integrated circuit comprising a static memory cell constituted by a MIS transistor or a MOS transistor (hereinafter, simply referred to as a MOS or MOS transistor) as a memory cell. A circuit suitable for high speed and low power of a memory (static random access memory).

As the MOS transistor, which is a type of field effect transistor having a gate insulating film, decreases withstand voltage as it becomes finer, its operating voltage must be lowered. Even in this case, in order to maintain the high speed operation, it is necessary to lower the threshold voltage V T of the MOS transistor in accordance with the decrease in the operating voltage. This is because the operating speed is governed by the effective gate voltage of the MOS transistor, that is, the operating voltage minus V T , and the larger this value, the higher the speed. In general, however, when V T is set to about 0.4 V or less, as is well known, a DC current, called a subthreshold current, increases exponentially with the decrease of V T , which is inherently blocked. For this reason, in a semiconductor integrated circuit composed of a plurality of MOS transistors, even if it is a CMOS circuit, the direct current increases significantly. Therefore, there is an inherent problem in future semiconductor devices in which high speed, low power, and low voltage operation are important. That is, the subthreshold current is generated and becomes a large direct current as the whole chip. For this reason, it is impossible to make the V T of the transistor in the memory cell, especially the cross-coupled transistor, less than about 0.4V. However, in this case, the effective gate voltage is further lowered with the decrease in the operating voltage. For this reason, the operation margin of the memory cell also (margin) is narrower, the operating speed is easy to be affected by the manufacturing variation of the decrease, or V T.

Figure 2 shows a memory cell and waveform diagram of the prior art to further illustrate the above problem.

As a memory cell, a CMOS type static memory (SRAM) is taken as an example. First, the memory cell is in an unselected state, that is, the word line WL is at a low level equal to 0V, the memory node N 2 in the cell is at a high level equal to 1V equal to the power supply voltage Vcc, and the other memory node N 1 is at a low level equal to 0V. Consider the case of remembering. Conventionally, since all transistors of the memory cell have a V T of 0.4 V or more, the N-channel MOS transistor Q S2 and the P-channel MOS transistor Q C1 are both non-conductive. This is due to the gate-to-source voltage of 0V at Q S2 and Q C1 . Thus, the current flowing through Vcc can be ignored. This is why SRAM is low power. The voltage margin of this memory cell decreases as Vcc-V T decreases. Therefore, to lower the increasing Vcc V T also andoejiman unless low, go to lower the V T less than 0.4V begins to flow to the original ratio of two transistors Q S2, Q can be a C1-conductive sub-threshold current, and V T It increases exponentially with the decrease of. In general, V T changes due to variations in the manufacturing process and the subthreshold current increases as the temperature increases, so considering the V T change (deviation) and the rise in junction temperature, this current becomes larger in the worst case conditions. Since this current flows to all memory cells in the chip, a current of about 10 mA or more may flow even in a 128K bit SRAM. This current is also the data holding current of the entire cell array. This is a big problem considering that the data holding current of a conventional SRAM using a MOS transistor with a relatively high threshold voltage so that the subthreshold current does not substantially occur can be 10 μA or less. Therefore, in terms of current, V T must be set to a relatively large value such as about 0.4 V or more. Here, the V T, for example, looks at a state fixed at 0.5V, consider the case of lowering the Vcc. The demand for lowering Vcc arises from the demand for lower power or the demand for driving with one battery, in addition to the demand for lowering the breakdown voltage of the MOS transistor. For example, when the MOS transistor becomes smaller in size, the channel length is 0.5 μm or less, or the gate insulating film thickness is 6 nm or less, the transistor operates sufficiently fast even when the external power supply voltage Vcc is set to a low voltage of 1.5 to 1.0 V. Therefore, it is possible to lower Vcc to this extent by giving priority to low power. However, if Vcc is lowered, the voltage margin of the memory cell is significantly lowered. In other words, the effective gate voltage of the conduction transistor Q S1 is Vcc-V T , and when Vcc approaches V T , the effective gate voltage becomes small, and the variation rate for the change of V T becomes remarkable. In addition, the well-known soft error immunity is also lowered, and margin for equivalent noise such as the difference in threshold voltage (so-called offset voltage) between the cross-coupled pair transistors Q S1 and Q S2 , Q C1 and Q C2 in the memory cell. Also decreases.

Even when the memory cell is selected, if V T is high as 0.5V and Vcc is low, the operation speed is low or the operating margin is reduced. When Vcc of 1 V is applied to the word line WL, for example, Q T1 and Q S1 are conducting, and a small voltage is changed in the DL by the current flowing therein and the load resistance (actually composed of a MOS transistor) connected to the data line DL. (0.2V) appears. On the other hand, Q S2 is non-conducting because its gate voltage is sufficiently lower than V T , and hence no voltage change appears in other data lines / DL. By the voltage polarity between the data pairs, the memory information of the memory cells is discriminated and read is executed. Here, the larger the voltage change appearing in the DL, the more stable it is, but for this purpose, it is necessary to flow as large and constant current as possible through Q S1 and Q T1 . Since the effective gate voltages of Q S1 and Q T1 are substantially the same and are Vcc-V T , the current decreases with the decrease in Vcc as described above, and the effect of the change in V T is strong.

As described above, in the conventional circuit and the driving method, the DC current increases remarkably, the operating speed of the memory cell decreases, fluctuates, or the operating margin decreases with the decrease of Vcc. Therefore, the performance of an SRAM chip or an example of a microprocessor chip incorporating an SRAM also degrades significantly with the deterioration of Vcc.

SUMMARY OF THE INVENTION An object of the present invention is to suppress an increase in subthreshold current and a decrease in voltage margin associated with low voltage operation of a static memory cell made of a MOS transistor in a static memory or a semiconductor device incorporating a static memory. .

The objective is to provide a voltage of two memory nodes in a memory cell in a non-selected state in a static memory cell in which a MOS transistor cross-links substantially no current flows between the drain and the source even though the voltages of the gate and the source are the same. The voltage of at least one feeder line of this memory cell so that the difference is greater than the voltage difference between the two memory nodes when the memory cell is selected and a voltage corresponding to write information is applied to the storage node of the memory cell on the data pair line. By controlling it. As a result, the voltage between the two memory nodes in the memory cell can be sufficiently high even if the main power supply voltage at the time of selecting the memory cell remains, so that the memory cell has low power and a wide operating margin, thereby enabling stable operation.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1A to 1C are diagrams showing one embodiment of the present invention. FIG. 1A shows an example in which a transistor Qp, which is a means for controlling the connection of the operation potential V CH of a circuit and a memory cell, is added for each cell, and FIG. 1B shows the addition of Qp for each row. For example, FIG. 1C illustrates an example of sharing Qp in all cells.

For simplicity, the threshold voltage V T of all transistors in the memory cell is 0.5V. Therefore, if the voltages of the gate and the source are almost the same, no subthreshold current flows through the transistor. Fig. 1A is a conceptual diagram of the present invention which is the most basic. The P-channel MOS Qp serving as a switch between the common source of the P-channels MOS Q C1 and Q C2 , which are the power supply nodes on the high potential side of the memory cell MC, and the power supply V CH is inserted into the memory cell. The common source of the N-channel MOS Q S1 , Q S2 which is the low-power feed node of the memory cell MC is connected to the reference potential Vss (normally, the ground potential 0V). The memory cell MC illustrated here is a static memory cell composed of MOS transistors whose gate and drain are cross-coupled with each other. In detail, there are an inverter composed of Q C1 and Q S1 and an inverter composed of Q C2 and Q S2 , and a memory cell and a memory node N 1 , N each having an output of one inverter connected to an input of the other inverter. It consists of two transfer MOS transistors Q T1 and Q T2 , each of which is connected to one end thereof. The operating environment of the memory cell MC is a power supply of the voltage Vcc supplied from the outside is sufficient that the current supply capability of high power, and power supply of the voltage Vcc is higher than V CH is in a low current supply capability of the power source. In a power supply having a low current supply capability, there is a problem that the voltage of the power supply temporarily decreases when a current higher than the supply capability flows.

When data is written to a memory cell on a data pair line, Vcc is normally applied to one side of the pair and 0 is applied to the other side with Qp turned off. At this time, when the word line voltage is set to Vcc, Vcc-V T which drops by V T of Q T1 or Q T2 is input to either of the storage nodes N 1 and N 2 , and 0 is input to the other. However, in this state, the storage voltage (difference voltage between nodes N 1 and N 2 ) becomes Vcc-V T , for example, when Vcc = 1V and V T = 0.5V, it becomes 0.5V, which is too low. Thus, after writing, i.e., after turning off the word line voltage, Qp is conducted and a sufficiently high V CH (e.g., 2V) is applied to the common source. The cross-coupled transistors in the memory cell are then activated to act as differential amplifiers, with the result that either one of N 1 , N 2 is charged to V CH and the other is zero. As a result, the memory voltage rises from Vcc-V T to V CH . The timing of Qp conduction does not have to match the word line selection timing. However, the word line voltage is turned off to prevent unnecessary current from flowing through the memory cells through the memory cell at the power supply V CH with weak current supply capability. It is preferable to become a later timing. Further, the node in the period until the word line off, and then to conduct Qp N 1, N 2 of the write data is maintained by the parasitic capacitance with each of the nodes N 1, N 2. As described above, if V CH is continuously supplied to the memory cell while Qp is turned on during the data holding period or standby after the memory cell is activated, the operation margin of the memory cell is expanded. In addition, the operation is high speed and stable even when the memory cell is read. This is because the current driving capability of Q S1 or Q S2 is improved by the increase in the gate voltage. As described above, since the light can be executed while the Qp is not conducting, the memory cell is dynamic in any write data, thereby enabling low power and high speed light. If there is no Qp and V CH is directly connected to the memory cell, or if Qp conducts during the write process, the current flows through Qp for a long time, making it difficult to invert or invert the stored memory information. Irrationality occurs.

FIG. 1B illustrates an embodiment in which Qp is shared among a plurality of memory cells, and the memory cell becomes smaller as the number of transistors decreases. Here, when light in a state in which the whole, the non-Q P1 as described above, the MC 1, MC 1, for example, the data pairs in the gate of the gate of Q 0 C1, Q C2, the Vcc-V T (0.5V) Forcibly added. Therefore, V CH was by Q C1 continuity by then is charged into the parasitic capacitance of the common power supply line PL 1 is discharged to Vcc-V T. At this time, the memory cell MC 2 on the same word line WL 1 is substantially subjected to a read operation, but the memory information of MC 2 is not destroyed due to the voltage drop of PL 1 described above. The memory voltage of MC 2 also only drops from V CH up to Vcc-V T , which is the voltage of PL 1 . The sensitivity of the differential amplifier in the memory cell is determined by the offset voltage of the paired transistors and the like, which is, for example, about 0.2V or less, and the information is not destroyed since Vcc-V T is above this sensitivity. That is, if V CH is added to PL 1 again by turning on Q P1 after the writing is completed, the memory voltage of MC 2 is also changed to V CH as in MC 1 . In this embodiment, only one feed line corresponding to the selected word line needs to be charged to V CH . Since many other power supply lines (PL 2 and the like) are in the V CH state, the charging operation does not occur even when the corresponding charging transistor Q P2 is turned on. In other words, the charging of the feeder is localized and lowered in power.

FIG. 1C illustrates an embodiment in which the charge transistor Qp is shared by all memory cells, and the degree of integration is improved from the above-described example. However, in this case, since the voltages of all the feeders including the feedline of the memory cell on the unselected word line side drop, the charge / discharge power for charging them to V CH may increase or become low speed. In addition, if the feed lines adjacent to the word lines are shared, the area of the memory cells can be reduced. For example, in FIG. 1B, when PL 1 and PL 2 are one common feed line and controlled by one transistor, the number of wirings of the memory cell is effectively reduced.

In addition, a circuit configuration for providing a switch MOS transistor in a feed node on the high potential side of a memory cell of an SRAM is described in Japanese Patent Laid-Open No. 60-38796 or Japanese Patent Laid-Open Publication No. Hei 2-108297. The potential connected via the power source potential supplied to the apparatus is completely different from the present invention.

Hereinafter, a more specific embodiment will be described, mainly including the write operation as well as the read operation, taking the example of FIG. 1B as an example.

3 is a circuit diagram of an embodiment according to the present invention, FIG. 4 is a timing diagram at read time, and FIG. 5 is a timing diagram at write time.

As a memory cell, a flip-flop type cell consisting of a P-channel MOS transistor and an N-channel MOS transistor is taken as an example, and the threshold voltage V T of all transistors in the cell is high enough to almost ignore the subthreshold current, for example, 0.5V. Shall be. For the sake of simplicity, a 4-bit cell array is taken as an example, and it is assumed that Vcc = 1 V and V CH = 2 V under the assumption that Vcc single power supply drive of the SRAM is performed by battery driving. Features of the invention

[1] The voltage of the cell feed lines PL 1 and PL 2 is switched in accordance with the operation timing of the cell. That is, the information holding voltage when the cell is not selected (2V in FIG. 3) is determined by the voltage applied from the feed line of the cell, and its magnitude is larger than the write voltage written to the data line in this cell when the cell is selected. The voltage at the feed line of the cell is controlled.

[2] The data lines DL 1 , / DL 1 , DL 2 , and / DL 2 provide an approximate intermediate voltage (Vcc / 2 = 0.5V) of the maximum voltage that the data line can take (Vcc = 1V in FIG. 3). It works by reference. This reduces the charge / discharge power of the data line by half.

[3] The amplitude of the pulse voltage of the selected word line is larger than the maximum voltage that the data line can take. In order to eliminate the influence of the threshold voltage V T of the select transistor connected to the word line, the amplitude of the pulse voltage is set to a value V CH greater than V T above the maximum voltage of the data line in a boost circuit or the like in the chip. In addition, the current driving capability of O T1 and Q T2 is improved by the boosted portion, resulting in high speed.

Consider a case in which a part of the SRAM embedded in the microprocessor chip or the like or the SRAM chip itself (hereinafter, SRAM collectively) is deactivated by the SRAM activation signal CE. The main part in the SRAM is in the precharge state by the precharge signal φ P. For example, the feed lines PL 1 and PL 2 of the cell are precharged with the voltage V CH sufficiently boosted inside the chip based on the external power supply voltage Vcc. The decrease in the storage voltage in the cell due to the minute leakage (leakage) current in the cell is prevented by the compensation currents from the P-MOS Q P1 and Q P2 , whereby the storage state of each cell is maintained. Here, V CH is formed in the voltage conversion circuit VC2. VC2 is formed by boosting Vcc in the chip using a charge pump circuit for driving a capacitor, and accordingly, the current driving capability thereof is reduced. However, since the threshold voltage of the transistor in the cell is set high enough to be 0.5 V or more, the sum of the leak current of the cell can be sufficiently reduced to only 10 µA or less even in a megabit large capacity SRAM. Therefore, the compensation current can be supplied to all the memory cells in the V CH boost circuit. Details of the boosting circuit are described in "Ultra LSI Memory (Baifukan, published in November 1994), p.315". In addition, the on-chip step-up circuit that operates at a very low voltage power supply Vcc of about 1 V is a problem described in "1995 Symposium on VLSI Circuits Digest of Technical Papers, (1995), pp.75-76)". . The threshold voltage of the MOS transistor used in the boosting circuit of this document is about 0.6V, and it is considered that a boost circuit that operates even at a lower supply voltage Vcc can be obtained by using a MOS transistor having a lower threshold voltage. When using a transistor having a low threshold voltage, attention must be paid to the subthreshold current described above. However, if the number of transistors is sufficient to form a boosting circuit, it is possible to prevent the leakage current from being practically unusable. A circuit configuration in which a boost circuit that generates a boost voltage by an external supply power supply is connected to a feed node on the high potential side of a memory cell of an SRAM is described in Japanese Patent Application Laid-Open No. 6-223581. The potential of the boost circuit or an external power supply is connected.

Each data line DL 1 , / DL 1 , DL 2 , / DL 2 in the precharge period deactivated by the SRAM activation signal CE (in this specification, an inverted signal which is a pair of complementary signals is described as / DL 1 ). Is precharged to Vcc / 2 by the precharge circuit PC, so that the voltage amplitude of the data line is halved compared with the conventional Vcc precharge. In this case, the Vcc / 2 power supply is formed by the voltage conversion circuit VC1 at Vcc, and specifically, the circuit described in Fig. 4.60 of p.324 of the above-described "ultra-LSI memory". Since the Vcc / 2 is formed inside the chip, the load current driving capability is generally low, so when precharging, the Vcc / 2 power supply directly frees one side of the data pair from 0 to Vcc / 2. If you charge The level of Vcc / 2 fluctuates because a sufficient charge current cannot be supplied, and this fluctuation is particularly problematic since the number of data pairs is usually 64 or 128 or more, so an amplifier AMP is provided for each data line. The amplifier AMP's role is to amplify the micro-differential voltage at the time of cell read indicated by the data pair at high speed to Vcc, so that one side of the data pair becomes 0 and the other becomes Vcc. Q EQ is turned on and the data pair is automatically equilibrated to Vcc / 2, which eliminates the need for a large charging current to flow through the Vcc / 2 power supply. It is sufficient to allow a small current to flow so as to suppress the level fluctuation gradually due to the leakage current, so that the built-in Vcc / 2 power supply circuit can be used by using the AMP.

Hereinafter, a case in which data is read from a memory cell will be described with reference to FIG. 4. The SRAM is activated by the enable signal CE SRAM, any word line e.g. WL 1 When this is selected, applying a pulse of V CH to WL 1, all cells (MC 1, MC 2) on the WL 1 is activated. The selection signal pulse of this word line is received by the row address signal Ax and is formed by the row address decoder XDEC and driver DRV. If 0 V and 2 V (= V CH ) are stored in the nodes N 1 and N 2 in the cell MC 1 , respectively, Q T1 and Q S1 are conducted, so that the data lines DL 1 gradually discharge toward 0 V. On the other hand, since the gate voltages of Q S2 and Q C2 are almost zero, current flows through Q C2 and Q T2 , and the data line DL 1 rises slightly at 0.5 V (= Vcc / 2). Since it takes time for this minute differential voltage shown on the data pair to become large enough, a pulse is applied to the driving lines SP and SN of the amplifier AMP to amplify the data lines DL 1 and / DL 1 at 0V and 1V, respectively, at high speed. Since the AMP does not determine the SRAM density or the subthreshold current at the cell level, the transistor size in the AMP can be selected larger than that in the cell, and the threshold voltage can be lowered to about 0.2V, thus enabling fast amplification. In addition, the AMP enters the operating state when the memory cell is selected by the amplifier driving circuit SPG. In the non-operating state (standby state), the driving line SP and the SN remain at the same potential, so the subthreshold hold current is problematic. It does not become. The AMP also operates at a data pair voltage of about 0.5V.

The difference voltage of the data pair line amplified sufficiently large as described above is output on the I / O pair line by the read select signal φ R1 of the open decoder decoder YDEC and the driver DRV, and goes to the data output Dout through the read / write buffer circuit RWB. do. Here, Q R1 and Q R2 are circuits for converting the voltage of the data pair line into current. If the threshold voltage of these transistors to the data line voltage of 0.5V DL 1 is not a current flow, the I / O line because 0V, on the other hand / the DL 1 is 1V, the current flows because / I / O lines. Which of the large currents flows can be detected in the RWB in the form of polarity discrimination of the differential current or the differential voltage (resistance R in the figure). When the threshold voltage V T of Q R1 and Q R2 is sufficiently low, for example, 0.2 V, the minute voltage difference before amplification by the amplifier AMP can be detected, so that the speed is as high as that. This is because the mutual conductance increases by one minute to lower V T , allowing a larger current to flow.

In the above read operation (Fig. 4), the node voltage of the memory cell MC 1 will be discussed in detail. If Q P1 or Q P2 is conducted or Q P1 or Q P2 is removed during this operation period, a problem occurs if V CH (2 V) is forcibly applied to the feed line PL 1 or the like. When V CH is an external voltage having a large current driving capability, a large direct current flows in all cells on PL 1 for a period of time while voltage is applied to the word line, resulting in high power. Alternatively, when using the power supply voltage V CH boosted in the chip as in the present embodiment, the current driving capability of the boost circuit is insufficient, so that the level of V CH decreases. For this reason, the storage voltage of the non-selected cells on PL 1 also decreases. Once the voltage across all feed lines has fallen, it takes a long time to recover the level of V CH . This is because the parasitic capacity of the sum of feeders is large. This delays the cycle time of the SRAM. Therefore, when the cell is inactive, all feed lines PL 1 and PL 2 are forcibly set to V CH (2V) by the precharge signal phi P, but each feed line is separated from the V CH generating circuit during the activation period. Each feed line has almost become a floating state, the level of V CH to their parasitic capacitance is maintained. However, when the cell is activated (in this case, a read operation), the cell node N 1 eventually becomes 0 and Q C2 conducts strongly. Sources of the transistors are so connected to the floating voltage of the PL 1 PL 1 is as a result of drop in the V CH, and N 1, N 2 is about to be charged to the high level. However, since N 1 is forcibly fixed to the voltage (0 V) of DL 1 , it remains zero. On the other hand, the gate that is the voltage of WL 1 of Q T2 is 2V, / DL 1 also 1V because Q T2 is conducting, and by the Q C2 until the same voltage of the PL 1 and N 2 N 2 is still charge end PL 1 becomes 1V. Clearly the feeder discharged to 1V is localized. That is, it is PL 1 only and PL 2 corresponding to another non-selected word line is not discharged and remains V CH . In actual memory, there are a large number of feed lines, and since only one of them is discharged, unnecessary charge / discharge power is eliminated, and the feed line to be charged by the built-in V CH generator circuit is localized into one, so the design of the V CH generator circuit is Becomes easy.

The write operation to the cell MC 1 is performed by applying a differential voltage to the common I / O pair line as shown in FIG. Here, the information stored in the MC 1 to costs is then a case of writing the information in the opposite example. Voltages of 1 V and 0 V are applied to the data pairs DL 1 and / DL 1 , respectively, and are applied to the cell nodes N 1 and N 2 as they are. Therefore, the difference voltage 1V is written to the nodes N 1 and N 2 . If the precharge operation is performed by? P after the word line WL 1 is turned off from 2V to 0, the difference voltage 1V of the cell node is amplified to 2V by the amplification action of the cell itself. This is because the voltage of the cell feed line PL 1 is 2V. This high voltage becomes a subsequent information holding voltage. To where the off-WL 1, and also in the write operation, V CH generator is then to minimize the capacity to be charged is not unless the V CH to PL 1.

As described above, the storage information of the other memory cells MC on the selection word line WL 1 is not destroyed by the above operation. The memory cell MC 1 is running a read or write operation I / O pair line while running the transfer of information (data) read operation of the same as in Figure 4, so WL 1 is always applied to the selecting pulse of the MC 2 are MC 2 And data pair DL 2 , / DL 2 is executed. Thus, PL 1 is bakkwieodo from 2V to 1V is applied again in a 2V V CH 2 nodes in the MC 2 is returned to V CH, 0. In addition, the stored information of the memory cells MC 3 and MC 4 on the unselected word line WL 2 has no adverse effect at all. MC 3, MC transistors in the 4, V T is therefore high enough the sub-threshold current is because, so feed line PL 2 small junction leakage current as negligible if high flow, does not flow is the V CH of the pre-charging during maintenance to be.

When the amplitude of the pulse voltage of the selected word line is Vcc, and the maximum value V D that the data line can take is set to Vcc-V T or less, the word voltage does not need to be generated from the boost power supply V CH , and at the time of cell writing, for example. Since the influence of the threshold voltage V T of the transistors Q T1 and Q T2 in the memory cell can be eliminated, the design becomes easy. FIG. 6 shows an embodiment in such a case, in which a circuit diagram is shown in FIG. 6A and a waveform diagram is shown in FIG. 6B. FIG. 6 is an extract of a portion related to the driving method of the memory cell from the entire SRAM of FIG. 3, and the difference compared with FIG. 3 is the precharge circuit PC and the read / write circuit RWB. In this embodiment, the signal level of the word line is taken as 0 V as the reference potential and the power supply potential Vcc, and the feed node at the high potential side of the memory cell at the time of non-selection is V CH (= 2 Vcc) and the feed node at the low potential side of the memory cell. The reference potential was 0V. The precharge potential of the data line is set to a potential which is increased by at least the sensitivity voltage of the memory cell at the reference potential (0V = Vss).

The sensitivity voltage or sensitivity of the memory cell is the minimum potential difference required for inverting the state of the memory cell, which is a flip-flop circuit, for example, by the potential difference applied between DL and / DL in FIG. In order to set the potential difference applied between DL and / DL of the data line as the sensitivity voltage, the precharge potential of the data line may be at least half of this sensitivity voltage. In general, since the sensitivity voltage of the memory cell is smaller than 0.2V, the reference voltage V R is set to 0.2V with a margin here, and the precharge potential of the data line is set to 0.2V. In other words, this embodiment is an example in which the maximum value of the voltage amplitude that the data line can take is lowered to the low voltage V R near the sensitivity voltage of the memory cell itself below V T (0.5 V). Since the voltage amplitude of the data line of the memory cell is minimized, high speed and low power operation are possible. For this purpose, the data pair can be precharged by a step-down power supply consisting of a comparator having Q L1 and V R as reference voltages. The memory voltage of the memory cell can be made sufficiently high at V CH (2V).

Hereinafter, the read operation will be described with reference to FIG. 6B. First, all cell feed lines are precharged to V CH (2V) by the precharge signal phi p. After the end of the precharge, a pulse of amplitude Vcc (1V) is applied to the selection word line WL 1 . In the case where node N 1 in the cell is 0 and N 2 is V CH (2V), for example, Q T1 conducts and data line DL 1 discharges toward 0 at 0.2V. In the other data line / DL 1 , Q T2 is conductive, but Q S2 is non-conductive, so that the charge of the node N 2 is divided into / DL 1 and the data line rises slightly from 0.2V to become υ. This increase is very small because the data line capacity is overwhelmingly larger than the intra-node node capacity. At this time, the voltage of N 2 discharges from 2V to υ. In this way, the differential voltage shown on the data pairs is extracted to the I / O pairs as lead information through the read transistors Q R1 and Q R2 . In order to obtain a large gain, P-channel MOS is used for Q R1 and Q R2 . This series of operations eventually causes PL 1 to fall to υ. However, the next time the precharge operation starts, ν is greater than the sensitivity of the cell itself, so that it is normally amplified to V CH by the cross-linked P-channels MOS Q C1 and Q C2 . If the voltage difference ν between N 2 and N 1 is less than this sensitivity, it may not be amplified normally during precharge, and there is a fear that inverted information is maintained. The write operation is performed by applying a differential voltage of 0.2 V to one of the data pair lines selected from the I / O pair lines and 0 to the other, and setting PL 1 to 2 V by the precharge operation similarly to the read operation. .

FIG. 7 is a diagram showing an embodiment in which a large memory voltage is obtained by pulse driving two power supply nodes of a high potential side and a low potential side of a memory cell during precharge, and FIG. 7A shows a circuit diagram thereof. FIG. 7B shows a waveform diagram thereof. FIG. 7 illustrates a portion of the entire SRAM of FIG. 3 related to a driving method of a memory cell. The difference compared to FIG. 3 is that the potential of the low potential side of the memory cell is changed according to selection / non-selection of the memory. It is. In other words, the low voltage supply node on the low potential side of the memory cell was set to 0 V as the reference potential at the time of non-selection, and the voltage dropped to Vcc / 2 at least by the sensitivity voltage of the memory cell described above. In this embodiment, the signal level of the word line is taken as 0 V as the reference potential and the power supply potential Vcc. The precharge potential of the data line is Vcc / 2, and the feed node at the high potential side of the memory cell at the time of non-selection is V CH (= 2 Vcc). It was set as.

In FIG. 6, the precharge voltage of the data line is a low voltage near 0V, whereas in the present embodiment, it is Vcc / 2. For this reason, the read transistors Q R1 and Q R2 in FIG. 6 can be replaced with an N-channel MOS suitable for high speed operation. In addition, since the two types of amplifiers Q S1 and Q S2 , Q C1 and Q C2 in the cell are activated at the beginning of the precharge, they are amplified at higher speed. Here, assume that V CH = 3V, Vcc = 1.5V, V T = 0.5V, and V R = 0.2V. It is assumed that a Vcc / 2 precharge circuit PC as shown in Fig. 3 is connected to each data pair line. During the precharge period, every data line is 0.75V, PL 1 such that the feed line of the feed line is connected to the N channel MOS in the cell, such as 3V, PL '1 is set to 0V. During the pre-charging period, so Q L2 is blocked by the Q L3, L4 Q is because by the PL 'to 1 to zero. In addition, the two nodes N 1 and N 2 in all the cells are 3V or 0 depending on the stored information. At the end of the precharge, PL 1 remains at 3V. On the other hand, PL ' 1 starts to rise toward Vcc by the resistor R', but when (Vcc / 2) -V R becomes 0.55V, a comparator and Q L2 having (Vcc / 2) -V R as the reference voltage are used. The voltage limiting circuit to be formed operates to suppress further rise. Along with this, for example, the node N 1 on the low voltage side is also 0.55V. Here, R 'is set to a relatively high resistance value in order to suppress power consumption, but it is also possible to substitute a MOS transistor. When the word voltage rises, N 2 is 3V and N 1 is 0.55V, so Q T1 and Q S1 conduct and the data line DL 1 is discharged. Since there is a difference of V R between DL 1 and PL ′ 1 , DL 1 eventually discharges to a voltage of 0.55V of PL ′ 1 . On the other hand, since Q S2 is non-conducting, as described above, the charge of the node N 2 is discharged to / DL 1 through Q T2 , and N 2 and / DL 1 become almost the same voltage 0.75V + υ. This difference voltage shown on the data pairs is extracted to the I / O pairs through selection of the lead circuit connected to each data line. Subsequent precharge causes a difference of nearly 0.2V between nodes N 1 and N 2 to be amplified to 3V at high speed. When PL ' 1 goes to zero, N 1 is 0.55V and N 2 is a voltage slightly higher than 0.75V, so both of Q S1 and Q S2 conduct, and almost 0.2V between N 1 and N 2 The differential voltage is amplified by the cross coupled amplifiers Q S1 and Q S2 . This difference voltage is also amplified by the other cross coupling amplifiers Q C1 and Q C2 . In the example of FIG. 6, in the initial stage of amplification in the cell at the start of precharge, the amplifier composed of Q S1 and Q S2 is non-conducting, and is a little slow because it is amplified only by the amplifier composed of Q C1 and Q C2 . In this example, however, both amplifiers contribute to amplification in the early stages of amplification, which is high speed. Obviously, the write operation may be applied in accordance with write data such as 0.75V on one side of the selected data pair line and 0.55V on the other side. Of course, PL ' 1 is controlled to be 0.55V at the time of cell selection as in the case of read. In this example, since the voltage amplitude of the data line is extremely small, about 0.2, it can be driven by the Vcc / 2 voltage generation circuit built into the chip. Therefore, the amplifier AMP shown in FIG. 3 can be removed in some cases, resulting in a small chip. In addition, since the data pair lines always operate in the vicinity of Vcc / 2, the stress voltage to the transistors for the precharge circuit and the read circuits Q R1 and Q R2 on each data line is reduced by half so that the reliability is improved. In addition, the precharge voltage of the data line need not necessarily be Vcc / 2. Clearly, the precharge voltage of the data line may be set higher than the sensitivity of the in-cell amplifier with respect to the PL ' 1 voltage at the time of selection.

In this embodiment, an example is described in which a power supply circuit comprising Q L2 , Q L3 and a comparator is connected to each of the source driving lines PL '(PL' 1 , PL ' 2 ) of an N-channel MOS in a cell. This is to speed up the access time by increasing the time to raise PL ' 1 to 0.55V. However, in order to reduce the chip area, this circuit can be shared with other feed lines as shown in FIG. During the precharge period, the common feed line PLC is always fixed at (Vcc / 2) -V R by the common power supply circuit, but all feed lines PL ' 1 ... PL'n are zero. Here, when PL ' 1 is selected, it is decoded by an external address, φ X1 becomes 0, and PL' 1 is separated from the PLC. After that, / φ P becomes Vcc and discharges PL 1 to zero.

Fig. 9 shows an example of application to the driving method in which the voltage of the data line takes a value near Vcc at the time of reading. FIG. 9 is a part of the entire SRAM of FIG. 3 that is related to the driving method of the memory cell. The difference between FIG. 3 is the precharge circuit PC and the read / write control circuit RWC. In this embodiment, the signal level of the word line is taken as the reference potential 0 V and the power supply potential Vcc. The power supply node of the high shrinkage of the memory cell at the time of non-selection is V CH (= 2 Vcc), and the power supply node of the low potential side of the memory cell is referred to. It set to 0V which is electric potential. In addition, the precharge potential of the data line was set to Vcc.

Each data line is connected to transistors Q D1 and Q D2 that are loaded to the selected cell and a transistor Q EQ that balances the data pair voltage. These circuits are the precharge circuit PC of this embodiment. The operation will be described below using the read operation timing of FIG.

In the precharge period, the data pair is Vcc (1V), and PL 1 is VCH (2V). Here, it is assumed that the data pair lines DL 1 and / DL 1 are opened by the selection signal φ RW1RW1 is 1 V to 0 V), and the word line WL 1 is selected so that a pulse of 0 V to 1 V is applied. If N 2 is 2V, a DC current flows between Q D1 , Q T1 , and Q S1 , and as a result, a small recipe voltage Vs (about 0.2 V) appears in DL 1 . On the other hand, since N 1 is approximately 0, Q S2 is non-conducting, and Q T2 is also non-conducting as is apparent in the voltage relationship, no current flows in the paths of Q D2 , Q T2 and Q S2 . This is because the voltage of N 1 rises slightly due to the recipe operation, but it is because the size of the transistor in the cell is designed to be less than or equal to V T. Therefore, a differential signal equal to Vss appears on the data pair line. Since this voltage is a recipe voltage, the voltage is transmitted to the I / O pair without being passed through the complex lead circuit as shown in FIG. Here, since Q S2 and Q T2 are always non-conducting, the charge accumulated at the node of N 2 is not lost. In other words, the voltage of PL 1 is in the state of 2V. Therefore, even if the current driving capability of the V CH boosting circuit built into the chip does not have much current, current does not flow to PL 1 serving as the load, so that it is also possible to remove Q P1 and connect it directly in some cases. However, this is possible only in the read operation. This becomes difficult in the write operation according to FIG. 11.

When the I / O line pairs in one data pair DL 1 to 1V, the write operation is executed, such as 0V to the other side / DL 1 node N 1 in the cell is from about 0 to 0.5V by then. This is because the threshold voltage of Q T1 is 0.5 V and the voltage of WL 1 is 1 V, so that the voltage dropped by the threshold voltage becomes the voltage of N 1 . On the other hand, N 2 becomes 0 at 2V until then. This is because Q T2 conducts and N 2 discharges to be equal to the voltage of / DL 1 . For this reason, Q C1 becomes stronger in conduction compared with Q C2 , and the floating state PL 1 is forcibly discharged to 0.5 V applied to N 1 in the data line. Therefore, the PL 1 must be charged again to 2V by the subsequent precharge.

If the voltage drop of PL 1 is large, the burden of the boost circuit is increased because the voltage corresponding to the boost voltage (V CH ) generation circuit must be supplied to PL 1 . For this reason, the area of the V CH generating circuit itself becomes large or power consumption increases. 12 is a load circuit for suppressing the voltage drop to near Vcc. In Fig. 12 (a), Q P is made non-conductive in the time zone when the cell is selected, and Q R is made conductive instead. Since the voltage of the feed line is from V CH to Vcc, one of the nodes in the cell (for example, N 1 ) is suppressed to Vcc (1V) without dropping to 0.5V as shown in FIG. 11. In Fig. 12B, the precharge pulse / φ P is removed to simplify the design. N-channel MOS Q R, which has a threshold voltage of about 0.2 V, is lower than that of other transistors. Since the diode is connected, when the voltage of the feed line becomes Vcc-V T, that is, 0.8 V or less, conduction is conducted, so that a voltage drop below that can be prevented. That is, one of the cell nodes is suppressed to 0.8V without dropping to 0.5V as shown in FIG. The Q R of this transistor serves to prevent the voltage level of PL 1 in the floating state from being excessively lowered due to the diffusion layer leakage current in the cell when Q P is the timing of pulse timing off. Also

Assuming that the voltages of FIGS. 10 and 11 are applied, the word lines WL 1 , WL 2 and the feed lines PL 1 , PL 2 are arranged orthogonally as shown in FIG. Can also be taken. For example, when the cells on WL 1 are read, all of their cells perform the same operation as in FIG. 10, so that the voltage V CH levels of all the feed lines do not change. However, in the write operation, only the feed line belonging to the selected data pair line changes. For example, if a pulse voltage of a combination of 1 V and 0 corresponding to write information is applied to the data pairs DL 1 and / DL 1 (which are omitted in the drawing), the cell MC 1 performs the same operation as in FIG. The voltage of PL 1 drops from 2V to 0.5V. Since the cell MC 2 performs the same operation as that of FIG. 10, the voltage V CH of the PL 2 does not change. Whether the arrangement of the word line and the feed line is parallel or orthogonal depends on the layout and area of the cell. In Fig. 9, since the feed line and the data pair line cross each other, there is a drawback to be laid out in another wiring layer, but there is an advantage of low noise. For example, consider a case where a large voltage change occurs in PL 1 because a pulse is applied to WL 1 and cell MC 1 is written. At this time, since the read operation is effectively performed for the cell MC 2 , the signal is shown on the data pair lines DL 2 and / DL 2 . Because this signal is small, the operation of MC 2 is susceptible to noise. However, the data-pair, so it perpendicular to the PL 1, the noise which the voltage changes in the PL 1 occurs via the binding capacity would have been offset On data pairs. FIG. 13 is the opposite of understanding in FIG. 9. For example, differential noise occurs in adjacent data pairs DL 2 and / DL 2 due to the voltage variation of PL 1 . In this case, however, noise can be canceled by intersecting the data pairs in the middle, as is well known in dynamic memories.

In the above embodiments, it is assumed that V CH is generated from a power supply boosted by Vcc in the chip. This is to realize a Vcc single power supply operation that is easy for the user to use. However, in some cases, V CH may be an external chip power supply itself. For example, as shown in FIG. 14, the case of the external two power supplies Vcc1 and Vcc2 is considered. The chip consists of an input / output interface circuit INTF, a core CORE such as a static memory SRAM, an arithmetic circuit (for example, a microprocessor MPU), and the like. INTF operates relatively large devices at relatively high voltages (Vcc1) to ensure the existing logic interface levels. On the other hand, CORE determines chip performance (speed, power) or chip area, so the main part of this part is high performance using micro devices that operate at low voltage (Vcc2). Devices in CORE are generally finer than devices in INTF. In such a chip, Vcc1 may be regarded as V CH in the above embodiments. By doing so, the entire chip is operated by two power sources, but the problem of output level fluctuation due to the internal power supply operation is eliminated and the design becomes easy. FIG. 15 shows an example of application to a chip in which FIG. In the chip operated by the internal power source Vcc2 which stepped down the external single power source Vcc1, it is sufficient to consider Vcc1 as V CH in the above embodiments.

In the above embodiment, the memory cell has been assumed to be a CMOS type. However, in the present invention, since the differential amplifier function in the memory cell is applied, at least one latch-type amplifier coupled to the memory cell may be used. Instead of the P-channel MOSs Q C1 and Q C2 , a well-known high resistance polysilicon load or the like may be used. This is because the nodes N 1 and N 2 can be raised toward the V CH so that they can be amplified in the cross-linked N-channel MOSs Q S1 and Q S2 . In addition, the V T of the N-channel transfer transistors Q T1 and Q T2 having the transfer (transfer) function in the memory cell may be lower than V T of the other transistors in the memory cell, for example, 0.2. At the time of selection, the effective gate voltage of Q T1 and Q T2 is increased and the drive current is increased by one minute to lower V T , thereby enabling high-speed operation. However, since the subthreshold current flows through Q T1 or Q T2 at the time of non-selection, in order to eliminate this, the gates of the word lines in the non-select state, that is, Q T1 and Q T2 , are negative voltages from 0 until now. It must be biased to be deeper than 0.2V. If the gate voltage and the source voltage are set to V G and V S , respectively, the effective gate voltage at the non-selection of Q T1 or Q T2 becomes V G -V S -V T , but V G , V S and V T are -0.2, respectively. At V or less and 0 and 0.2V, this effective gate voltage is -0.4V or less. On the other hand, the sub-thread when the minimum value of V in the hold current to bypass the rest T in the effective gate voltage of 0.4V to 0.4V transistors having the V T in a normal bias condition V G, V S, V T are each 0, 0, 0.4V, so -0.4V. Therefore, in the combination of the low V T and the negative voltage gate described above, the lower effective gate voltage is applied, so that the subthreshold current does not flow. In this case, the selection word voltage becomes a pulse rising from V-0.2V or higher at -0.2V in the non-selection state.

In addition, although it is assumed that the V T of the P-channel and N-channel transistors in the memory cell is equal to 0.5V, it is not necessary to do so. N-channel transistors because it is important to determine the transistor such as the lead current to the data line, the V T is, for example, possible low V T of about not a sub-threshold current is a problem to be 0.4V. However, since the main role of the P-channel transistor is to charge the microcapacity in the memory cell, even if the speed is somewhat low, the absolute value may be set to 0.4V or more, for example, 0.6V. In addition, for simplifying V CH it is assumed that came to twice the V CH Vcc may, for example, withstand voltage of the transistor is less than a gate breakdown voltage Vcc.

There is also a method of charging a feed line at a high speed while increasing the sensitivity in the memory cell. As described above, a circuit in which a transistor is cross-coupled in a memory cell can be regarded as a differential amplifier, but in addition to the offset voltage, the capacitance difference between the nodes N 1 and N 2 also affects the sensitivity of the differential amplifier. Depending on the layout of the memory cells, if the density is prioritized, a difference in capacity may occur. However, if the value is large, the sensitivity is deteriorated. That is, just before amplification, a larger voltage difference is needed between the nodes N 1 and N 2 . The sensitivity due to this capacitance difference becomes worse as the speed of raising the feed line (for example, PL 1 ) to V CH increases. This problem can be solved by two-stage amplification as shown in FIG. That is, two transistors having substantially different channel widths (for example, 10 times) are connected in parallel to each of the feed lines (PL 1 and the like). First, by applying φ P , conducting transistor Q P1 having a small channel width, charging the feed line little by little, amplifying the node N 1 , N 2 to an arbitrary large voltage difference, and then applying φ ' P to increase the channel width. The large transistor Q ' P1 is turned on to charge at high speed.

17 is a cross-sectional view of an embodiment of the present invention. As shown in this embodiment, the switch MOS Q P and the PMOS transistor of the memory cell are formed in the n well, but the source or drain electrode of each transistor is increased to V CH so that the potential of the well is V CH. It is necessary to keep it. At this time, when the potential of the n well forming the PMOS transistor of the peripheral circuit is Vcc, the substrate may be p-type.

18 is a cross-sectional view of another embodiment of the present invention. In this embodiment, since the large voltage V CH is applied to the switch MOS and the PMOS transistors of the memory cell, the breakdown voltage is increased by making the gate oxide films of these MOS thicker than the peripheral circuits. Since the MOS transistor of the peripheral circuit is thin in the oxide film thickness, there is an effect that the transconductance is increased and it can operate at high speed.

19 is a cross-sectional view of another embodiment of the present invention. In this embodiment, as shown in Fig. 1A, the switch MOS and the PMOS of the memory cell are not separated as in the case where the switch MOS is attached to each memory cell. In such a case, the wells forming both MOS transistors may be set at the potential of V CH .

20 is a cross-sectional view of another embodiment of the present invention, in which the present invention is formed on an N-type substrate. When the present invention is applied on an N-type substrate, the peripheral circuit, the switch MOS, and the PMOS of the memory cell cannot be separated. Therefore, as described in the present embodiment, a common deep P well may be formed in the switch MOS and the PMOS of the memory cell, and an N well may be formed therein to change the peripheral circuit and the potential.

In order to maximize the advantages of the present invention, it is desirable to further study the memory array and peripheral circuits. Fig. 21 is an embodiment of the present invention applied to an SRAM portion of a chip or an SRAM of one chip. The memory portion is divided into a plurality of memory arrays MA 1 , MA 2 ,... The global word line is connected across a plurality of memory arrays. In the memory array, the sub-word lines (WL 11 ..., WL n1, WL 12, ..., WL n2, ...) one in direction m, the data line direction (DL 11, / DL 11, ..., DL 12, / DL 12, ... m ... n m m n n plurality of memory cells MC arranged in matrix. The sub feeder lines PL 11 ,... Where the boost voltage V CH is applied to the feeder node to the high potential side of the plurality of memory cells via the switch MOS transistors Q PL11 ,..., Q PLn1 , Q PL12 ,..., Q PLn2,. , PL n1 , PL 12 ,..., PL n2 , ... are connected to each other in pairs with the above-described subword lines. Note that the subword line can be read only by changing the word line in correspondence with the above-described embodiment.

Where, V T of the MOS transistor (Q C1, Q C2, Q S1, Q S2) of forming a memory cell in the memory cell MC as shown in Figure 22 in the way to Figure 9 the base is 0.5V, the transfer MOS V T of the transistors Q T1 and Q T2 is set to 0.2V. In other words, the MOS transistors included in the memory cells are set to a threshold voltage at which the subthreshold current does not become a problem as the whole SRAM, whereas the transfer MOS transistor is set to a threshold voltage which requires attention. The power supply Vcc supplied externally to this SRAM is 1 V, and the boost voltage V CH formed in the voltage conversion circuit VC2 at this Vcc is 2 V (= 2 Vcc), and similarly, the negative voltage -V WB formed at the voltage conversion circuit V3 at Vcc is 0.2. It was set to V.

For example, in order to select one subword line WL 11 , that is, to apply a cell activation pulse rising to Vcc (1V) from the above-described negative voltage-V WB (eg, -0.2V) to WL 11 , the global word line It is sufficient to select GL 1 and the control line R X1 by the address signal. In order to select R X1 , the memory array selection signal φ sr1, which is formed using YDEC, DRV, and the timing control circuit TC, is a signal for substantially selecting the memory array MA1 is used. That is, the pulse applied to the GL 1 for applying a pulse that rises to Vcc at -V by the WB LCB receives the φ sr1 in R X1 and raised to -V WB from Vcc by another LCB level converter which is connected to GL 1 Do it. The global word line GL 1 is selected by the row address decoder, the driver XDEC, and the DRV in the row address Ax. At this time, other GL lines (global word lines) and other Rx lines remain Vcc and -V WB , respectively. On the other hand, in the switch MOS selection signal groups φ P1 , φ P2 ..., only φ P1 becomes a pulse rising from 0 to V CH by another level converter LCA, and otherwise it remains at 0V. Thus, PL 11 . , The switch MOS connected to PL n1 is turned off, and the corresponding switch MOS group of the unselected memory array remains on. In order to rise to V CH to φ P1 from 0V YDEC, is formed by using the timing control circuit TC and DRV 2, it is substantially the selection signal for selecting the memory array to the memory array MA1 signal φ sp1 is used. In this way, the group of memory cells MC on the WL 11 is activated and operates as described above.

Here, Q ' D1 and Q' D2 on each data pair line are acceleration transistors for precharging the voltage of the data pair line to Vcc at high speed. Further, RWC has a read / write circuit selected by the column selection signal lead (φ RY1) similar to that of Figure 3, using a low V T both to the speed. Further, in order to execute the write operation from the I / O line to the data line at high speed, the N-channel and P-channel MOS selected by the column write selection signals φ WY1 and / φ WY1 are connected in parallel.

By dividing / partly driving the word line and the feed line as described above, the burden on the generation circuit of the built-in V CH or -V WB can be reduced, and a single power supply design becomes easier. This is because the voltage fluctuates depending on the operation, so that the feed line or word line that must feed V CH or -V WB is localized to the sub feed line subword line WL 11 . In this embodiment, one switch MOS may be added to each feed line, so the area increase due to division is small. However, for example, since φ P1 is a high voltage (V CH ) pulse, the power for charging and discharging the gate capacitance of the plurality of switch MOSs connected to this line becomes relatively large.

FIG. 23 calculates the operating voltage margin of the memory cell of FIG. In the figure, the horizontal axis represents the power supply voltage Vcc supplied from the outside, and the vertical axis represents the time from when the word line WL is selected (0 V to Vcc) until the potential difference of the / DL reaches 100 mV. The defined signal rise time τ is shown. The smaller the signal rise time τ is, the better. In the memory cell of Fig. 22, all six MOS transistors have the same threshold voltage V T == 0.75 V, and the source power supply node (high power supply node of the memory cell) of Q C1 and Q C2 is supplied with a power supply voltage. The characteristics of a conventional memory cell connected directly to Vcc are shown. In this conventional configuration, since the V T of the MOS transistor is large, the subthreshold current is not substantially a problem. However, in the conventional configuration, it can be seen that when the power supply voltage is 0.8 V or less, the signal rise time tau rapidly increases and practically does not operate. That is, when the threshold voltage V T less than the power supply voltage Vcc MOS transistor is used, due to the increase in the rise time τ is not the memory cell is not substantially operated.

On the other hand, when the memory cell of Fig. 22 of the present application is used, it operates to a lower power supply voltage. The curve shown by the present invention of FIG. 23 sets the threshold voltages of Q C1 , Q C2 , Q S1 and Q S2 constituting the memory cells in the memory cells of FIG. 22 to 0.75 V, and the thresholds of the transfer MOS transistors Q T1 and Q T2 . The voltage was calculated at 0.2V. Incidentally, the boosted voltage V CH is calculated for two cases of 2 Vcc and 3 Vcc, and the calculation points are indicated by circles (circle) and square (□), respectively. In this example, it can be seen that even when the power supply voltage falls below the threshold voltage of the MOS transistor of the memory cell, it operates at τ = 10 ns and operates to about 0.5 V. That is, according to the present application, although the threshold voltage of the MOS transistor of the memory cell cannot be lower than a predetermined value (for example, 0.5V) due to the limitation of the subthreshold current, the SRAM of the SRAM operating below the threshold voltage A construction method was obtained. In Fig. 22, since the threshold voltages of Q T1 and Q T2 are set to 0.2 V, which is a problem for the subthreshold current, Q T1 when the memory cell is in an unselected state with the signal level on the low potential side of the word line as -V WB . and a sub-threshold current in Q T2 was does not flow. In order to prevent the subthreshold current from being a problem for Q T1 and Q T2 , for example, when a MOS transistor with a threshold voltage of 0.5 V is used, the signal level on the high potential side of the word line may be sufficiently increased to increase its driving capability. . Sufficient low-voltage operation is possible if V T such as the load MOS on the data line or the MOS in the read / write control circuit RWC shown in Fig. 21 is sufficiently small (for example, 0.2 V or less). Other peripheral drive / logic circuit is effective at sufficiently low Vcc that is sufficiently low V T by using the sub-threshold current reduction circuit as described in the aforementioned book "ultra LSI memory". Thus, the cell chip as a whole will operate in Vcc of the V T less than the cross-coupled MOS.

The present application is particularly advantageous for devices operating at low supply voltages, such as batteries. That is, although the power supply voltage of the solar cell is about 0.5V, the SRAM is finally made to operate in this solar cell. In addition, since the voltage can be reduced, the effect of reducing power consumption is remarkable.

Fig. 24 shows another embodiment for the purpose of lowering the power even though the area is slightly larger. For simplicity, only portions of WL 11 and PL 11 in FIG. 21 are extracted. The MOS transistors PL 11 to PL n1 for switching (switching) V CH in FIG. 21 are simultaneously controlled by one signal φ P1 , whereas in FIG. 24, a level converter for controlling the switch MOS and its gate is provided for each divided feed line. Added. For example, when WL 11 is selected and an active pulse is applied, the gate of Q PL1 goes from 0 to V CH and Q PL1 is turned off. Therefore, the gate capacitance driven at the high voltage V CH becomes one, resulting in low power. At this time, the gate of the other switch MOS is in a state of zero.

As apparent from the above-described embodiment, the present invention achieves the effect of realizing a semiconductor device incorporating a high-speed static memory cell having a wide voltage margin even in low voltage operation without increasing the current consumption.

1 is a view illustrating a concept of the present invention for controlling a feeder line voltage of a static memory cell;

2 is a view of a conventional static memory cell and its operation waveform;

3 is an embodiment applied to a static memory cell array,

4 is a timing diagram of a read operation of FIG. 3;

5 is a timing diagram of the write operation of FIG. 3;

6 is an embodiment applied to a static memory cell array,

7 is an embodiment applied to a static memory cell array,

8 is an embodiment sharing a power supply circuit for power supply,

9 is an embodiment applied to a static memory cell array,

10 is a timing diagram of the read operation of FIG. 9;

11 is a timing diagram of the write operation of FIG. 9;

12 is a voltage drop prevention circuit diagram of a feed line;

13 illustrates an embodiment in which a feed line and a word line are orthogonal to each other;

14 is an application example to an external two power supply chip,

15 is an application example to an external single power supply chip,

16 is an embodiment of a drive system of a feeder line,

17 is a cross-sectional view of an embodiment of the present invention;

18 is a cross-sectional view of another embodiment of the present invention;

19 is a cross-sectional view of another embodiment of the present invention;

20 is a cross-sectional view of another embodiment of the present invention;

21 illustrates an embodiment applied to a divided memory cell array;

FIG. 22 is an embodiment of an internal circuit of the memory cell of FIG. 21;

FIG. 23 is a characteristic diagram of an embodiment of the memory cell of FIG. 22;

24 is an embodiment of a driving method of a divided feeder.

[Description of the code]

Q C1 , Q C2 , Q T1 , Q T2 , Q S1 , Q S2 ‥‥ Transistor in memory cell,

N 1 , N 2 . Memory nodes in memory cells,

DL, / DL, DL 11 , / DL 11 , DL 12 , / DL 12 ‥‥ Data lines,

WL 1 , WL 2 , WL 11 , WL 12 , WL n1 , WL n2 Word lines,

PL 1 , PL 2 , PL ' 1 , PL' m , PL 11 , PL 12 , PL n1 , PL n2

PLC… Common feeder, MC, MC 1 to MC 4 ‥‥ Memory cell, Vss... Reference potential, Vcc... Power supply voltage, V CH ... Power supply voltage or boosted power supply voltage, Q P1 , Q P2 , Q P , Q ' P1 . Switch transistor, CE… Chip activation signal, PC... Precharge circuit, φ P , / φ ' P , ‥ φ P1 , φ P2 , φ' P1 . Precharge signal, AMP... Amplifier, SP, SN… Amplifier drive line, Q EQ … Balancing transistors,? R1 ,? R2 . Lead selection symbol, φ W1 , φ W2 . Light selection symbol, φ RW1 . Lead / light selection symbol, A X , A Y. Row and column addresses, Din, Dout... Data input and data output, / WE... Write control signal, Q R1 , Q R2 . Lead transistors, Q W1 , Q W2 . Light transistor, SPG… Amplifier Drive Circuit, XDEC, DRV… Row Decoder and Driver, YDEC, DRV… Thermal Decoder and Driver, I / O, / I / O… Data input / output line, RWC ... Lead / light control circuit, RWB… Read / write buffer circuit, Q L1 , Q L2 , Q L3 , Q L4 . Internal voltage control transistor, φ X1 , φ Xn ... Feed line select signal, INTF. I / O interface circuit of chip, CORE. Chip's main circuit, VDC… Built-in step-down circuit, Vcc1, Vcc2... Power supply voltage, VC1, VC2, VC3... Voltage conversion circuit, PCG... Precharge signal generation circuit, LCA, LCB... Level converter, RX1, RX2... Control line, GL1, GLn ... Global word line,? RY1 ... Column lead select signal ,? WY1 , /? WY1 . Column light selection signal, Q PL1 , Q PL2 . Switch transistor, V WB . Word line bias voltage, MA1, MA2... Memory array,? Sr1,? Sr2,... Memory array select signal,? Sp1,? Sp2... Memory array select signal, TC1, TC2... Timing control circuits GA11, GAn1, GA12, GAn2... NAND gate.

Claims (36)

  1. A semiconductor device using a static memory cell having a MOS transistor whose gate and drain are cross-coupled with each other,
    The cross-coupled MOS transistors are configured such that substantially no current flows between the drain and the source even when the voltages of the gate and the source are the same.
    The feed node of the static memory cell is connected to the first power supply voltage via a switch,
    In the selected state of the static memory cell, the switch is made non-conductive,
    In the non-selection state of the static memory cell, the switch is turned on,
    And said first power supply voltage is greater than a maximum voltage of a data line.
  2. The method of claim 1,
    And a feed node of a plurality of said static memory cells is commonly connected to said switch.
  3. The method of claim 1,
    And the maximum voltage of the data line is determined by a second power supply voltage, wherein the first power supply voltage is generated by boosting the second power supply voltage in a chip.
  4. The method of claim 3,
    And a power supply voltage lower than a threshold voltage of a MOS transistor forming a memory cell in said static memory cell.
  5. The method of claim 1,
    The switch is a MOS transistor, and at least the potential of the well of the first conductivity type forming the MOS transistor and the well of the well of the first conductivity type forming the static memory cell are connected to the first power supply voltage. A semiconductor device characterized by the above-mentioned.
  6. The method of claim 4, wherein
    And the gate insulating film of the MOS transistor forming the switch and the static memory cell is thicker than the gate insulating film of the MOS transistor of the peripheral circuit.
  7. The method of claim 1,
    And a threshold voltage of the transfer MOS transistor in the static memory cell is smaller than the threshold voltage of the MOS transistor forming the memory cell.
  8. The method of claim 1,
    And said switch controls conduction and non-conduction in synchronism with the active timing of a word line.
  9. The method of claim 1,
    And a voltage level control means provided on a power supply line shared by a plurality of static memory cells to feed the first power supply voltage.
  10. A semiconductor device operable by a power supply generating a voltage between a reference potential and a first potential, the semiconductor device comprising:
    Static memory cells;
    A word line connected to the static memory cell;
    A data line connected to the static memory cell;
    A voltage conversion circuit which receives the power supply and generates a second potential having a voltage higher than the first potential;
    A switch connected between a feed node on the high potential side of the static memory cell and the second potential,
    And the switch is turned off when the word line is brought into a selected state.
  11. The method of claim 10,
    The semiconductor device includes a second voltage conversion circuit that receives the power source and generates a third potential that is a half of the first potential,
    A feed node on the low potential side of the static memory cell is connected to the reference potential,
    The data line becomes the third potential when the static memory cell is in an unselected state,
    And said word line has a signal level at said reference potential or said second potential.
  12. The method of claim 10,
    The semiconductor device includes a second voltage conversion circuit that receives the power source and generates a third potential greater than the sensitivity voltage of the static memory cell.
    A feed node on the low potential side of the static memory cell is connected to the reference potential,
    The data line becomes the third potential when the static memory cell is in an unselected state,
    And said word line has a signal level at said reference potential or said first potential.
  13. The method of claim 10,
    The semiconductor device includes a second voltage conversion circuit that receives the power source and generates a third potential that is a half of the first potential;
    A third voltage conversion circuit for generating a fourth potential at the second potential, the fourth potential being as small as the sensitivity voltage of the static memory cell,
    The feed node on the low potential side of the static memory cell becomes the reference potential when the word line is in the unselected state, and becomes the fourth potential when the word line is in the selected state,
    The data line becomes the third potential when the static memory cell is in an unselected state,
    And said word line has a signal level at said reference potential or said first potential.
  14. The method of claim 10,
    A feed node on the low potential side of the static memory cell is connected to the reference potential,
    The data line becomes the first potential when the static memory cell is in an unselected state,
    And said word line has a signal level at said reference potential or said first potential.
  15. The method of claim 10,
    The static memory cell includes first and second inverters having one output connected to an input of the other, a first MOS transistor having one end connected to an input of the first inverter, and one end thereof being the first one. Has a second MOS transistor connected to the output of the inverter,
    And the first and second MOS transistors have a threshold voltage smaller than the threshold voltage of the MOS transistors included in the first and second inverters.
  16. The method of claim 15,
    The semiconductor device includes a second voltage conversion circuit configured to receive the power and generate a third potential lower than the reference voltage.
    Feed nodes on the low potential side of the first and second inverters are connected to the reference potential,
    The data line becomes the first potential when the static memory cell is in an unselected state,
    And said word line has a signal level at said third potential or said first potential.
  17. The method of claim 10,
    The switch is a MOS transistor, and the first well of the first conductivity type forming the MOS transistor of the switch and the second well of the first conductivity type forming the MOS transistor of the static memory cell are connected to the first potential. The semiconductor device characterized by the above-mentioned.
  18. The method of claim 17,
    And the gate insulating film of the MOS transistor forming the switch and the static memory cell is thicker than the gate insulating film of the transistor of the peripheral circuit.
  19. A semiconductor device operable by a power supply generating a voltage between a reference potential and a first potential, the semiconductor device comprising:
    A plurality of memory arrays;
    A voltage conversion circuit which receives the power supply and generates a second potential having a voltage greater than the first potential;
    A global word line extending over said plurality of memory arrays,
    The memory array is
    A plurality of static memory cells arranged in a matrix in a first direction and a second direction that are substantially orthogonal;
    A sub feed line extending in the first direction and connected to a feed node on a high potential side of the plurality of static memory cells in the first direction,
    A switch connected between the sub feed line and the second potential,
    A word line extending in the first direction and connected to a plurality of static memory cells in the first direction, the word line being selected corresponding to the global word line;
    A data line extending in the second direction and connected to the plurality of static memory cells in the second direction,
    And the switch is turned off when the word line is brought into a selected state.
  20. The method of claim 19,
    The semiconductor device includes a second voltage conversion circuit that receives the power source and generates a third potential that is a half of the first potential,
    A feed node on the low potential side of the static memory cell is connected to the reference potential,
    The data line becomes the third potential when the static memory cell is in an unselected state,
    And said word line has a signal level at said reference potential or said second potential.
  21. The method of claim 19,
    The semiconductor device includes a second voltage conversion circuit that receives the power source and generates a third potential greater than the sensitivity voltage of the static memory cell.
    A feed node on the low potential side of the static memory cell is connected to the reference potential,
    The data line becomes the third potential when the static memory cell is in an unselected state,
    And said word line has a signal level at said reference potential or said first potential.
  22. The method of claim 19,
    The semiconductor device includes a second voltage conversion circuit that receives the power source and generates a third potential that is a half of the first potential;
    A third voltage conversion circuit for generating a fourth potential at the second potential, the fourth potential being as small as the sensitivity voltage of the static memory cell,
    The feed node on the low potential side of the static memory cell becomes the reference potential when the word line is in the unselected state and becomes the fourth potential when the word line is in the selected state,
    The data line becomes the third potential when the static memory cell is in an unselected state,
    And said word line has a signal level at said reference potential or said first potential.
  23. The method of claim 19,
    A feed node on the low potential side of the static memory cell is connected to the reference potential,
    The data line becomes the first potential when the static memory cell is in an unselected state,
    And said word line has a signal level at said reference potential or said first potential.
  24. The method of claim 19,
    The static memory cell includes first and second inverters having one output connected to an input of the other, a first MOS transistor having one end connected to an input of the first inverter, and one end thereof being the first one. Has a second MOS transistor connected to the output of the inverter,
    And the first and second MOS transistors have threshold voltages lower than the threshold voltages of the MOS transistors included in the first and second inverters.
  25. The method of claim 24,
    The semiconductor device includes a second voltage conversion circuit configured to receive the power and generate a third potential lower than the reference voltage.
    Feed nodes on the low potential side of the first and second inverters are connected to the reference potential,
    The data line becomes the first potential when the static memory cell is in an unselected state,
    And said word line has a signal level at said third potential or said first potential.
  26. The method of claim 19,
    The switch is a MOS transistor, and the first well of the first conductivity type forming the MOS transistor of the switch and the second well of the first conductivity type forming the MOS transistor of the static memory cell are connected to the first potential. The semiconductor device characterized by the above-mentioned.
  27. The method of claim 26,
    And the gate insulating film of the MOS transistor forming the switch and the static memory cell is thicker than the gate insulating film of the transistor of the peripheral circuit.
  28. A semiconductor device operable by a power supply generating a voltage between a reference potential and a first potential, the semiconductor device comprising:
    First and second inverters whose one output is connected to the input of the other, the first MOS transistor whose one end is connected to the input of the first inverter, and one end thereof, are connected to the output of the first inverter. A static memory cell having a second MOS transistor;
    A word line connected to gates of the first and second MOS transistors;
    A pair of complementary data lines connected to the other ends of each of the first and second MOS transistors;
    A voltage conversion circuit which receives the power supply and generates a second potential having a voltage higher than the first potential;
    A switch connected between a feed node on the high potential side of the first and second inverters and the second potential,
    And the first and second MOS transistors have threshold voltages lower than the threshold voltages of the MOS transistors included in the first and second inverters.
  29. The method of claim 28,
    The semiconductor device includes a second voltage conversion circuit configured to receive the power and generate a third potential smaller than the reference voltage.
    Feed nodes on the low potential side of the first and second inverters are connected to the reference potential,
    The pair of complementary data lines become the first potential when the static memory cell is in an unselected state,
    And said word line has a signal level at said third potential or said first potential.
  30. The method of claim 29,
    The switch is a MOS transistor, and the well of the first conductivity type forming the MOS transistor of the switch and the well of the first conductivity type forming the MOS transistor of the static memory cell are connected to the first potential. A semiconductor device.
  31. The method of claim 30,
    And the gate insulating film of the MOS transistor forming the switch and the static memory cell is thicker than the gate insulating film of the transistor of the peripheral circuit.
  32. A semiconductor device operable by a power supply generating a voltage between a reference potential and a first potential, the semiconductor device comprising:
    First and second inverters whose one output is connected to the input of the other, the first MOS transistor whose one end is connected to the input of the first inverter, and one end thereof, are connected to the output of the first inverter. A static memory cell having a second MOS transistor;
    A word line connected to gates of the first and second MOS transistors;
    A pair of complementary data lines connected to the other ends of each of the first and second MOS transistors;
    A voltage conversion circuit which receives the power supply and generates a second potential having a voltage higher than the first potential;
    A switch connected between a feed node on the high potential side of the first and second inverters and the second potential,
    And the difference between the reference potential and the first potential is lower than a threshold voltage of the MOS transistors included in the first and second inverters.
  33. 33. The method of claim 32,
    And the first and second MOS transistors have threshold voltages lower than the threshold voltages of the MOS transistors included in the first and second inverters.
  34. The method of claim 33, wherein
    The semiconductor device includes a second voltage conversion circuit configured to receive the power and generate a third potential smaller than the reference voltage.
    Feed nodes on the low potential side of the first and second inverters are connected to the reference potential,
    The pair of complementary data lines become the first potential when the static memory cell is in an unselected state,
    And said word line has a signal level at said third potential or said first potential.
  35. The method of claim 34, wherein
    The switch is a MOS transistor, and the well of the first conductivity type forming the MOS transistor of the switch and the well of the first conductivity type forming the MOS transistor of the static memory cell are connected to the first potential. A semiconductor device.
  36. 36. The method of claim 35 wherein
    And the gate insulating film of the MOS transistor forming the switch and the static memory cell is thicker than the gate insulating film of the transistor of the peripheral circuit.
KR19960018651A 1995-06-02 1996-05-30 Semiconductor device KR100373223B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP95-136349 1995-06-02
JP13634995 1995-06-02
JP02757496A JP4198201B2 (en) 1995-06-02 1996-02-15 Semiconductor device
JP96-027574 1996-02-15

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1020010015077A Division KR100395261B1 (en) 1995-06-02 2001-03-23 Semiconductor device

Publications (1)

Publication Number Publication Date
KR100373223B1 true KR100373223B1 (en) 2003-07-22

Family

ID=26365515

Family Applications (3)

Application Number Title Priority Date Filing Date
KR19960018651A KR100373223B1 (en) 1995-06-02 1996-05-30 Semiconductor device
KR1020010015077A KR100395261B1 (en) 1995-06-02 2001-03-23 Semiconductor device
KR1020030032779A KR100395260B1 (en) 1995-06-02 2003-05-23 Semiconductor device

Family Applications After (2)

Application Number Title Priority Date Filing Date
KR1020010015077A KR100395261B1 (en) 1995-06-02 2001-03-23 Semiconductor device
KR1020030032779A KR100395260B1 (en) 1995-06-02 2003-05-23 Semiconductor device

Country Status (4)

Country Link
US (12) US5668770A (en)
JP (1) JP4198201B2 (en)
KR (3) KR100373223B1 (en)
TW (1) TW302535B (en)

Families Citing this family (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4198201B2 (en) * 1995-06-02 2008-12-17 株式会社ルネサステクノロジ Semiconductor device
US5831910A (en) * 1995-08-18 1998-11-03 Hitachi, Ltd. Semiconductor integrated circuit utilizing overdriven differential amplifiers
JP3560266B2 (en) 1995-08-31 2004-09-02 株式会社ルネサステクノロジ Semiconductor device and semiconductor data device
US6361842B1 (en) 1996-05-30 2002-03-26 United States Brass Corporation Reformed crosslinked polyethylene articles
JPH10188571A (en) * 1996-12-25 1998-07-21 Toshiba Corp Semiconductor memory circuit device, and method for writing into semiconductor memory cell
US6115307A (en) * 1997-05-19 2000-09-05 Micron Technology, Inc. Method and structure for rapid enablement
US6157974A (en) * 1997-12-23 2000-12-05 Lsi Logic Corporation Hot plugging system which precharging data signal pins to the reference voltage that was generated from voltage detected on the operating mode signal conductor in the bus
US5986962A (en) * 1998-07-23 1999-11-16 International Business Machines Corporation Internal shadow latch
JP4030198B2 (en) * 1998-08-11 2008-01-09 株式会社ルネサステクノロジ Manufacturing method of semiconductor integrated circuit device
US6122760A (en) * 1998-08-25 2000-09-19 International Business Machines Corporation Burn in technique for chips containing different types of IC circuitry
US6141240A (en) * 1998-09-17 2000-10-31 Texas Instruments Incorporated Apparatus and method for static random access memory array
US6040991A (en) * 1999-01-04 2000-03-21 International Business Machines Corporation SRAM memory cell having reduced surface area
US6181608B1 (en) * 1999-03-03 2001-01-30 Intel Corporation Dual Vt SRAM cell with bitline leakage control
FR2793064B1 (en) * 1999-04-30 2004-01-02 St Microelectronics Sa Reduced leakage current memory
JP2001167581A (en) * 1999-12-09 2001-06-22 Mitsubishi Electric Corp Semiconductor memory
JP4530464B2 (en) * 2000-03-09 2010-08-25 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit
JP4044721B2 (en) * 2000-08-15 2008-02-06 株式会社ルネサステクノロジ Manufacturing method of semiconductor integrated circuit device
JP5004386B2 (en) * 2000-09-18 2012-08-22 三洋電機株式会社 Display device and driving method thereof
US6529400B1 (en) * 2000-12-15 2003-03-04 Lsi Logic Corporation Source pulsed, dynamic threshold complementary metal oxide semiconductor static RAM cells
DE10104701B4 (en) * 2001-02-02 2014-04-17 Qimonda Ag A method of writing data into a memory of a DRAM and DRAM having a memory
US6946901B2 (en) * 2001-05-22 2005-09-20 The Regents Of The University Of California Low-power high-performance integrated circuit and related methods
JP2003051191A (en) * 2001-05-31 2003-02-21 Mitsubishi Electric Corp Semiconductor memory device
JP5240792B2 (en) * 2001-06-05 2013-07-17 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2002368135A (en) * 2001-06-12 2002-12-20 Hitachi Ltd Semiconductor memory device
JP2003059273A (en) 2001-08-09 2003-02-28 Hitachi Ltd Semiconductor memory
JP2003132683A (en) * 2001-10-23 2003-05-09 Hitachi Ltd Semiconductor device
JP2003151267A (en) * 2001-11-09 2003-05-23 Fujitsu Ltd Semiconductor memory device
JP2003188351A (en) * 2001-12-17 2003-07-04 Hitachi Ltd Semiconductor integrated circuit
US6639827B2 (en) * 2002-03-12 2003-10-28 Intel Corporation Low standby power using shadow storage
US6894356B2 (en) * 2002-03-15 2005-05-17 Integrated Device Technology, Inc. SRAM system having very lightly doped SRAM load transistors for improving SRAM cell stability and method for making the same
CA2479682A1 (en) * 2002-03-27 2003-10-09 The Regents Of The University Of California Low-power high-performance memory cell and related methods
US6724648B2 (en) * 2002-04-05 2004-04-20 Intel Corporation SRAM array with dynamic voltage for reducing active leakage power
TWI283406B (en) * 2002-08-28 2007-07-01 Brilliance Semiconductor Inc Charging-free ultra-low power virtual dynamic random access memory
JP2004158084A (en) 2002-11-05 2004-06-03 Hitachi Ulsi Systems Co Ltd Semiconductor integrated circuit device
US6990011B2 (en) * 2003-05-09 2006-01-24 Stmicroelectronics, Inc. Memory circuit and method for corrupting stored data
US6791886B1 (en) * 2003-05-30 2004-09-14 International Business Machines Corporation SRAM cell with bootstrapped power line
JP4282388B2 (en) * 2003-06-30 2009-06-17 株式会社東芝 Semiconductor memory device
US7224600B2 (en) * 2004-01-08 2007-05-29 Stmicroelectronics, Inc. Tamper memory cell
US6985380B2 (en) * 2004-03-26 2006-01-10 Intel Corporation SRAM with forward body biasing to improve read cell stability
CA2482254A1 (en) * 2004-04-07 2005-10-07 Mold-Masters Limited Modular injection nozzle having a thermal barrier
US20050289017A1 (en) * 2004-05-19 2005-12-29 Efraim Gershom Network transaction system and method
US7349681B2 (en) * 2004-07-13 2008-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Self-biased high-speed receiver
JP4291751B2 (en) * 2004-07-23 2009-07-08 富士通マイクロエレクトロニクス株式会社 Semiconductor memory device
US7196925B1 (en) * 2004-08-26 2007-03-27 Cypress Semiconductor Corporation Memory array with current limiting device for preventing particle induced latch-up
JP4553185B2 (en) * 2004-09-15 2010-09-29 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit device
TWI290717B (en) * 2004-11-08 2007-12-01 Zmos Technology Inc High speed and low power SRAM macro architecture and method
KR100616199B1 (en) * 2004-12-06 2006-08-25 주식회사 하이닉스반도체 Circuit and method for controlling voltage generation in semiconductor memory device
ITVA20050018A1 (en) * 2005-03-15 2006-09-16 St Microelectronics Srl controlled switch
JP4912016B2 (en) 2005-05-23 2012-04-04 ルネサスエレクトロニクス株式会社 Semiconductor memory device
US7355905B2 (en) 2005-07-01 2008-04-08 P.A. Semi, Inc. Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage
JP4917767B2 (en) * 2005-07-01 2012-04-18 パナソニック株式会社 Semiconductor memory device
US7313033B2 (en) * 2005-09-28 2007-12-25 Infineon Technologies Ag Random access memory including first and second voltage sources
JP4929668B2 (en) 2005-10-12 2012-05-09 富士通セミコンダクター株式会社 Semiconductor memory
US8134644B2 (en) * 2005-10-15 2012-03-13 Cooper J Carl Audio synchronizer control and communications method and apparatus
US7554843B1 (en) * 2005-11-04 2009-06-30 Alta Analog, Inc. Serial bus incorporating high voltage programming signals
US20070103195A1 (en) * 2005-11-07 2007-05-10 Jeong Duk-Sohn High speed and low power SRAM macro architecture and method
US7411853B2 (en) * 2005-11-17 2008-08-12 Altera Corporation Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits
JP4865360B2 (en) * 2006-03-01 2012-02-01 パナソニック株式会社 Semiconductor memory device
JP4936749B2 (en) * 2006-03-13 2012-05-23 株式会社東芝 semiconductor memory device
US7292485B1 (en) * 2006-07-31 2007-11-06 Freescale Semiconductor, Inc. SRAM having variable power supply and method therefor
US7359272B2 (en) * 2006-08-18 2008-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit and method for an SRAM with reduced power consumption
US7492627B2 (en) * 2006-11-17 2009-02-17 Freescale Semiconductor, Inc. Memory with increased write margin bitcells
JP5057430B2 (en) * 2006-12-18 2012-10-24 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit and manufacturing method thereof
DE102007002150A1 (en) * 2007-01-15 2008-07-31 Infineon Technologies Ag Concept for the reduction of leakage currents of integrated circuits with at least one transistor
US8705300B1 (en) 2007-02-27 2014-04-22 Altera Corporation Memory array circuitry with stability enhancement features
EP2020658B1 (en) * 2007-06-29 2014-06-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device and semiconductor device
US7606061B2 (en) * 2007-08-07 2009-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. SRAM device with a power saving module controlled by word line signals
JP4775352B2 (en) * 2007-09-26 2011-09-21 ソニー株式会社 Manufacturing method of semiconductor memory device
JP4420121B2 (en) * 2008-03-12 2010-02-24 トヨタ自動車株式会社 Knee airbag device with column
JP2009231891A (en) * 2008-03-19 2009-10-08 Nec Electronics Corp Semiconductor device
EP2299933A4 (en) * 2008-06-04 2015-07-29 Endologix Inc Docking apparatus and methods of use
TWI425509B (en) * 2009-11-17 2014-02-01 Univ Hsiuping Sci & Tech Dual port sram having a discharging path
JP2011123970A (en) 2009-12-14 2011-06-23 Renesas Electronics Corp Semiconductor memory device
SG10201408329SA (en) * 2009-12-25 2015-02-27 Semiconductor Energy Lab Memory device, semiconductor device, and electronic device
EP3703055A1 (en) 2010-02-23 2020-09-02 Rambus Inc. Methods and circuits for dynamically scaling dram power and performance
US8320203B2 (en) 2010-03-26 2012-11-27 Intel Corporation Method and system to lower the minimum operating voltage of register files
US8531873B2 (en) * 2011-05-08 2013-09-10 Ben-Gurion University Of The Negev Research And Development Authority Ultra low power SRAM cell circuit with a supply feedback loop for near and sub threshold operation
US20120281459A1 (en) * 2011-05-08 2012-11-08 Ben-Gurion University Of The Negev Research And Development Authority Ultra low power memory cell with a supply feedback loop configured for minimal leakage operation
CN103250239A (en) * 2011-10-18 2013-08-14 新加坡优尼山帝斯电子私人有限公司 Semiconductor device
US8611169B2 (en) 2011-12-09 2013-12-17 International Business Machines Corporation Fine granularity power gating
US9093125B2 (en) 2012-01-23 2015-07-28 Qualcomm Incorporated Low voltage write speed bitcell
US9111600B2 (en) * 2012-03-30 2015-08-18 Intel Corporation Memory cell with improved write margin
US9001549B2 (en) * 2012-05-11 2015-04-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9153304B2 (en) * 2012-06-28 2015-10-06 Jaydeep P. Kulkarni Apparatus for reducing write minimum supply voltage for memory
US9111638B2 (en) * 2012-07-13 2015-08-18 Freescale Semiconductor, Inc. SRAM bit cell with reduced bit line pre-charge voltage
US8817528B2 (en) * 2012-08-17 2014-08-26 Globalfoundries Inc. Device comprising a plurality of static random access memory cells and method of operation thereof
US9183906B2 (en) 2012-10-02 2015-11-10 International Business Machines Corporation Fine granularity power gating
US20140119146A1 (en) * 2012-10-30 2014-05-01 Apple Inc. Clock Gated Storage Array
US8942052B2 (en) 2012-11-21 2015-01-27 International Business Machines Corporation Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages
KR102112367B1 (en) * 2013-02-12 2020-05-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
CN105493193B (en) * 2013-08-16 2018-10-19 英特尔公司 Use the retentive memory cell of the tool of resistance-type memory
JP2014139860A (en) * 2014-03-28 2014-07-31 Renesas Electronics Corp Semiconductor integrated circuit device
JP2016092536A (en) * 2014-10-31 2016-05-23 ルネサスエレクトロニクス株式会社 Semiconductor device
JP6436821B2 (en) * 2015-03-19 2018-12-12 エイブリック株式会社 Current detection circuit
US9786357B2 (en) * 2016-02-17 2017-10-10 Apple Inc. Bit-cell voltage distribution system
US9922701B2 (en) * 2016-08-08 2018-03-20 Taiwan Semiconductor Manufacturing Company Limited Pre-charging bit lines through charge-sharing
KR20180065073A (en) * 2016-12-06 2018-06-18 삼성전자주식회사 Sram device having uniform write characteristics
JP6535120B2 (en) * 2018-03-29 2019-06-26 ルネサスエレクトロニクス株式会社 Semiconductor device

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6161198B2 (en) 1978-11-08 1986-12-24 Nippon Electric Co
JPS57130463A (en) * 1981-02-06 1982-08-12 Toshiba Corp Semiconductor memory
JPS6120078B2 (en) * 1981-02-06 1986-05-20 Fujitsu Ltd
JPS58211391A (en) 1982-05-31 1983-12-08 Toshiba Corp Semiconductor storage device
JPS6038796A (en) * 1983-08-12 1985-02-28 Hitachi Ltd Semiconductor integrated circuit device
JPS62174968A (en) * 1986-01-29 1987-07-31 Hitachi Ltd Semiconductor device
JPS63108589A (en) * 1986-10-24 1988-05-13 Mitsubishi Electric Corp Semiconductor storage device
JPH01166399A (en) * 1987-12-23 1989-06-30 Toshiba Corp Static type random access memory
US5046052A (en) * 1988-06-01 1991-09-03 Sony Corporation Internal low voltage transformation circuit of static random access memory
JPH0766945B2 (en) * 1988-09-06 1995-07-19 株式会社東芝 Static memory
US4872141A (en) * 1988-09-12 1989-10-03 General Electric Company Radiation hard memory cell having monocrystalline and non-monocrystalline inverters
JPH02108297A (en) * 1988-10-18 1990-04-20 Nippon Telegr & Teleph Corp <Ntt> Memory cell circuit
JPH0383289A (en) 1989-08-25 1991-04-09 Nec Corp Mos type semiconductor storage device
JPH07109864B2 (en) * 1989-09-13 1995-11-22 シャープ株式会社 Static RAM
DE69119446T2 (en) * 1990-02-26 1996-10-31 Nec Corp Decoding circuit
WO1992003023A1 (en) 1990-08-06 1992-02-20 Fujitsu Limited Communication equipment having repeat switching function
US5226014A (en) * 1990-12-24 1993-07-06 Ncr Corporation Low power pseudo-static ROM
JPH04276386A (en) * 1991-03-01 1992-10-01 Nippon Telegr & Teleph Corp <Ntt> Memory circuit
JP3110113B2 (en) * 1991-11-21 2000-11-20 株式会社東芝 Static memory
JP3042203B2 (en) 1992-09-16 2000-05-15 日本電気株式会社 Static memory circuit
US5303190A (en) * 1992-10-27 1994-04-12 Motorola, Inc. Static random access memory resistant to soft error
US5301147A (en) * 1993-01-08 1994-04-05 Aptix Corporation Static random access memory cell with single logic-high voltage level bit-line and address-line drivers
KR0141933B1 (en) * 1994-10-20 1998-07-15 문정환 Sram of low power consumption
JP4198201B2 (en) * 1995-06-02 2008-12-17 株式会社ルネサステクノロジ Semiconductor device
TW373175B (en) * 1995-10-31 1999-11-01 Matsushita Electric Mfg Corp Data maintaining circuit
US5841707A (en) * 1995-11-29 1998-11-24 Texas Instruments Incorporated Apparatus and method for a programmable interval timing generator in a semiconductor memory
US5805496A (en) * 1996-12-27 1998-09-08 International Business Machines Corporation Four device SRAM cell with single bitline
JP3478953B2 (en) * 1997-09-03 2003-12-15 Necエレクトロニクス株式会社 Semiconductor storage device
JPH11260054A (en) * 1998-01-08 1999-09-24 Mitsubishi Electric Corp Dynamic semiconductor memory device
US6141240A (en) * 1998-09-17 2000-10-31 Texas Instruments Incorporated Apparatus and method for static random access memory array
US6058060A (en) * 1998-12-31 2000-05-02 Invox Technology Multi-bit-per-cell and analog/multi-level non-volatile memories with improved resolution and signal-to noise ratio
JP2002368135A (en) * 2001-06-12 2002-12-20 Hitachi Ltd Semiconductor memory device

Also Published As

Publication number Publication date
KR100395261B1 (en) 2003-08-21
US20020110036A1 (en) 2002-08-15
JP4198201B2 (en) 2008-12-17
US7978560B2 (en) 2011-07-12
US20100165706A1 (en) 2010-07-01
US20030012049A1 (en) 2003-01-16
US20010006476A1 (en) 2001-07-05
US5668770A (en) 1997-09-16
US7251183B2 (en) 2007-07-31
US20040046188A1 (en) 2004-03-11
US8325553B2 (en) 2012-12-04
US20070165448A1 (en) 2007-07-19
KR100395260B1 (en) 2003-08-21
US6215716B1 (en) 2001-04-10
US7706205B2 (en) 2010-04-27
TW302535B (en) 1997-04-11
US6639828B2 (en) 2003-10-28
US6469950B2 (en) 2002-10-22
US6108262A (en) 2000-08-22
JPH0951042A (en) 1997-02-18
US5894433A (en) 1999-04-13
US20050226077A1 (en) 2005-10-13
US20110235439A1 (en) 2011-09-29
US6917556B2 (en) 2005-07-12
US6388936B2 (en) 2002-05-14

Similar Documents

Publication Publication Date Title
US4094012A (en) Electrically programmable MOS read-only memory with isolated decoders
US6671201B2 (en) Method for writing data into a semiconductor memory device and semiconductor memory therefor
US5583821A (en) Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage
JP4558410B2 (en) Method of accessing memory of unloaded 4TSRAM cell
US4584672A (en) CMOS dynamic random-access memory with active cycle one half power supply potential bit line precharge
US6992343B2 (en) Semiconductor memory device
EP0643393B1 (en) Semiconductor memory device having voltage booster circuit
JP4443886B2 (en) Semiconductor memory device
US6643182B2 (en) Semiconductor device
KR100650244B1 (en) Gated diode memory cells
US6603345B2 (en) Semiconductor device with reduced leakage of current
JP4822791B2 (en) Semiconductor memory device
US9111593B2 (en) Differential sense amplifier without dedicated precharge transistors
US6347058B1 (en) Sense amplifier with overdrive and regulated bitline voltage
EP0713222B1 (en) An integrated circuit memory device
JP3913709B2 (en) Semiconductor memory device
US5581500A (en) Memory cell with power supply induced reversed-bias pass transistors for reducing off-leakage current
US6826074B2 (en) Semiconductor memory device
JP3802952B2 (en) Data sensing circuit for semiconductor memory device
JP3085073B2 (en) Static RAM
EP0475407B1 (en) DRAM using word line drive circuit system
JP4895439B2 (en) Static memory
US6545923B2 (en) Negatively biased word line scheme for a semiconductor memory device
JP4251815B2 (en) Semiconductor memory device
US6567330B2 (en) Semiconductor memory device

Legal Events

Date Code Title Description
A107 Divisional application of patent
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130118

Year of fee payment: 11

FPAY Annual fee payment

Payment date: 20140117

Year of fee payment: 12

FPAY Annual fee payment

Payment date: 20150119

Year of fee payment: 13

FPAY Annual fee payment

Payment date: 20160119

Year of fee payment: 14