JPH09120675A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent undue overdrive even when the power supply voltage being fed to a sense amplifier is high. SOLUTION: At the time of employing an overdive technology where a power supply voltage VDD is fed as an operational power supply based on an initially activated first control signal ϕSAIB at the activation timing of sense amplifier and then a step down voltage VDL having lower level than the power supply voltage is fed as an operating power supply voltage based on a second activated control signal ≃SA2B, a control circuit TG employs an inverter operating with the power supply voltage VDD as a delay means 12 for determining the overdrive time after activation of first control signal before activation of second control signal. Delay time of delay circuit has negative dependency on the power supply voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit provided with a differential amplifier circuit driven in an overdrive format, for example, a DRAM (Dynamic Random Random) whose operating voltage is lowered for high integration. -Technology effective when applied to access memory).

[0002]

2. Description of the Related Art In order to increase the storage capacity of DRAM, MOS transistors such as memory cell transistors (hereinafter also referred to as MOSFETs) are miniaturized, and as a result, the gate length of MOS transistors is reduced and the gate oxide film is thinned. Therefore, the operating voltage is being reduced. In particular, in the case of a DRAM, a high level write operation (charging operation for the storage capacity of a memory cell) is performed when the high level read operation efficiency is not lowered (or the high level read operation margin is made relatively large). It is effective to raise the selection level of the word line or lower the voltage of the data line to which the data input / output terminal of the memory cell is coupled (the level of the data line reached by the amplifying operation of the sense amplifier). However, as described above, when the gate oxide film of the MOS transistor is thinned with the high integration of the transistor, if the voltage level of the word line is unnecessarily raised, the gate oxide film is easily broken and the DRAM It is not preferable in terms of reliability. Under such circumstances, it is inevitable to reduce the voltage of the data line. When the voltage of the data line is lowered in this way, it impedes high-speed operation of the sense amplifier. That is, when the voltage of the operating power supply of the sense amplifier is lowered, the current flowing through the sense amplifier is reduced, and when the charge information of the memory cell is read to the data line, the minute potential difference formed on the complementary data line is reduced. The speed of amplification is reduced.

Therefore, there is a sense amplifier overdrive technique as a technique for operating a sense amplifier at high speed under a low voltage. For example, when the sense amplifier is configured in the CMOS static latch form, the external power supply voltage VDD is applied to the source of the P-channel MOS transistor at the beginning of the sense amplifier activation timing, and then the voltage VDL obtained by stepping down the external power supply voltage VDD is applied. Give and operate the sense amplifier. One of the sense amplifier overdrive technologies is ISSCC95A 29ns 64Mb DRAM with
Reported in Hierachical Arry Architecture / FA14.2. Further, Japanese Patent Laid-Open No. 5-62467 discloses a technique of using a dummy data line to control a period (overdrive time) in which an external power supply voltage is supplied to a sense amplifier.

[0004]

As a result of studying the above-mentioned sense amplifier overdrive technique, the present inventor has found the following problems. That is, the source of the P-channel MOS transistor forming the sense amplifier is supplied with the external power supply voltage VDD via the switch element, and is also coupled to the output terminal of the step-down circuit via another switch element. The supply lines of the external power supply voltage VDD and the step-down voltage VDL are shared by many sense amplifiers. When the external power supply voltage VDD is supplied to the sense amplifier, it is an operating voltage higher than the step-down voltage VDL, so that the sense amplifier operates at high speed. That is, the initial transient response operation in the amplification operation of the sense amplifier is speeded up. Then, the operating power supply of the sense amplifier is switched to the step-down voltage VDL.
In this case, since an undesired capacitance component exists in the supply line and the data line of the operating power source shared by a large number of sense amplifiers, the external power source voltage VDD is at the upper limit level of the allowable range, In a state where an external power supply voltage of a higher level than usual is supplied to test the margin, the operating power supply of the sense amplifier is the step-down voltage V.
When switched to DL, it is expected that current will flow backward from the sense amplifier toward the output terminal of the step-down circuit.

At this time, if a circuit in which a high resistance is connected in series to a current source coupled to an external power supply voltage is adopted as the step-down circuit to minimize the through current in the step-down circuit, the sense amplifier side It has been found by the present inventor that the current flowing backward toward the output terminal of the step-down circuit is blocked by the high resistance and is not immediately leaked to the ground potential, and as a result, the step-down voltage VDL may rise.

The undesired increase of the stepped down voltage VDL is disadvantageous in the following points. That is, the step-down voltage VDL
Rises the arrival voltage of the data line due to the amplification operation of the sense amplifier, which reduces the potential difference between the selection level of the word line and the high level of the data line,
In high-level writing to the memory cell, the high-level voltage of the data line cannot be applied to the storage capacitor. Further, if the voltage reached by the sense amplifier on the data line is increased due to an undesired increase in the step-down voltage VDL, the initial level (precharge level) of the data line equalized during the chip non-selection period is correspondingly increased. ) Also rises, and when the data written in such a state is read, the high level read voltage margin with respect to the precharge level is also reduced. Further, when the booster circuit forming the word line selection level uses the step-down voltage VDL, an undesired increase in the step-down voltage VDL raises the word line selection level, and the gate oxide film of the memory cell select transistor is increased. There is a risk of damaging the.

The above problems are problems when the external power supply voltage is at the upper limit level of the allowable range, but when the external power supply voltage is at the lower limit level of the allowable range, in the amplifying operation of the sense amplifier. There is a problem that the speed of the initial transient response operation cannot be sufficiently obtained.

As mentioned above, the present inventors have revealed the above-mentioned problems when adopting the overdrive technique.
The above-mentioned Japanese Patent Laid-Open No. 5-62467 discloses that the charging / discharging state of the dummy data line is detected and the overdrive time is controlled accordingly, but in this case, the dummy data line is formed. Area needed. Further, in order to detect the potential level of the dummy data line,
There is a problem that a detection circuit for that purpose must be newly provided. Since the data lines arranged on the outermost side of the memory array are likely to be defective in the manufacturing process,
Not commonly used as a normal data line. Therefore, it is possible to use the unused data line as the dummy data line, but if the data line that is likely to be defective is used as the dummy data line, a reliable operation cannot be expected. As described above, the present inventor has revealed that the technique of adjusting the overdrive time by using the dummy data line has a problem in terms of the degree of integration of the chip and the reliability of the operation.

Further, according to the study by the present inventor, in the CMOS static latch type sense amplifier, the power switch MOS transistor for supplying the drive voltage to the drive line of the P-channel type MOS transistor is
Since the conventional P-channel type is used, when the operating voltage of the sense amplifier is lowered, the gate-source voltage (VGS) of the power switch MOS transistor is reduced when the operating voltage is supplied. As a result, it has been clarified that the current supply capability of the power switch MOS transistor is lowered and the high speed operation of the sense amplifier is hindered. Especially when the sense amplifier is overdriven, the high-speed operation of the sense amplifier is significantly hindered when the step-down voltage is supplied. It is considered that such a problem generally appears not only in the case of overdriving the sense amplifier, but also in a differential amplifier circuit whose operating voltage is lowered.

An object of the present invention is to effectively prevent excessive overdrive to the differential amplifier circuit even if the high-potential side drive voltage for the differential amplifier circuit such as a sense amplifier driven in the overdrive form is increased. Another object of the present invention is to provide a highly integrated semiconductor integrated circuit capable of achieving the above.

Another object of the present invention is to provide an undesired level to the step-down voltage of a step-down circuit which supplies the step-down voltage as one operating power source to a differential amplifier circuit such as a sense amplifier driven in an overdrive format. It is an object of the present invention to provide a semiconductor integrated circuit capable of preventing the risk of rising.

Another object of the present invention is to provide a technique capable of preventing a decrease in operating current supply capability due to a MOS transistor for supplying a low-voltage operating power supply to a differential amplifier circuit. . Another object of the present invention is to provide a semiconductor integrated circuit capable of operating a differential amplifier circuit such as a sense amplifier at high speed even when the operating voltage is lowered.

Another object of the present invention is to provide a semiconductor integrated circuit capable of amplifying the potential of the data line at a high speed and surely to a desired level in the overdrive technique.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] In order to ensure high-speed operation of the differential amplifier circuit (3) included in the circuit portion driven at a low voltage when the operating voltage is lowered due to the miniaturization or high integration of the element, At the activation timing of the differential amplifier circuit, first, a first drive control signal (φSA) for supplying a first drive voltage (VDD) as an operating power source of the differential amplifier circuit is first obtained.
1B) and is activated in response to the deactivation of the first drive control signal after the activation of the first drive control signal, the level is higher than that of the first drive voltage. A second drive control signal (φSA2) for controlling supply of a low second drive voltage (VDL) as an operating power supply of the differential amplifier circuit.
As a delay means (12) for defining a period during which the first drive control signal is activated (that is, an overdrive time) when the overdrive technique for forming B) is adopted in the control circuit (TG). An inverter circuit that receives the first drive voltage as an operating power supply is used, and a period during which the first drive control signal is activated has a negative dependency on the first drive voltage.

The overdrive technique can be adopted as a drive technique for a differential amplifier circuit such as a sense amplifier included in a large number of DRAMs having dynamic memory cells. That is, this is to ensure high-speed operation of the differential amplifier circuit (3) such as a sense amplifier when the operating voltage is lowered due to the higher integration of the memory array. At this time, the operating power supply of the memory array is the step-down voltage (VD) obtained by stepping down the external power supply voltage (VDD) by the step-down circuit (1).
L), when driving a differential amplifier circuit such as a sense amplifier, the external power supply voltage is set to the first drive voltage,
The step-down voltage is the second drive voltage.

When the overdrive technique is adopted as a drive system for a differential amplifier circuit such as a sense amplifier,
When the external power supply voltage is at the upper limit level of the allowable range, or when a power supply voltage higher than normal is being supplied to test the operating margin, the operating power supply of the differential amplifier circuit is the external power supply. When the voltage (VDD) is switched to the step-down voltage (VDL), it is expected that the current flows backward from the differential amplifier circuit toward the output terminal of the step-down circuit. For example, as a step-down circuit, if a circuit in which a high resistance is connected in series to a current source that is coupled to the power supply voltage is adopted to try to minimize the through current in the step-down circuit
The current flowing backward from the sense amplifier side toward the output terminal of the step-down circuit is not blocked by the high resistance and is not immediately leaked to the ground potential. At this time, according to the above-mentioned means, in the MOS circuit such as the CMOS inverter which defines the overdrive time, the higher the operating power supply voltage is, the shorter the transient response time is, and therefore the lower external power supply voltage (VDD) is. When the overdrive time is relatively long, the overdrive time is relatively short when the external power supply voltage (VDD) is high. Since the delay time of the delay circuit has a negative dependency on the external power supply voltage (VDD) as described above, it is possible to prevent the differential amplifier circuit from being overdriven excessively.

By preventing excessive overdrive to the differential amplifier circuit, it is possible to prevent the occurrence of a situation in which current flows backward from the differential amplifier circuit such as a large number of sense amplifiers toward the step-down circuit. A situation in which the step-down voltage is undesirably raised in level is prevented.

[2] The MOS transistor (Q42) for supplying the operating voltage (VDL) to the drive line (SDP) on the high potential side of the differential amplifier circuit (3) is an N-channel type, and switching supplied to its gate. Control signal (φ
The high level potential of SAN2) is the potential of the boosted voltage (VPP) whose level is higher than the drain voltage. As the boosted voltage, the output voltage of the internal booster circuit (2) forming the word line selection level can be used.

According to another aspect, the operating voltage (VD) is applied to the drive line (SDP) on the high potential side of the differential amplifier circuit (3).
The MOS transistor (Q43) for supplying L) is a P-channel type, and the low level potential of the switching control signal (φSAP2B) supplied to the gate of the MOS transistor (Q43) is a negative voltage () whose polarity is opposite to that of the power supply voltage (VDD). VBB). The output voltage of the substrate bias voltage generating circuit (5) can be used as the negative voltage.

Even if the operating voltage of a differential amplifier circuit such as a sense amplifier is lowered, if the MOS transistor for supplying operating power to the drive line on the high potential side is an N-channel type, it is turned on. The gate-source voltage for this purpose can be determined according to factors such as the breakdown voltage of the gate oxide film of the MOS transistor. Therefore, there is no tendency that the gate-source voltage decreases as the operating voltage of the differential amplifier circuit decreases. Further, the carrier mobility of the N-channel type MOS transistor is about three times larger than that of the P-channel type MOS transistor, so that the gate-source voltage is equal to or lower than that of the P-channel type MOS transistor. A relatively large current supply capability can be obtained even with voltage. As a result, it is possible to prevent the gate-source voltage of the MOS transistor for supplying operating power to the high potential side drive line from being reduced as the operating voltage is lowered, and even in the situation where the operating voltage is lowered. The differential amplifier circuit can be operated at high speed.

Further, an MO that supplies operating power to the drive line on the high potential side of a differential amplifier circuit such as a sense amplifier.
Even if the S-transistor is a P-channel type, if the signal voltage for controlling the switch is a negative voltage, the M
The gate-source voltage of the OS transistor can be made relatively large, and as a result, the differential amplifier circuit can operate at high speed even when the operating voltage is lowered.

As the boosted voltage for defining the signal amplitude for switch controlling the N-channel type MOS transistor for supplying the operating power to the drive line on the high potential side,
The output of the booster circuit forming the word line selection level is used, and the operating power is supplied to the drive line
By using the negative voltage formed by the substrate bias voltage generating circuit as the negative voltage for defining the signal amplitude for controlling the switching of the channel type MOS transistor, the circuit scale can be increased when the operating speed of the differential amplifier circuit is increased. The increase can be suppressed as much as possible.

[3] Further, the following means can be adopted for overdriving. That is, the semiconductor integrated circuit is a CMOS latch circuit including a pair of data lines, a pair of P-channel type MOS transistors and a pair of N-channel type MOS transistors, and a sense amplifier for amplifying the potential difference between the pair of data lines. A first terminal for receiving a first voltage, a second terminal for receiving a second voltage lower than the first voltage, a pair of sources commonly coupled in the pair of P-channel MOS transistors, and the first terminal. First switch MO provided between
An S-transistor, an N-channel type second provided between the pair of commonly-coupled sources and the second terminal.
The switch MOS transistor and the first switch MOS transistor are turned on during a first period,
The first and second switches M so that the first switch MOS transistor is turned off and the second switch MOS transistor is turned on in the second period after the period.
A control circuit for outputting a signal to the gate of the OS transistor, and the second switch MOS in the second period.
The gate voltage of the transistor is higher than the second voltage.

The control circuit includes a delay circuit that defines the first period, and the fluctuation of the first period has a negative dependence on the fluctuation of the first voltage.

According to this means, in the overdrive technique, the overdrive time (first period) can be controlled according to the overdrive voltage (first voltage), so that the overdriving of the sense amplifier can be prevented and
Second switch M for supplying a relatively low voltage (second voltage)
It is possible to reduce the on-resistance of the OS transistor and increase the current supply capability accordingly. Therefore, in the overdrive technique, the sense amplifier can quickly and surely amplify the voltage level of the data line to a desired level.

By configuring the delay circuit with an inverter circuit that receives the first voltage as an operating power supply, the overdrive time can be reliably controlled with a simple structure.

In the second period, the second switch M
By making the gate voltage of the OS transistor equal to or higher than the sum of the second voltage and the threshold voltage of the second switch MOS transistor,
It is possible to prevent a drop corresponding to the threshold voltage from occurring in the second switch MOS transistor.

[0030]

FIG. 8 shows a DR according to an example of the present invention.
A block diagram of the AM is shown. DRAM shown in FIG.
Is not particularly limited, but is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. FIG. 8 typically shows two memory arrays M.
ARY0 and MARY1 are shown.

The DRAM shown in FIG. 8 receives an external power supply voltage VDD such as 3.3V and a ground potential VSS such as 0V from an external power supply terminal. In this DRAM, the MOS transistors in the memory arrays MARY0 and MARY1 are miniaturized in order to increase the storage capacity, and the gate oxide film is thinned as the gate length of these MOS transistors is reduced. Therefore, the memory array M
The operating voltage in ARY0 and MARY1 is lowered, and a step-down voltage VDL such as 2.2 V is used as a basic operating power supply. The step-down voltage VDL is generated by the step-down circuit 1 that steps down the external power supply voltage VDD. In the figure, 5 is a circuit for generating the substrate bias voltage VBB. The substrate bias voltage generating circuit 5 can also be configured by a known circuit. For example, although not shown, the substrate bias voltage generating circuit 5 is configured by a capacitor and a diode element, and receives the periodic signal of the positive polarity to receive the negative substrate bias voltage VB.
Form B.

Each of the memory arrays MARY0 and MARY1 is divided into eight memory mats MMAT0 to MMAT7. Individual memory mats MMAT0 to MMAT7
Includes a large number of one-transistor type dynamic memory cells whose select terminals are connected to word lines and whose data input / output terminals are connected to complementary data lines. Word drivers WD0 to WD7 and row address decoder XD for each memory mat
0 to XD7 are provided. Row address decoder XD0
When the operation is selected, the to XD7 decode the internal complementary row address signal AX to form a word line selection signal, and select one word line corresponding to the internal complementary row address signal AX. The word drivers WD0 to WD7 receive the word line selection signal and drive the word line to be selected by the word line selection signal to the selection level in synchronization with the word line drive timing instructed by the control signal φX. The word line selection level formed by the word drivers WD0 to WD7 is the boosted voltage VPP having a higher level than the stepped down voltage VDL. The boosted voltage VPP is generated by the booster circuit 2 that boosts the lowered voltage VDL. Although details of the booster circuit 2 are not shown, it can be easily formed by applying a known charge pump circuit.

SA01, SA23, SA45, SA67
Is a sense amplifier block, CSW01, CSW23, C
SW45 and CSW67 are column switch circuit blocks, which are arranged between a pair of left and right memory mats and shared by a pair of adjacent left and right memory mats. Sense amplifier blocks SA01, SA23, SA45, SA67 and column switch circuit blocks CSW01, CSW23, CS
A shared data line structure is adopted for the pair of left and right memory mats arranged with the W45 and CSW67 interposed therebetween, and the operation of either one of the memory mats is selected. The operation selection and operation control of the memory mats, such as the operation control of each sense amplifier block and the control of the data line sharing switch circuit (see FIG. 9) between the memory mats sharing the sense amplifier block, are performed by a pair of memory mats. Mat controller MC provided for each
NT01, MCNT23, MCNT45, MCNT67
Do.

Mat controller MCNT01, MCN
T23, MCNT45 and MCNT67 have a mat selection signal MS and sense amplifier control signals φSAN, φSAN2.
φSAP1B is supplied. The mat selection signal MS is a 3-bit signal instructing which one is selected from the eight memory mats MMAT0 to MMAT7. Actually, it corresponds to the information of the upper 3 bits of the row address signal held in the row address buffer RAB. Mat controller MCNT01, MCNT23, MCNT4
5, MCNT 67 decodes the mat selection signal MS,
The operation control of the sense amplifier block and the activation control of the row address decoder are performed so that the memory mat designated by it is operated. For example, when the mat select signal MS designates the memory mat MMAT0, the row address decoder XD0 is activated, the sense amplifier block SA01 is connected to the memory mat MMAT0 via the data line sharing switch circuit, and the memory mat MMAT0 is connected.
A memory cell selection operation is enabled in AT0.
Sense amplifier control signals φSAN, φSAN2, φSAP
Details of 1B will be described later.

Each column switch circuit block CSW
n receives a column selection signal from the column address decoder YD, thereby selecting four sets of complementary data lines from the memory mat, and complementary common data lines CD0-C0.
Conduct to D3. In the read operation, the column address decoder YD is made operable by the timing signal φY which is set to the enable level after the word line selection operation is determined, thereby decoding the internal complementary column address signal AY and generating the column selection signal. .

By the word line selection operation and the column selection operation, four memory cells designated by the mat selection signal MS, the internal complementary row address signal AX, and the internal complementary column address signal AY are supplied to the complementary common data lines CD0 to CD0. CD
3 is conducted. Although not particularly shown, the memory array MARY1 side is also configured in the same manner as described above, and the memory array MARY
Complementary common data lines CD4 to CD7 are arranged on the first side.

The complementary common data lines CD0 to CD7 are
Although not particularly limited, it is coupled to the data input / output circuit DIO. The data input / output circuit DIO includes a main amplifier, a write amplifier, and a data input / output buffer. When the timing signal φW is set to the enable level, the data input operation for writing is performed, and the timing signal φ
When R is set to the enable level, a data output operation for reading is performed. Dynamic R of this embodiment
In the AM, data is written and read in units of 8 bits, the memory array MARY0 carries the lower 4 bits, and the memory array MARY1 carries the upper 4 bits.

The row address buffer RAB fetches and holds the row address signal input from the external address input terminals A0 to Ai via the address multiplexer AMX. This fetching operation is instructed by the high level of the timing signal φXL supplied from the timing generating circuit TG.

Although not particularly limited, the address multiplexer AMX supplies the disable level timing signal φREF from the timing generation circuit TG when the dynamic RAM is set to the normal operation mode, so that the external terminals A0 to Ai are supplied. The row address signal supplied via the row address buffer RAB is transmitted. In addition, the dynamic RAM is CBR (CAS brfore R
AS) When the timing signal φREF is set to the enable level during the refresh cycle, the refresh address signal supplied from the refresh address counter RFC is selected and transmitted to the row address buffer RAB.

The refresh address counter RFC is
Although not particularly limited, when the dynamic RAM is set to the CBR refresh mode, the timing generation circuit TG
From the timing signal φRC supplied every predetermined cycle
A refresh address is generated by performing a counting operation in synchronization with the.

The column address buffer CAB synchronizes the column address signal supplied through the external address input terminals A0 to Ai with the timing when the control signal φYL supplied from the timing generation circuit TG is enabled. Capture and hold.

The timing generation circuit TG uses the row address strobe signal RAS * (the symbol * means that the signal to which it is attached is a row enable signal) and the column address strobe CAS as access control signals from the outside. *, The write enable signal WE *, and the output enable signal OE * are supplied, and the dynamic RAM is based on these levels and change timings.
The operation mode is determined, the various timing signals are formed, and the internal operation of the dynamic RAM is controlled. The row address strobe signal RAS * instructs chip selection by its low level and notifies that the row address signal is valid. According to this, the timing controller TG fetches the row address signal,
Then, the control signals for word line selection operation and memory mat selection are sequentially generated. The column address strobe CAS * is a signal notifying that the column address signal is valid. When it is set to the enable level, the timing controller TG sequentially generates the control signals for fetching the column address signal and the column selecting operation. The write enable signal WE * instructs the DRAM to perform a write operation according to its enable level, and the output enable signal OE * instructs the DRAM to perform a read operation according to its enable level. In the CBR refresh mode, the row address strobe signal RAS is used.
It is specified by setting the column address strobe CAS * to the enable level before * is enabled.

FIG. 9 shows the memory mats MMAT0 and MMAT.
Partial circuit diagrams of the MAT1, the sense amplifier block SA01, and the column switch circuit block CSW01 are shown. Particularly, in the figure, one column selection signal YS00
The circuit portion that receives the signal is typically shown. In the figure, the channel (back gate) part is marked with an arrow M
The OS transistor is a P-channel type and is distinguished from an N-channel type MOS transistor without an arrow.

WL0 to W typically shown in FIG.
Li is a word line, and DL0, DL0B, DL1, D
L1B is a complementary data line, and MC is a dynamic memory cell. The dynamic memory cell MC is formed by connecting a series circuit of a selection MOS transistor Q1 connected to a data line and a storage capacitor SC to a plate potential PL (VDL / 2). Q27 to Q34 are some sharing switch MOS transistors forming a data line sharing switch circuit. The representatively shown sharing switch MOS transistors Q27 to Q30 arranged between the memory mat MMAT0 and the memory mat MMAT0 have control signals φSH.
Representatively shown sharing switch MOS transistors Q31 to Q34 which are switch-controlled by RL and are arranged between memory mat MMAT1 and control signal φSH.
Switch control is performed by RR. For example, the mat selection signal M
When S selects the memory mat MMAT0, the mat controller MCNT01 controls the control signal φSHRL to the high level. When the mat selection signal MS selects the memory mat MMAT1, the mat controller MCNT01 controls the control signal φSHRR to a high level. The sharing switch MOS transistor related to the memory mat not selected by the mat selection signal MS is controlled to the off state by the mat controller corresponding to the memory mat.

N-channel type MOS transistor Q9,
Q10 and P-channel type MOS transistors Q13, Q
The differential amplifier circuit of the static latch type constituted by 14 is one sense amplifier 3 composed of a CMOS latch circuit, and the sense amplifier 3 is provided for each complementary data line. The operating power of the sense amplifier 3 is supplied via the drive lines SDN and SDP. The drive lines SDN and SDP are common to each sense amplifier 3.
The supply control of the operating power supply to the drive lines SDN and SDP will be described later. In addition to the sense amplifier 3, each complementary data line includes a MOS transistor Q21 for equalizing the complementary data line when the dynamic RAM is on standby. The MOS transistor Q21 is switch-controlled by the control signal φPCSB. Further, a MOS transistor Q17 for supplying a precharge potential to the complementary data line with equalization of the complementary data line,
Q18 is provided. The precharge potential is set to a half level of the step-down voltage VDL and is supplied through the wiring HVC. The MOS transistors Q17 and Q18 are switch-controlled by the control signal φPCB. The control signal φ
PCB and φPCSB are output from the timing controller TG. The precharge voltage VDL / 2 is formed by the precharge voltage forming circuit 4, and for example, the step-down voltage VDL
It is composed of a resistance voltage dividing circuit and the like.

In FIG. 9, Q23 and Q24 are complementary data lines DL0 and DL0B and complementary common data line CD0 (cd
0, cd0B), and Q25, Q26 are column switches provided between the complementary data lines DL1, DL1B and the complementary common data line CD1 (cd1, cd1B). A similar column switch is provided for each complementary data line, and four pairs of complementary data lines are used as a set to form four pairs of complementary common data lines CD0 (cd0, c).
d0B), CD1 (cd1, cd1B), CD2 (cd
2, cd2B) and CD3 (cd3, cd3B) are commonly connected.

Next, the drive line SD of the sense amplifier 3
A circuit configuration for supplying operating power to N and SDP will be described.

FIG. 1 shows a circuit for supplying operating power to the drive lines SDN and SDP of the sense amplifier 3.
In the same figure, the sense amplifier 3 for one column is representatively shown, but the drive line SD representatively shown in the figure is shown.
N and SDP are generic names of drive lines SDN and SDP for all sense amplifiers 3 included in the DRAM of this embodiment. The drive line SDN has a control signal φS.
The ground potential VSS is supplied through an N-channel MOS transistor Q40 which is switch-controlled by AN.
The drive line SDP has a P-channel type MOS transistor Q switch-controlled by a control signal φSA1B.
An external power supply voltage VDD is supplied via 41, and a step-down voltage VDL is supplied via a P-channel type MOS transistor Q42 which is switch-controlled by a control signal φSA2B. Control signals φSAN, φSA1B, φSA2
B is output from the timing controller TG.

As described above, the DRAM according to this example receives the external power supply voltage VDD such as 3.3V from the external power supply terminal, but the memory array M is increased in order to increase the storage capacity.
Since the MOS transistors in ARY0 and MARY1 are miniaturized, and the gate oxide film is thinned with the reduction in the gate length of those MOS transistors, the operating voltage in the memory arrays MARY0 and MARY1 is lowered. For example, a step-down voltage VDL such as 2.2V is used as a basic operating power supply. At this time, if only the step-down voltage VDL is supplied to the drive line SDP, the operating speed of the sense amplifier 3 becomes slower. Therefore, the drive line SDP is supplied with the external power supply voltage VDD at the beginning of the sense amplifier activation timing. Next, the step-down voltage VDL is applied to operate the sense amplifier.
Sense amplifier overdrive technology is applied.

That is, as shown in FIG. 2, the control signal φSAEB (internal control signal of the timing controller TG and not shown in FIG. 1) that defines the activation period of the sense amplifier 3 is at a low level. When changed to the active level, first, the control signal φSA1B is changed to the low level, and the power supply voltage VDD is supplied to the drive line SDP via the MOS transistor Q41. As a result, the current supplied from the P-channel type MOS transistors Q13 and Q14 of the sense amplifier 3 is relatively large, so that the minute potential difference appearing on the complementary data lines DL0 and DL0B due to the memory cell selecting operation is quickly amplified. Next, the control signal φSA1B is inverted to the high level and the control signal φSA2B is set to the low level, whereby the step-down voltage VDL is supplied to the drive line SDP via the MOS transistor Q42. The control signal φSAN is set to high level in synchronization with the low level period of the control signal φSAEB. As a result, the arrival levels of the complementary data lines driven by the sense amplifier 3 are defined such that one is the ground potential VSS and the other is the step-down voltage VDL. In this way, the amplification operation of the sense amplifier 3 under the low voltage driving of the memory cell array is accelerated.
In FIG. 2, ODT is the overdrive time.
Since the switch MOS transistors Q41 and Q42 are coupled in parallel, the power supply voltage VDD and the step-down voltage VDL are supplied to the drive line SDP via one switch MOS transistor, respectively. Therefore, the ON resistance of the switch circuit can be reduced as compared with the case where the switch MOS transistors are coupled in series.

The step-down circuit 1 has a series connection point of a P-channel type MOS transistor Q50 coupled to the external power supply voltage VDD and a high resistance R1 coupled to the ground potential VSS as an output terminal Nout, and the output terminal Nout. Is fed back to the non-inverting input terminal (+) and the inverting input terminal (-)
Is supplied with a reference voltage VLR and is provided with an operational amplifier AMP1 for switch controlling the MOS transistor Q50. The operational amplifier AMP1 has an output terminal N
When the potential of out is made lower than the reference potential VLR, MO
When the conductance of the S transistor Q50 is increased (the ON resistance is decreased) and the potential of the output terminal Nout is made higher than the reference potential VLR, the conductance of the MOS transistor Q50 is decreased (the ON resistance is increased) and the voltage of the output terminal Nout is reduced. Feedback control is performed so as to maintain the reference voltage VLR. The voltage thus formed at the output terminal Nout is the step-down voltage VDL. In particular, the value of the resistor R1 is set to a very large value in order to minimize the through current flowing in the series circuit of the MOS transistor Q50 and the resistor R1. In the negative feedback control, high resistance R1
The current that flows to the output terminal Nout via the output terminal is substantially negligible. The reference voltage VLR is, for example, a control voltage formed by a known reference voltage generating circuit (not shown), and is set to 2.2V, for example.

Here, the external power supply voltage VDD is, for example, 3.
It is set to 3V, but the available power supply voltage is typically ± 10%.
Allowing a certain degree of tolerance. Therefore, the active period (overdrive time ODT) of the control signal φSA1B is set so that the transient response operation of the sense amplifier 3 can be accelerated even when the lower limit level in the allowable range is supplied as the external power supply voltage VDD. Must be set. Therefore, if the overdrive time is fixed only from such a viewpoint, the supplied external power supply voltage VDD is at the upper limit level of the allowable range, or is particularly high for an operation margin test on the power supply voltage VDD side. For example, when the external power supply voltage VDD is supplied, when the operating power supply of the sense amplifier 3 is switched from the external power supply voltage VDD to the step-down voltage VDL, a current flows from the drive line SDP to the output terminal Nout of the step-down circuit 1. Will flow backwards. As described above, the reverse current cannot be expected to be immediately discharged to the ground potential VSS via the high resistance R1. Driveline SD
The reverse current from P gradually raises the level of the step-down voltage VDL, and accordingly raises the precharge level (VDL / 2) of the complementary data line.

In this example, the overdrive time ODT is set in accordance with the level of the power supply voltage VDD so as to prevent excessive overdrive in which a current flows backward from the drive line SDP to the step-down circuit 1. It is variably controlled.

The timing forming circuit therefor is shown as part of the timing controller TG shown in FIG. That is, in the low level period of the control signal φSAEB that defines the activation period of the sense amplifier 3, both control signals φSA1B, so that the control signal φSA1B is first activated and then the control signal φSA2B is activated. In order to change φSA2B complementarily, a NAND gate 10 and a NOR gate 11 each having two inputs are used.
Is provided, one input terminal of the NAND gate 10 and one input terminal of the NOR gate 11 are coupled to each other, and an odd number of Cs are provided between the one input terminal and the other input terminal of the NAND gate 10.
MOS inverters INV0 to INVi (i = 2n-1)
A delay circuit 12 in which are connected in series is arranged. FIG. 4 shows a specific example of the delay circuit. The other input terminal of the NAND gate 10 has a CMOS inverter 1
The control signal φSAEB is supplied via 3 and the control signal φSAEB is supplied to the other input terminal of the NOR gate 11. The control signal φSA1B is output from the NAND gate 10, and the control signal φSA2B is formed by inverting the output of the NOR gate 11 by the CMOS inverter 14. The control signal φSAN corresponds to the control signal φSAEB in three stages in series.
It is formed through MOS inverters 15, 16 and 17.

The operating power supplies for the circuits included in the timing controller TG are the external power supply voltage VDD and the ground potential VSS. The number of serial stages of the CMOS inverters INV0 to INi included in the delay circuit 12 is sufficient for overdriving the transient response operation of the sense amplifier 3 even when the external power supply voltage VDD is at the lower limit level of the allowable range. The time ODT is determined to be obtained. Here, the CMOS inverters INV0 to INi of the delay circuit 12 which define the overdrive time ODT receive the external power supply voltage VDD as their power supply voltage as shown in FIG. The higher the operating power supply voltage of each inverter, the shorter the transient response time. Therefore, when the external power supply voltage (VDD) is low, the overdrive time is relatively long, and when the external power supply voltage (VDD) is high, the overdrive time is relatively long. Overdrive time is shortened relatively. Thus, the delay time of the delay circuit has a negative dependence on the external power supply voltage (VDD).
Therefore, the supplied external power supply voltage VDD is at the upper limit level of the allowable range, or the external power supply voltage VDD is particularly high for an operation margin test on the power supply voltage VDD side.
Is supplied, the delay time of the delay circuit 12 is relatively shortened. In other words, overdrive time OD
T is made relatively short, and the time during which the relatively high level external power supply voltage VDD is supplied to the drive line SDP via the MOS transistor Q41 is shortened. As a result, the sense amplifier 3 can be prevented from being overdriven excessively by the external power supply voltage VDD having a relatively high level.

As described above, the overdrive voltage (VD) is used as the power supply voltage of the inverter forming the delay circuit.
By using D), the overdrive time can be reliably controlled with a simple configuration.

Since it is possible to prevent the overdrive to the sense amplifier 3 from becoming excessive, it is possible to prevent the occurrence of a situation in which a current flows backward from a large number of sense amplifiers 3 toward the step-down circuit 1, whereby the step-down voltage VDL becomes unbalanced. It is possible to prevent a situation where the level is raised to a desired level. Therefore,
It is possible to prevent the reliability of the circuit for lowering the operating voltage from being lowered due to the stepped-up voltage VDL being undesirably raised in level. For example, the arrival voltage of the data line due to the amplifying operation of the sense amplifier 3 is increased by the rise of the step-down voltage VDL, so that the potential difference between the selection level of the word line and the high level of the data line is reduced, and the data is transferred to the memory cell. It is possible to prevent that the high level voltage of the data line cannot be applied to the storage capacitor SC in the high level writing of. Further, if the voltage reached by the sense amplifier 3 on the data line is increased due to an undesired increase in the step-down voltage VDL, the pre-level corresponding to the initial level of the data line equalized during the chip non-selection period is correspondingly increased. When the charge level also rises and the data written in such a state is read, it is possible to prevent the high-level read voltage margin from the precharge level from being reduced. Further, when the booster circuit 2 forming the word line selection level uses the step-down voltage VDL, an undesired increase in the step-down voltage VDL raises the word line selection level VPP to select the memory cell MC.
There is no possibility of damaging the gate oxide film of the S transistor Q1.

FIG. 3 shows another example of a circuit for generating control signals φSAN, φSA1B, φSA2B for controlling the sense amplifier. In the circuit shown in the figure, the control signal φSAEB is applied to one input terminal of a 2-input NOR gate 20.
Is provided, and a delay circuit 21 for determining the overdrive time is arranged between one input terminal and the other input terminal of the NOR gate 20. The control signal φS
AN is formed by inverting the control signal φSAEB by the CMOS inverter 22, the control signal φSA1B is formed by inverting the output of the NOR gate 20 by the CMOS inverter 23, and the control signal φSA2B is the output of the delay circuit 21 by CM.
It is formed by being inverted by the OS inverter 24. The control signals φSAN, φSA1B, and φSA2B having the waveforms shown in FIG. 2 can be basically formed also by the logical configuration shown in FIG. In particular, in the case of FIG. 3, the delay circuit 21 includes CMOS inverters INV0, INV1, IN of odd stages.
It is composed of a series circuit of V3 and CR delay circuit 25. The CR delay circuit 25 is a delay element composed of passive circuit elements such as a capacitive element and a resistive element, which is different from the CMOS inverter, and its delay time has no negative dependence on the power supply voltage. In the case where the delay circuit 12 shown in FIG. 1 is composed of only CMOS inverters and the power supply voltage dependency of the delay time is too large and inconvenient, the delay time does not depend on the power supply voltage CR as shown in FIG.
It is advisable to combine the delay circuit and the CMOS inverter to form the delay circuit. Note that it is naturally possible to employ the delay circuit 21 of FIG. 3 also in the logical configuration of FIG.

Needless to say, the above-described example is merely an example, and various modifications can be made without departing from the gist of the present invention. For example, the current source in the step-down unit 10 is not limited to the configuration in which the negative feedback control is performed by using the operational amplifier. Further, the memory mat structure of the DRAM, the logical structure of the mat selection, the number of parallel input / output bits of data, etc. are not limited to the above-mentioned embodiment, and can be appropriately changed. In addition, control signals φSAN, φSA1B, φSA for controlling sense amplifiers
The logical configuration of the circuit that generates 2B is not limited to those shown in FIGS. 1 and 3, and can be changed as appropriate. Also as the delay means, the MOS circuit is not limited to the CNOS inverter, but can be constituted by a NAND gate, a NOR gate or the like. The circuit whose delay time has a negative dependence on the power supply voltage is not limited to the circuit having only the MOS transistor, and may be configured to include other circuit elements such as a bipolar transistor.

FIG. 5 shows a circuit according to another example for supplying operating power to the drive lines SDN and SDP of the sense amplifier 3. In FIG. 5 and FIG. 1, the same parts are designated by the same reference numerals.

The drive line SDN is an N channel type M
The drive line SDP is connected to the common drain of the OS transistors Q9 and Q10, and the drive line SDP is connected to the common drain of the P-channel MOS transistors Q13 and Q14.
In the same figure, the sense amplifier 3 for one column is representatively shown, but the drive line SD representatively shown in the figure is shown.
N and SDP are generic names of drive lines SDN and SDP for all sense amplifiers 3 included in the DRAM of this embodiment. The drive line SDN has a control signal φS.
The ground potential VSS is supplied through an N-channel MOS transistor Q40 which is switch-controlled by AN.
An external power supply voltage VDD is supplied to the drive line SDP via a P-channel type MOS transistor Q41 which is switch-controlled by a control signal φSAP1B, and
The step-down voltage VD is supplied via an N-channel type MOS transistor Q42 'which is switch-controlled by the control signal φSAN2.
L is supplied. Control signals φSAN, φSAP1B, φ
SAN2 is output from the timing controller TG.

Control signals φSAN, φSAP1B, φSA
The circuit forming N2 is shown as part of the timing controller TG shown in FIG. That is, the control signal φSAEB that defines the activation period of the sense amplifier 3
In a low level period (which is an internal control signal of the timing controller TG and is not shown in FIG. 1), the control signal φSAP1B is first activated, and then the control signal φSAN2 is activated. An input type NAND gate 10 and a NOR gate 11 are provided, one input terminals of the NAND gate 10 and the NOR gate 11 are coupled to each other, and an odd number of CMOs are provided between the one input terminal and the other input terminal of the NAND gate 10.
A delay circuit 12 in which S inverters INV0 to INVi (i = 2n−1) are connected in series is arranged. The other input terminal of the NAND gate 10 is supplied with the control signal φSAEB through the CMOS inverter 13, and the NOR gate 11
The control signal φSAEB is supplied to the other input terminal of the. The control signal φSAP1B is output from the NAND gate 10, and the control signal φSAN is the control signal φSAEB.
Are formed through CMOS inverters 15, 16 and 17 of three stages in series. The output φSA2 of the NOR gate 11 is supplied to the level conversion circuit 6, and the output of the level conversion circuit 6 is used as the control signal φSAN2.

The level conversion circuit 6 is a circuit for enlarging the signal amplitude of the input signal and transmitting it to the output, and a series circuit of P-channel type MOS transistors Q60 and Q61 and an N-channel type MOS transistor Q62 and a P-channel type. A series circuit of the MOS transistors Q63 and Q64 and the N-channel MOS transistor Q65 is arranged in parallel between the boosted voltage VPP and the ground potential VSS.
The input signal φSA2 is supplied to the gates of the MOS transistors Q61, Q62, and the MOS transistors Q64, Q
The input signal φSA2 is inverted by the CMOS inverter 18 and supplied to the gate of 65. MOS transistor Q
The connection point of 61 and Q62 is connected to the gate of MOS transistor Q63, and the connection point of MOS transistors Q64 and Q65 is connected to the gate of MOS transistor Q60. The signal amplitude of the input signal φSA2 is the ground potential VSS and the power supply voltage V
It is the potential difference from DD. That is, the operating power sources of the NOR gate 11 are VDD and VSS. Control signal φSA2
Is set to the level of the power supply voltage VDD, the
ON state of transistor Q62, MOS transistor 6
5, the control signal φSAN2 changes to the boosted voltage VPP depending on the off state of the MOS transistors Q63 and Q64.
To the level of. Control signal φSA2 is ground potential VSS
Control signal φSAN2 is set to the level of ground potential VSS by the off state of MOS transistor Q62, the on state of MOS transistor 65, the on state of MOS transistors Q60 and Q61, and the off state of MOS transistor Q63. . Therefore, the input signal φSA2 whose signal amplitude is the potential difference between the ground potential VSS and the power supply voltage VDD is the output signal φSAN2 whose signal amplitude is the potential difference between the ground potential VSS and the boosted voltage VPP.
And the logical values of both signals φSA2 and φSAN2 are matched. The boosted voltage VPP is set to 4.0V, for example.

FIG. 6 shows waveforms of control signals φSAN, φSAP1B, φSAN2 for supplying operating power to drive lines SDN and SDP by the circuit configuration of FIG.

When the control signal φSAEB defining the activation period of the sense amplifier 3 is changed to the low level active level, first, the control signal φSAP1B is changed to the low level (ground potential VSS level) and the MOS transistor Q41. The power supply voltage VDD is supplied to the drive line SDP via. As a result, P of the sense amplifier 3
Since the currents supplied to the channel type MOS transistors Q13 and Q14 are relatively large, the minute potential difference appearing on the complementary data lines DL0 and DL0B due to the memory cell selecting operation is quickly amplified. Then, control signal φSAP
1B is inverted to the high level (the level of the power supply voltage VDD) and the control signal φSAN2 is set to the high level (the level of the boost voltage VPP), so that the step-down voltage VDL is applied to the drive line SDP via the MOS transistor Q42 '. Supplied. The control signal φSAN is the control signal φS
It is set to high level in synchronization with the low level period of AEB. As a result, the arrival levels of the complementary data lines driven by the sense amplifier 3 are defined such that one is the ground potential VSS and the other is the step-down voltage VDL.

At this time, the MOS transistor Q42 'is an N-channel type, and the high level of the control signal φSAN2 for controlling it to an ON state is a voltage higher than its drain voltage (step-down voltage VDL), for example, the word line boost voltage. Since it is set to VPP, the gate-source voltage of the MOS transistor Q42 'is made relatively large. The carrier mobility of the N-channel MOS transistor is about three times higher than that of the P-channel MOS transistor. Therefore, using the P-channel type MOS transistor Q42 as in the embodiment of FIG.
A relatively large current supply capability can be obtained in the MOS transistor Q42 ', as compared with the case where it is controlled to the ON state by the ground potential VSS. As a result, the sense amplifier 3 can operate at high speed even when the operating voltage is lowered.

N-channel type MOS transistor Q4
If the gate voltage of 2'is the drain voltage (step-down voltage VD
L), this MOS transistor Q4
The source voltage of 2'is lower than the gate voltage by the threshold voltage of the MOS transistor Q42 '. In order to reduce this voltage drop, the gate voltage is set higher than the drain voltage in the embodiment of the present invention. When the gate voltage is set to a voltage equal to or higher than the sum of the drain voltage and the threshold voltage, the decrease in the threshold voltage can be completely canceled, so that the voltage (VDL) reduced in voltage is supplied to the sense amplifier. It is possible to more effectively prevent the deterioration of the ability.

For example, VSS = 0V, VDD = 3.3V,
Assuming that VDL = 2.2V and VPP = 4.0V, the N-channel type MOS transistor Q42 ′ has VPP = 4.V.
The gate-source voltage at the time of turning on by the gate voltage of 0V is 1.8V, and it is assumed that the MOS transistor Q4
The gate-source voltage is 2.2V when 2 ′ is a P-channel type and is turned on with a gate voltage of 0V.
Although the gate-source voltage of the P-channel type MOS transistor is apparently higher, even in that case, considering the difference in carrier mobility, the MOS transistor Q42 'of the N-channel type is relatively larger. The current supply capacity can be obtained. In particular, the MOS transistor Q
When 42 ′ is a P-channel type and is turned on at the ground potential VSS, the gate-source voltage (VGS) = the step-down voltage VDL, and VGS is reduced as the operating voltage of the sense amplifier 3 is lowered. Take a trend. On the other hand, in the configuration in which the N-channel MOS transistor Q42 'is turned on by the boosted voltage VPP as in this embodiment, the N-channel MOS transistor Q42' is provided.
The gate-source voltage for turning on the
It can be determined according to factors such as the breakdown voltage of the gate oxide film of the S-transistor Q42 ', and VGS decreases as the operating voltage decreases.
Does not tend to be smaller. Therefore, in the situation where it is expected that the operating voltage will be lowered in the future, the MOS
The configuration in which the transistor Q42 ′ is an N-channel type and is controlled to be in the ON state by the boosted voltage is excellent in coping with speeding up of the sense amplifier. Further, by generating the switch control signal φSAN2 of the MOS transistor Q42 'using the output VPP of the booster circuit 2 forming the word line selection level, the circuit scale can be increased as much as possible when the operation speed of the sense amplifier 3 is increased. You can hold it down.

In the example of FIG. 5 as well, similar to the embodiment of FIG. 1, by using the overdrive voltage (VDD) as the power supply voltage of the inverter forming the delay circuit 12, it is possible to ensure a simple configuration. The overdrive time can be controlled.

Therefore, according to the example shown in FIG. 5, in the overdrive technique, the overdrive time can be controlled according to the overdrive voltage (VDD) and the step-down voltage supply MOS transistor Q42 'can be controlled.
Since the current supply capacity is high, the level of the data line can be amplified at a high speed and reliably to a desired level.

FIG. 7 shows another example for supplying the step-down voltage VDL to the drive line SDP of the sense amplifier 3. In this example, a P-channel type MOS transistor Q43 is adopted in place of the MOS transistor Q42 ', and the signal amplitude for switch control of the MOS transistor Q43 is set within the range between the substrate bias voltage VBB and the power supply voltage VDD, whereby the MOS transistor Q43' is selected. This is intended to make the gate-source voltage of Q43 relatively large. In FIG. 4, the switching control signal of the MOS transistor Q43 is φSAP2B, and its signal amplitude is the potential difference between the power supply voltage VDD and the substrate bias voltage VBB.

In FIG. 7, 7 is a level conversion circuit.
This level conversion circuit 7 outputs the control signal φSA2 to CM.
A circuit for inverting and inputting with the OS inverter 19, enlarging the signal amplitude of the input signal and transmitting to the output, a series circuit of a P-channel type MOS transistor Q70 and N-channel type MOS transistors Q71, Q72, and a P-channel A series circuit of a MOS transistor Q73 and N-channel MOS transistors Q74 and Q75 is arranged in parallel between the power supply voltage VDD and the substrate bias voltage VBB. The inverted signals of the input signal φSA2 are supplied to the gates of the MOS transistors Q70 and Q71, and the input signal φSA2 is supplied to the gates of the MOS transistors Q73 and Q74.
Are supplied via the CMOS inverters 19 and 20.
The connecting point of the MOS transistors Q70 and Q71 is connected to the gate of the MOS transistor Q75 and the MOS transistor Q7.
The connection point of 3 and Q74 is connected to the gate of the MOS transistor Q72. The signal amplitude of the input signal φSA2 is the potential difference between the ground potential VSS and the power supply voltage VDD (the operating power supplies of the inverters 19 and 20 are VSS and VDD), and when the control signal φSA2 is at the level of the power supply voltage VDD. ON state of the MOS transistor Q70, MOS
OFF state of transistor 73, MOS transistor Q7
4, control signal φSAP2B depending on the ON state of Q75
Is set to the level of the substrate bias voltage VBB. When the control signal φSA2 is set to the level of the ground potential VSS, the MOS
OFF state of transistor Q70, MOS transistor 7
The control signal φSAP2B is set to the level of the power supply voltage VDD depending on the ON state of 1, the ON states of the MOS transistors Q73 and Q72, and the OFF state of the MOS transistor Q75. Therefore, the signal amplitude is the potential difference between the ground potential VSS and the power supply voltage VDD, and the logical value of the input signal φSA2 is inverted, so that the signal amplitude is the potential difference between the substrate bias voltage VBB and the power supply voltage VDD.
Converted to B.

With the configuration of FIG. 7, the drive line SDP
P-channel type MOS to supply the step-down voltage VDL to the
Even if the transistor Q43 is adopted, the signal amplitude for switch control of the transistor Q43 is set to the substrate bias voltage VBB and the power supply voltage V
By setting the range to DD, the gate-source voltage of the MOS transistor Q43 can be made relatively large,
As a result, the sense amplifier 3 can operate at high speed even when the operating voltage is lowered. However, in a situation where the operating voltage is being lowered, the gate-source voltage of the MOS transistor Q43 tends to be reduced as the step-down voltage VDL is lowered. By using the negative voltage formed by the substrate bias voltage as the substrate bias voltage VBB, it is possible to suppress the increase in the circuit scale as much as possible when the operating speed of the sense amplifier 3 is increased.

Needless to say, the above example can be variously modified without departing from the scope of the present invention. For example, in the above example, the case where the sense amplifier is overdriven has been described, but Q42 and Q43 are also related to the MOS transistor that supplies the operating voltage to the drive line on the high potential side of the sense amplifier when the overdrive is not adopted. Configurations can be employed as well. Furthermore, when adopting overdrive, MO
The configuration relating to Q42 and Q43 can be similarly adopted for the S transistor Q41. Also, DRAM
The memory mat structure, the logic structure for mat selection, the number of parallel input / output bits of data, etc. are not limited to those in the above embodiment, and can be changed appropriately. The logic configuration of the circuit that generates the control signals φSAN, φSAP1B, and φSAN2 for controlling the sense amplifier is not limited to that shown in FIG. 1 and can be changed as appropriate.

In the above description, the invention made mainly by the present inventor is the field of application behind which DRA is applied.
However, the present invention is not limited to this, and the present invention is applied to a data processing LSI such as a synchronous DRAM, a pseudo static RAM, and a microcomputer which are operated in synchronization with a clock signal. The present invention can be widely applied to semiconductor integrated circuits having a differential amplifier circuit for a receiver for data transmission such as those memories.

[0076]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, when the overdrive technique is adopted as a drive system for a differential amplifier circuit such as a sense amplifier, the delay time of the delay means that defines the overdrive time has a negative dependence on the external power supply voltage. With this, when the supplied external power supply voltage is at the upper limit level of the allowable range, or when a particularly high external power supply voltage is supplied for an operation margin test on the power supply voltage side, the delay means delays. The time is relatively shortened, in other words, the overdrive time (ODT) is relatively shortened, and the time when the relatively high level external power supply voltage is supplied to the drive line (SDP) of the differential amplifier circuit. Is shortened. As a result, it is possible to prevent the differential amplifier circuit from being overdriven excessively by the external power supply voltage having a relatively high level.

Since it is possible to prevent excessive overdrive to the differential amplifier circuit, it is possible to prevent a situation in which a current flows backward from a large number of differential amplifier circuits toward the step-down circuit, which reduces the operating voltage. It is possible to prevent the step-down voltage (VDL) supplied to the voltage-converted circuit, for example, the memory array of the DRAM from being undesirably raised in level. Therefore, it is possible to prevent the reliability of the circuit aimed at lowering the operating voltage from being lowered due to the step-down voltage being undesirably raised in level. For example, the reaching voltage of the data line due to the amplifying operation of the differential amplifier circuit such as the sense amplifier is increased by the increase of the step-down voltage, so that the potential difference between the selection level of the word line and the high level of the data line is reduced. It is possible to prevent a situation in which the high level voltage of the data line cannot be applied to the storage capacitor during the high level write to the memory cell. Further, if the arrival voltage of the data line by the differential amplifier circuit such as the sense amplifier is increased due to the undesired increase of the step-down voltage, the precharge level of the equalized data line also increases accordingly. When the data written in such a state is read, it is possible to prevent the read voltage margin at the high level with respect to the precharge level from being reduced. In addition, when the booster circuit that forms the word line selection level uses the stepped down voltage, an undesired increase in the stepped down voltage raises the word line selection level and damages the gate oxide film of the memory cell selection transistor. There is no possibility of causing it.

A MOS transistor circuit such as a CMOS inverter is constructed by using a delay element composed of a passive element such as a CR delay circuit having no power supply voltage dependence on the delay time together with a MOS transistor circuit to form the delay means. It is possible to deal with the case where the dependency of the delay time on the power supply voltage is too large when trying to secure the required delay time by itself. It becomes easy to make.

The MOS transistor for supplying the power supply voltage or the step-down voltage to the drive line on the high potential side of the differential amplifier circuit is an N-channel type, and the amplitude of the switching control signal thereof is set to a voltage higher than the power supply voltage. It is possible to prevent the gate-source voltage of the MOS transistor for supplying operating power to the drive line on the high potential side from being reduced as the operating voltage is lowered, and differential amplification is performed even in the situation where the operating voltage is lowered. The circuit can be operated at high speed.

Even when the MOS transistor for supplying the operating power supply to the drive line on the high potential side of the differential amplifier circuit is of the P-channel type, the signal amplitude for switch control thereof is in the range of the negative voltage and the power supply voltage. If so, the MO
The gate-source voltage of the S transistor can be made relatively large, and as a result, the differential amplifier circuit can be operated at high speed even when the operating voltage is lowered.

As the boosted voltage for defining the signal amplitude for switch controlling the N-channel type MOS transistor for supplying the operating power to the drive line on the high potential side,
The output of the booster circuit forming the word line selection level is used, and the operating power is supplied to the drive line
By using the negative voltage formed by the substrate bias voltage generating circuit as the negative voltage for defining the signal amplitude for controlling the switching of the channel type MOS transistor, the circuit scale can be increased when the operating speed of the differential amplifier circuit is increased. The increase can be suppressed as much as possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example for driving and controlling a sense amplifier in an overdrive format.

FIG. 2 is a waveform diagram of an example of a control signal for driving and controlling the sense amplifier shown in FIG.

FIG. 3 is a logic circuit diagram showing another generation logic of a control signal for driving a sense amplifier in an overdrive format.

FIG. 4 is a circuit diagram showing an example of a delay circuit.

FIG. 5: Sense amplifier drive lines SDN, SDP
FIG. 3 is a circuit diagram showing an example for supplying operating power to

6 is a drive line SD according to the circuit configuration of FIG.
Control signal φ for supplying operating power to N and SDP
It is a wave form diagram of SAN, φSAP1B, φSAN2.

FIG. 7 is a circuit diagram showing another example for supplying the step-down voltage VDL to the drive line SDP of the sense amplifier.

FIG. 8 is an overall block diagram of a DRAM according to an example of the present invention.

9 is a partial circuit diagram of a memory mat, a sense amplifier block, and a column switch circuit block of the DRAM shown in FIG.

[Explanation of symbols]

MARY0, MARY1 memory array MMAT0 to MMAT7 memory mats SA01, SA23, SA45, SA67 sense amplifier block WD0 to WD7 word driver XD0 to XD7 row address decoder YD column address decoder TG timing controller DL0, DL0B, DL1, DL1B complementary data lines WLi, WL (i-1) Word line MC Dynamic memory cell Q17, Q18 Precharge MOS transistor Q21 Equalize MOS transistor VDL Step-down voltage VDD External power supply voltage VSS Ground voltage VPP Word line drive voltage VBB Substrate bias voltage 1 Step-down circuit AMP1 Operational amplifier Q50 Current source MOS transistor R1 High resistance Nout Output terminal 2 Booster circuit 3 Sense amplifier Q9, Q10 N channel type MO for sense amplifier configuration
S-transistors Q13, Q14 P-channel type M for sense amplifier configuration
OS transistor SDP, SDN Sense amplifier drive line Q41, Q42, Q42 ', Q43 MOS transistor for supplying operating power to SDP Q40 MOS transistor for supplying operating power to SDN φSA2B, φSA1B, φSAN, φSAN2, φS
AP1B, φSAP2B Sense amplifier control signal 12 Delay circuit INV0 to INVi CMOS inverter 21 Delay circuit INV1 to INV3 CMOS inverter 25 CR delay element 4 Precharge voltage forming circuit 1 5 Substrate bias voltage generating circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Tsutsuo Takahashi 2326 Imai, Ome City, Tokyo, Hitachi, Ltd. Device Development Center (72) Inventor Kubota, 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Arai Corp. 2326 Imai, Ome-shi, Tokyo Hitachi Device Development Center (72) Inventor Koichi Abe 2350 Miura-mura Kihara, Inashiki-gun, Ibaraki Japan Texus Instruments Co. Shunichi Sukegawa 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Prefecture, Japan Nippon Textile Instruments Co., Ltd.

Claims (33)

[Claims] 1. A differential amplifier circuit that amplifies a potential difference between complementary signal lines, and a first drive control signal that supplies a first drive voltage as an operating power supply of the differential amplifier circuit.
A second drive voltage which is activated and has a lower level than the first drive voltage in response to the first drive control signal being deactivated after the first drive control signal is activated. And a control circuit that forms a second drive control signal to be supplied as an operating power supply of the differential amplifier circuit, the control circuit including a delay circuit that defines a period during which the first drive control signal is activated. The delay circuit includes an inverter circuit that receives the first drive voltage as an operating power supply, and a period during which the first drive control signal is activated is negatively dependent on the first drive voltage. A semiconductor integrated circuit having characteristics. 2. The semiconductor integrated circuit according to claim 1, wherein the inverter circuit is a CMOS inverter circuit. 3. A plurality of memory cells whose selection terminals are coupled to word lines, complementary signal lines connected to the data input / output terminals of the memory cells, and a differential amplifier circuit for amplifying the potential difference between the complementary signal lines. A step-down circuit for stepping down an external power supply voltage supplied from the outside to form a step-down voltage equal to or lower than the selection level of the word line; The first drive control signal to be supplied to the dynamic amplifier circuit is formed, and is activated in response to the deactivation of the first drive control signal after the activation of the first drive control signal. And a control circuit that forms a second drive control signal for supplying a step-down voltage generated by the step-down circuit as an operating power supply of a differential amplifier circuit, the control circuit activating the first drive control signal. Conversion A delay circuit that defines a period during which the first drive control signal is activated, and the delay circuit includes an inverter circuit that receives the external power supply voltage as an operating power supply. A semiconductor integrated circuit characterized by having a negative dependence on. 4. The semiconductor integrated circuit according to claim 3, wherein the step-down circuit is a circuit that forms the step-down voltage at a series connection point of a current source and a high resistance. 5. The memory cell is a dynamic type memory cell, and a circuit that forms a voltage that is approximately half the voltage of the output terminal of the step-down circuit as a precharge voltage for the complementary signal line and the complementary signal line. 7. An equalizing circuit that selectively conducts electricity, and a precharge circuit that supplies the precharge voltage to the complementary signal line in response to the conduction timing of the complementary signal line by the equalizing circuit. 4. The semiconductor integrated circuit according to 4. 6. A CMOS latch circuit comprising a pair of data lines, a pair of P-channel type MOS transistors and a pair of N-channel type MOS transistors, and a sense amplifier for amplifying a potential difference between the pair of data lines, A first terminal for receiving one voltage, a second terminal for receiving a second voltage lower than the first voltage, a pair of sources commonly coupled in the pair of P-channel MOS transistors, and the first terminal A first switch MOS transistor, a second switch MOS transistor provided between the pair of commonly coupled sources and the second terminal, and the first switch MOS transistor is turned on in a first period. During the second period after the first period, the first switch MOS transistor is turned off and the second switch MOS transistor is turned off. A control circuit that controls the first and second switch MOS transistors so that the MOS transistor is turned on, the control circuit includes a delay circuit that defines the first period, and the delay circuit A semiconductor integrated circuit comprising an inverter circuit receiving the first voltage as an operating power supply. 7. The first and second switch MOS transistors are coupled in parallel, and the second switch MOS transistors are connected in the first period.
7. The semiconductor integrated circuit according to claim 6, wherein the switch MOS transistor is turned off. 8. The semiconductor integrated circuit according to claim 7, wherein the inverter circuit is a CMOS inverter circuit. 9. The semiconductor integrated circuit according to claim 8, wherein the first terminal is an external power supply voltage. 10. The pair of P-channel type MOS transistors have a pair of gates receiving a potential of the pair of data lines and a pair of drains, and a drain of one MOS transistor of the pair of P-channel type MOS transistors. The other gate is coupled to each other, and the pair of N-channel type MOS transistors have a pair of sources commonly coupled, a pair of gates for receiving the potentials of the pair of data lines, and a pair of drains. One of a pair of N-channel MOS transistors
10. The semiconductor integrated circuit according to claim 9, wherein the drain and the other gate of the transistor are coupled to each other. 11. A differential amplifier circuit that amplifies a potential difference between complementary signal lines, and a first switching MO that supplies a first drive voltage to a drive line on the high potential side of the differential amplifier circuit.
An S transistor, a second switching MOS transistor that supplies a second drive voltage having a level lower than the first drive voltage to the drive line, and the first first in the activation period of the differential amplifier circuit. A first control voltage is supplied to the drive line via the switching MOS transistor, and then a second control voltage is supplied to the drive line via the second switching MOS transistor.
The first switching MOS transistor is a P-channel type, the high level potential of its switching control signal is the potential of the first drive voltage, and the second switching MOS transistor is an N-channel type and its switching control is performed. A semiconductor integrated circuit characterized in that a high-level potential of a signal is a potential boosted higher than a second drive voltage. 12. A step-down circuit for stepping down a power supply voltage supplied from the outside to form a step-down voltage, a plurality of memory cells each having a select terminal coupled to a word line, and a data input / output terminal of the memory cell. A complementary signal line to be connected, a differential amplifier circuit that amplifies a potential difference between the complementary signal lines, a first switching MOS transistor that supplies the power supply voltage to a drive line on the high potential side of the differential amplifier circuit, A power supply voltage is first supplied to the drive line via the second switching MOS transistor that supplies the step-down voltage to the drive line and the first switching MOS transistor during the activation period of the differential amplifier circuit, and then the second And a switching control signal generating means for supplying a step-down voltage to the drive line via the switching MOS transistor. Offer, the first switching MO
The S-transistor is a P-channel type, and the high level potential of the switching control signal thereof is the potential of the power supply voltage supplied from the outside, and the second switching MO
A semiconductor integrated circuit characterized in that the S-transistor is an N-channel type and the high level potential of the switching control signal is a potential boosted higher than the step-down voltage. 13. The increased potential is the same as or higher than the reduced voltage by a threshold voltage of the second switching MOS transistor. Semiconductor integrated circuit. 14. The semiconductor integrated circuit according to claim 13, further comprising a booster circuit that receives the stepped-down voltage and outputs the boosted potential, and an output level of the booster circuit is a word line selection level. circuit. 15. A step-down circuit for stepping down a power supply voltage supplied from the outside to form a step-down voltage, a plurality of memory cells each having a select terminal coupled to a word line, and a data input / output terminal of the memory cell. A complementary signal line to be connected, a differential amplifier circuit that amplifies a potential difference between the complementary signal lines, a first switching MOS transistor that supplies the power supply voltage to a drive line on the high potential side of the differential amplifier circuit, A power supply voltage is first supplied to the drive line via the second switching MOS transistor that supplies the step-down voltage to the drive line and the first switching MOS transistor during the activation period of the differential amplifier circuit, and then the second Switching control signal generating means for supplying a step-down voltage to the drive line via the switching MOS transistor of And a negative voltage generation circuit having a negative polarity with respect to a power supply voltage supplied from the outside, the first switching MOS transistor is a P-channel type, and the high level voltage of the switching control signal is the external voltage. The semiconductor integrated circuit is characterized in that the second switching MOS transistor is a P-channel type and the low level voltage of the switching control signal is the negative voltage level. . 16. The semiconductor integrated circuit according to claim 15, wherein the negative voltage generating circuit is a substrate bias voltage generating circuit. 17. A step-down circuit for stepping down a power supply voltage supplied from the outside to form a step-down voltage, a step-up circuit for forming a selection level of a word line, and a plurality of memories having selection terminals coupled to the word line. Cell, a complementary signal line connected to the data input / output terminal of the memory cell, a differential amplifier circuit for amplifying the potential difference between the complementary signal lines, and the step-down voltage on the drive line on the high potential side of the differential amplifier circuit. And a switching control signal generating means for supplying a step-down voltage to the drive line via the switching MOS transistor during the activation period of the differential amplifier circuit, the switching MOS transistor being an N channel Type, the low level potential of the switching control signal is the ground potential, and the high level potential is the booster circuit. 2. A semiconductor integrated circuit having a word line selection level potential formed in 1. 18. A step-down circuit for stepping down a power supply voltage supplied from the outside to form a step-down voltage, a plurality of memory cells each having a select terminal coupled to a word line, and a data input / output terminal of the memory cell. A complementary signal line to be connected, a differential amplifier circuit that amplifies a potential difference between the complementary signal lines, a second switching MOS transistor that supplies a step-down voltage to a drive line on the high potential side of the differential amplifier circuit, and the difference Provided are means for generating a switching control signal for supplying a step-down voltage to a drive line via a switching MOS transistor during the activation period of the dynamic amplifier circuit, and a circuit for generating a substrate bias voltage having a negative polarity with respect to the power supply voltage. The switching MOS transistor is a P-channel type, and the low level potential of the switching control signal is the substrate bias voltage. A semiconductor integrated circuit, wherein the high-level potential is a potential equal to or higher than the step-down voltage. 19. A CMOS latch circuit comprising a pair of data lines, a pair of P-channel type MOS transistors and a pair of N-channel type MOS transistors, and a sense amplifier for amplifying a potential difference between the pair of data lines, A first terminal for receiving one voltage, a second terminal for receiving a second voltage lower than the first voltage, a pair of sources commonly coupled in the pair of P-channel MOS transistors, and the first terminal A first switch MOS transistor, an N-channel type second switch MOS transistor provided between the pair of commonly coupled sources and the second terminal, and the first switch MOS transistor in a first period. Is turned on, and the first switch MOS transistor is turned off in the second period after the first period. And a control circuit for outputting a signal to the gates of the first and second switch MOS transistors so that the second switch MOS transistor is turned on, and the gate of the second switch MOS transistor in the second period. The semiconductor integrated circuit is characterized in that the voltage is higher than the second voltage. 20. The control circuit includes a delay circuit that defines the first period, and fluctuations in the first period have a negative dependence on fluctuations in the first voltage. 19. The semiconductor integrated circuit according to item 19. 21. The semiconductor integrated circuit according to claim 20, wherein the delay circuit includes an inverter circuit that receives the first voltage as an operating power supply. 22. In the second period, the gate voltage of the second switch MOS transistor is equal to or higher than the sum of the second voltage and the threshold voltage of the second switch MOS transistor. 22. The semiconductor integrated circuit according to claim 21, wherein: 23. The semiconductor integrated circuit according to claim 22, wherein the first and second switch MOS transistors are coupled in parallel and the second switch MOS transistor is turned off during the first period. circuit. 24. A pair of data lines, a plurality of word lines, a plurality of dynamic memory cells respectively coupled to one of the pair of data lines and one of the plurality of word lines, and a pair of P channels. Type CMOS transistor and a pair of N-channel type MOS transistors, a sense amplifier for amplifying a potential difference between the pair of data lines, a first terminal for receiving a first voltage, and a first voltage higher than the first voltage A second terminal for receiving a low second voltage; a step-down circuit for stepping down the first voltage to output the second voltage; a pair of sources commonly connected in the pair of P-channel MOS transistors; A first switch MOS transistor provided between the first terminal and a terminal, and an N provided between the pair of commonly coupled sources and the second terminal. A channel-type second switch MOS transistor, the first switch MOS transistor is turned on in a first period, the first switch MOS transistor is turned off, and the second switch is turned on in a second period after the first period. A control circuit that outputs a signal to the gates of the first and second switch MOS transistors so that the MOS transistor is turned on; and a booster circuit that boosts the second voltage and outputs a boosted voltage, In the second period, the boosted voltage is the second switch M.
A semiconductor integrated circuit which is supplied to a gate of an OS transistor. 25. The semiconductor integrated circuit according to claim 24, wherein the boosted voltage is supplied to a selected word line. 26. The semiconductor according to claim 25, wherein the boosted voltage is equal to or higher than a voltage boosted from the second voltage by a threshold value of the second switch MOS transistor. Integrated circuit. 27. The semiconductor integrated circuit according to claim 26, wherein the first terminal is an external power supply voltage terminal. 28. The control circuit includes a delay circuit that defines the first period, and the fluctuation of the first period has a negative dependence on the fluctuation of the first voltage. 27. The semiconductor integrated circuit according to 27. 29. The semiconductor integrated circuit according to claim 28, wherein the delay circuit includes an inverter circuit receiving the first voltage as an operating power supply. 30. The semiconductor integrated circuit according to claim 29, wherein the first and second switch MOS transistors are coupled in parallel, and the second switch MOS transistor is turned off during the first period. circuit. 31. The pair of P-channel type MOS transistors have a pair of gates receiving a potential of the pair of data lines and a pair of drains, and a drain of one MOS transistor of the pair of P-channel type MOS transistors. The other gate is coupled to each other, and the pair of N-channel type MOS transistors have a pair of sources commonly coupled, a pair of gates for receiving the potentials of the pair of data lines, and a pair of drains. One of a pair of N-channel MOS transistors
31. The semiconductor integrated circuit according to claim 30, wherein the drain and the other gate of the transistor are coupled to each other. 32. A CMOS latch circuit comprising a pair of data lines, a pair of P-channel type MOS transistors and a pair of N-channel type MOS transistors, and a sense amplifier for amplifying a potential difference between the pair of data lines, A terminal for receiving a driving voltage for the high-level side data line of the pair of data lines, a pair of sources commonly coupled in the pair of P-channel MOS transistors, a source coupled to the terminals, and a control signal. An N-channel switch MOS transistor having a gate for receiving the control signal, wherein a high level voltage of the control signal is higher than the drive voltage. 33. The high level voltage of the control signal is equal to or higher than the sum of the high level voltage and the threshold voltage of the switch MOS transistor. The semiconductor integrated circuit described.