JP3908392B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and is effective for use in a test technique for a circuit having a boost voltage, a substrate back bias voltage, and an internal buck voltage, such as a dynamic RAM (random access memory). It is about technology.
[0002]
[Prior art]
Japanese Patent Laid-Open No. 3-214669 is an example of a dynamic RAM provided with an internal power supply circuit that receives a power supply voltage supplied from an external terminal and generates an internal voltage necessary for circuit operation.
[0003]
[Problems to be solved by the invention]
In a dynamic RAM, it is advantageous to make the internal voltage constant in order to meet demands for higher speed, lower power consumption, higher performance, and the like. In the screening test, the conditions such as the power supply voltage, input / output voltage, temperature, and timing are generally combined within the specification range. Actually, this is performed by giving some margin to the specification in order to absorb apparatus errors such as a tester and variations in the reproducibility of characteristics. In particular, since the power supply voltage condition has a relatively large influence on the characteristics, a margin of about several percent is given to the specification. However, since the internal voltage is constant so as not to be affected by the power supply voltage supplied from the external terminal, it becomes impossible to perform a test with a margin that is more severe than in normal operation. It was found by the inventors of the present application.
[0004]
An object of the present invention is to provide a semiconductor integrated circuit device that realizes an efficient sorting test with a simple configuration while achieving high performance. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0005]
[Means for Solving the Problems]
  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, the firstA first voltage supplied from an external terminal ofOf the circuit supplied from the second external terminalGround potentialAndThe secondAn internal power supply circuit that forms an internal voltage different from one voltage;, InsideInternal circuit that operates with internal voltageWhenWithThe internal power supply circuit is a charge pump circuit that forms an internal voltage different from the first voltage or the ground potential, stops its operation upon receiving a detection signal at one level, and receives the detection signal at the other level. A charge pump circuit that resumes operation and a first signal that receives the internal voltage, detects that the internal voltage has reached a first internal voltage corresponding to the normal operation of the internal circuit, and outputs a detection signal of one level One level is detected by receiving a level detection circuit and an internal voltage, and the internal voltage reaches a second internal voltage higher than the first internal voltage in consideration of an operation margin corresponding to a test operation of the internal circuit. The second level detection circuit for outputting the detection signal and the internal voltage received the internal voltage, and the internal voltage reached a third internal voltage lower than the first internal voltage considering the operation margin corresponding to the test operation of the internal circuit This And a third level detection circuit that outputs a detection signal of one level, and the detection signal from the first level detection circuit is supplied to the charge pump circuit during normal operation, In the first test operation, the detection signal from the first level detection circuit is supplied to the charge pump circuit, and in the second test operation among the test operations, the detection signal from the third level detection circuit is supplied to the charge pump circuit. And
[0006]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram showing one embodiment of a booster circuit provided in a dynamic RAM to which the present invention is applied. The voltage generator VPP-gen. Although it is known per se, it is not shown in the figure, but comprises an oscillation circuit and a charge pump circuit that receives the oscillation pulse and forms a boosted voltage VPP higher than the power supply voltage VDD supplied from the external terminal. . The booster circuit is provided with a voltage detection circuit that controls the boosted voltage VPP to be a desired boosted voltage.
[0007]
When the boosted voltage VPP reaches a desired set voltage, the voltage detection circuit changes the detection signal VPSTOP to one level in response to the boosted voltage VPP reaching the desired set voltage, and the voltage generator VPP-gen. Is stopped. When the boosted voltage VPP falls below a desired set value due to an operation of an internal circuit using the boosted voltage VPP as an operating voltage or a leakage current, the voltage detection circuit causes the detection signal VPSTOP to go to the other level accordingly. The voltage generator VPP-gen. Restart the operation. In this way, the voltage detection circuit generates the detection signal VPSTOP corresponding to the change of the boost voltage VPP to generate the voltage generator VPP-gen. Is intermittently operated to maintain the boosted voltage VPP at a substantially desired constant voltage.
[0008]
In this embodiment, in order to evaluate the operation margin of the internal circuit, in addition to the boost voltage during normal operation, a function for setting two boost voltages for an operation test is added. The boosted voltage in the dynamic RAM sets a word line selection level as will be described later. A dynamic memory cell is composed of an address selection MOSFET and a storage capacitor. The address selection MOSFET functions as a switch to connect the storage capacitor and the bit line, and read by moving charges between the bit line and the storage capacitor. Or write.
[0009]
In order to turn on the address selection MOSFET, it is necessary to increase the gate voltage by an effective threshold voltage with respect to the source potential. Therefore, in order to move charges between the bit line and the storage capacitor, it is necessary to make the gate voltage of the address selection MOSFET higher than the threshold voltage with respect to the high level of the bit line. Therefore, the selection level of the word line to which the gate of the address selection MOSFET is connected needs to be higher by the threshold voltage than the high level of the bit line.
[0010]
In this embodiment, the first boosted voltage corresponding to the normal operation, the second boosted voltage set higher than that, and the third boosted voltage set lower than the first boosted voltage 3 In order to enable switching of different boosted voltages, three voltage detection circuits corresponding to the respective boosted voltages are provided.
[0011]
The internal voltage VDL is a voltage that determines the high level of the bit line as an operating voltage of the sense amplifier as will be described later. Therefore, the boosted voltage VPP is detected with reference to the internal voltage VDL in order to make the boosted voltage VPP higher than the internal voltage VDL by a voltage corresponding to the threshold voltage of the address selection MOSFET. As voltage detection means, a threshold voltage between the gate and source of a P-channel MOSFET is used.
[0012]
The voltage detection circuit corresponding to the normal operation (NORMAL) includes P-channel MOSFETs 66 and 67 and an N-channel MOSFET 61. The MOSFET 66 is in the form of a diode with its gate and drain connected in common. In the MOSFET 66, the boosted voltage VPP is applied to the source, and the commonly connected gate and drain are connected to the source of the MOSFET 67. The internal voltage VDL is supplied to the gate of the MOSFET 67. The N-channel MOSFET 61 is not particularly limited, but operates as a high resistance element when a predetermined voltage is constantly applied to the gate.
[0013]
The MOSFETs 66 and 67 are formed in independent N-type well regions in order to prevent the effective threshold voltage from changing due to the substrate effect due to the potential difference between the source and the substrate. Connected with source. Thus, when VPP−VDL <2Vth, MOSFETs 66 and 67 are turned off, and the drain output of MOSFET Q61 is set to the low level. On the other hand, when VPP rises so that VPP-VDL> 2Vth, MOSFETs 66 and 67 are turned on, the drain output of MOSFET Q61 is raised from low level to high level, and the logic threshold voltage of gate circuit 70 is reached. The gate circuit 70 determines that the level is high. With such a detection operation, the voltage generator VPP-gen. Is controlled.
[0014]
A voltage detection circuit for raising (UP) the boosted voltage VPP compared to the normal operation (NORMAL) is composed of P-channel MOSFETs 63 to 65 and an N-channel MOSFET 60. The MOSFETs 63 and 64 have their gates and drains connected in common to form a diode and are connected in series. The boosted voltage VPP is applied to the source of the one MOSFET 63, and the drain of the other MOSFET 64 is connected to the source of the MOSFET 65. The internal voltage VDL is supplied to the gate of the MOSFET 65. The N-channel MOSFET 60 is not particularly limited, but operates as a high-resistance element when a predetermined voltage is constantly applied to the gate.
[0015]
The MOSFETs 63 to 65 are each formed in an independent N-type well region in order to prevent an effective threshold voltage from changing due to the substrate effect due to the potential difference between the source and the substrate. Are connected to their respective sources. Thereby, when VPP−VDL <3Vth, the MOSFETs 63 to 65 are turned off, and the drain output of the MOSFET Q60 is set to the low level. On the other hand, when VPP rises so that VPP−VDL> 3Vth, MOSFETs 63 to 65 are turned on, the drain output of MOSFET Q60 is raised from low level to high level, and the logic threshold voltage of gate circuit 69 is reached. The gate circuit 69 determines that the level is high. By such a detection operation, the voltage generator VPP-gen. Is controlled.
[0016]
A voltage detection circuit for lowering (DW) the boosted voltage VPP compared to the normal operation (NORMAL) is configured by a P-channel MOSFET 68 and an N-channel MOSFET 62. The boosted voltage VPP is applied to the source of the MOSFET 68, and the internal voltage VDL is supplied to the gate. The N-channel MOSFET 62 is not particularly limited, but operates as a high-resistance element when a predetermined voltage is constantly applied to the gate.
[0017]
In the MOSFET 68, the well region in which it is formed is connected to the source and the boosted voltage VPP is applied. Thus, when VPP−VDL <Vth, the MOSFET 68 is turned off, and the drain output of the MOSFET Q62 is set to the low level. On the other hand, when VPP rises so that VPP-VDL> Vth, MOSFET 68 is turned on, the drain output of MOSFET Q62 is raised from low level to high level, and when the logic threshold voltage of gate circuit 71 is reached, the gate The circuit 71 determines that the level is high. By such a detection operation, the voltage generator VPP-gen. Is controlled.
[0018]
In order to select and validate only one detection signal among the three voltage detection circuits as described above, in other words, one of the three boosted voltages VDL + Vth, VDL + 2Vth, and VDL + 3Vth can be selected. For this purpose, the control signals UP, NORMAL, and DW are supplied to the gate circuits 69, 70, and 71 corresponding to the above three detection circuits, and only one of them is set to the high level (logic 1). The
[0019]
During normal operation, the control signal NORMAL is set to a high level (logic 1), the gate circuit 70 opens the gate, the detection signals corresponding to the MOSFETs 66 and 67 become valid, and the boost voltage VPP≈VDL + 2Vth is set. When the control signal UP is set to a high level (logic 1) during the test operation, the gate circuit 69 opens the gate, so that the detection signal corresponding to the MOSFETs 63 to 65 becomes valid, and the normal operation is performed as the boost voltage VPP≈VDL + 3Vth. It can be set higher than sometimes. Further, when the control signal DW is set to the high level (logic 1), the gate circuit 71 opens the gate, so that the detection signal corresponding to the MOSFET 68 becomes valid and can be set as low as the boost voltage VPP≈VDL + Vth.
[0020]
In order to reduce useless current in the detection circuit, the control signals UP, NORMAL, and DW are supplied to the gates of the N-channel MOSFETs 60, 61, and 62 that act as the high resistance. By adopting such a configuration, when the control signal is set to the low level, the N-channel MOSFET can be turned off and wasteful current reduction can be performed. In other words, when VPP≈VDL + 3Vth is formed by the high level of the control signal UP, it is possible to prevent a current from constantly flowing in the voltage detection circuit that detects a lower voltage. Further, during the normal operation, when VPP≈VDL + 2Vth is formed by the high level of the control signal NORMAL, it is possible to prevent the current from flowing steadily in the voltage detection circuit that detects a voltage lower than that, and the voltage generator VPP -Gen. Can be lightened even a little.
[0021]
FIG. 2 is a circuit diagram showing one embodiment of a substrate voltage generating circuit provided in a dynamic RAM to which the present invention is applied. The voltage generator VBB-gen. Is not shown in the figure because it is known per se, but includes an oscillation circuit and a charge pump circuit that receives the oscillation pulse and forms a negative voltage VBB lower than the ground potential VSS of the circuit supplied from the external terminal. . The substrate voltage generation circuit is provided with a voltage detection circuit that controls the substrate voltage VBB to be a desired negative voltage.
[0022]
When the substrate voltage VBB reaches a desired set voltage, the voltage detection circuit changes the detection signal VBSTOP to one level in response to the substrate voltage VBB reaching a desired set voltage, so that the voltage generator VBB-gen. Stop the operation. When the substrate voltage VBB is lowered in absolute value (increased in level) from a desired set value due to a current flowing into the substrate voltage due to the operation of the internal circuit, a leakage current, or the like, the voltage detection circuit responds accordingly. The detection signal VBSTOP is changed to the other level and the voltage generator VPP-gen. Restart the operation. In this way, the voltage detection circuit generates the detection signal VBSTOP corresponding to the change in the substrate voltage VBB to generate the voltage generation unit VBB-gen. Is intermittently operated to maintain the substrate voltage VBB at a substantially desired constant voltage.
[0023]
In this embodiment, in order to evaluate the operation margin of the internal circuit, a function for setting two kinds of substrate voltages for an operation test is added in addition to the substrate voltage during normal operation. The substrate voltage in the dynamic RAM is used to supply a negative back bias voltage to the address selection MOSFET of the dynamic memory cell, increase its effective threshold voltage, and reduce the leakage current in the data holding state. belongs to. Three types of substrate voltages including a first substrate voltage corresponding to normal operation, a second substrate voltage set higher than that, and a third substrate voltage set lower than the first substrate voltage. In order to enable switching, three voltage detection circuits corresponding to each are provided. These voltage detection circuits use the threshold voltage between the gate and source of an N-channel MOSFET as voltage detection means.
[0024]
The voltage detection circuit corresponding to the normal operation (NORMAL) includes N-channel MOSFETs 45 and 46 and a P-channel MOSFET 42. In the MOSFET 46, the gate and drain are commonly connected to form a diode, and the substrate voltage VBB is applied to the source. The drain of the MOSFET 46 is connected to the source of the MOSFET 45. The gate of the MOSFET 45 is supplied with the circuit ground potential. Between the drain of the MOSFET 45 and the power supply voltage VDL, there is provided a P-channel type MOSFET 42 that operates as a high resistance element with the circuit ground potential constantly applied to the gate.
[0025]
The MOSFETs 45 and 46 are formed in independent P-type well regions in order to prevent the effective threshold voltage from changing due to the substrate effect due to the potential difference between the source and the substrate. Connected with source. Thus, when the absolute value is VBB <2Vth, the MOSFETs 45 and 46 are turned off, and the drain output of the MOSFET Q42 is set to the high level. On the other hand, when VBB is lowered (deeper) so that VBB> 2Vth in absolute value, the MOSFETs 45 and 46 are turned on, the drain output of the MOSFET Q42 is lowered from high level to low level, and the gate circuit When the voltage falls below the logic threshold voltage of 53, the gate circuit 53 determines that the level is low. By such a detection operation, the voltage generator VBB-gen. Is controlled. As described above, since the signal level in the voltage detection circuit is opposite to that in FIG. 1, the gate circuit 53 is provided with an inverter circuit at the output portion of the NAND gate circuit.
[0026]
A voltage detection circuit for lowering the substrate voltage VBB than that in the normal operation (NORMAL), in other words, deeper (DEEP) is constituted by N-channel MOSFETs 47 to 49 and a P-channel MOSFET 43. The MOSFETs 49 and 48 are connected in series with their gates and drains connected in common to form a diode. The substrate voltage VBB is applied to the source of the one MOSFET 49, and the drain of the other MOSFET 48 is connected to the source of the MOSFET 47. A circuit ground potential VSS is supplied to the gate of the MOSFET 47. A P-channel MOSFET 43 is provided between the drain of the MOSFET 47 and the power supply voltage VDL. The channel type MOSFET 43 is not particularly limited, but operates as a high resistance element with a ground potential constantly applied to the gate.
[0027]
The MOSFETs 47 to 49 are formed in independent N-type well regions in order to prevent the effective threshold voltage from changing due to the substrate effect due to the potential difference between the source and the substrate, as described above. Are connected to their respective sources. As a result, when the absolute value is VBB <3Vth, the MOSFETs 47 to 49 are turned off, and the drain output of the MOSFET Q43 is set to the high level. On the other hand, when VBB decreases (becomes deep) so that VBB> 3Vth in absolute value, MOSFETs 47 to 49 are turned on, the drain output of MOSFET Q43 is raised from low level to high level, and gate circuit 52 When the voltage is lower than the logic threshold voltage, the gate circuit 52 determines the low level. By such detection operation, the voltage generator VPP-gen. Is controlled.
[0028]
A voltage detection circuit for raising the substrate voltage VBB, that is, for making it shallow (SHALLOW) as compared with the normal operation (NORMAL) is constituted by an N-channel MOSFET 44 and a P-channel MOSFET 41. The substrate voltage VBB is applied to the source of the MOSFET 44, and the circuit ground potential VSS is supplied to the gate. The P-channel MOSFET 41 operates as a high resistance element with a ground potential constantly applied to the gate.
[0029]
In the MOSFET 44, the well region in which the MOSFET 44 is formed is connected to the source, and the substrate voltage VBB is applied. Thereby, when VBB <Vth, the MOSFET 44 is turned off, and the drain output of the MOSFET Q41 is set to the high level. On the other hand, when VBB is lowered (deeper) so that VBB> Vth, the MOSFET 44 is turned on, the drain output of the MOSFET Q41 is pulled down from the high level to the low level, and becomes lower than the logic threshold voltage of the gate circuit 50. The gate circuit 50 determines that the level is low. By such detection operation, the voltage generator VBB-gen. Is controlled.
[0030]
In order to select and validate only one detection signal among the three voltage detection circuits as described above, in other words, one of the three substrate voltages -Vth, -2Vth, and -3Vth. Are supplied with control signals SHALLOW, NORMAL, and DEEPW to the gate circuits 50, 51, and 52 corresponding to the three detection circuits, and only one of them is at a high level (logic 1). ).
[0031]
When the control signal NORMAL is set to a high level (logic 1) during normal operation, the gate circuit 51 opens the gate, and the detection signals corresponding to the MOSFETs 45 and 46 become valid, and the substrate voltage VBB is set to −2Vth. . When the control signal DEEP is set to a high level (logic 1) during the test operation, the gate circuit 52 opens the gate, so that the detection signals corresponding to the MOSFETs 47 to 49 become effective, and the normal voltage is set to the substrate voltage VBB≈-3Vth. Can be set deeper than during operation. Further, when the control signal SHALLOW is set to a high level (logic 1), the gate circuit 50 opens the gate, so that the detection signal corresponding to the MOSFET 44 becomes valid and can be set low as the substrate voltage VBB≈−Vth.
[0032]
In order to reduce useless current in the detection circuit, the inverted signals of the control signals DEEP, NORMAL, and SHALLOW are supplied to the gates of the P-channel MOSFETs 60, 61, and 62 that act as the high resistance. With such a configuration, when the control signal is set to the low level, the P-channel MOSFET can be turned off by the high level of the inverted signal, and wasteful current reduction can be performed. That is, when VBB≈−3Vth is formed by the high level of the control signal DEEP, it is possible to prevent a current from constantly flowing in the voltage detection circuit that detects a voltage shallower than that. Further, in the normal operation, when VBB≈−2Vth is formed by the high level of the control signal NORMAL, it is possible to prevent a current from flowing steadily in the voltage detection circuit that detects a voltage shallower than that, and the voltage generator VBB-Gen. The power consumption can be reduced.
[0033]
FIG. 3 is a circuit diagram showing one embodiment of an internal voltage down converter provided in a dynamic RAM to which the present invention is applied. In this embodiment, a constant current is formed and passed through a trimming resistor R connected in series to form a plurality of divided voltages. A reference voltage such as 2.0 V is formed through a MOSFET switch-controlled by trimming signals TRM0 to TRM7 from a plurality of voltages formed by such a voltage dividing circuit.
[0034]
Although not particularly limited, the trimming signals TRM0 to TRM7 are formed by decoding a selection signal composed of 3 bits formed by selectively cutting three fuse means. That is, the three fuse means and the like are cut so that the step-down voltage VDL selects the divided voltage closest to the above 2.0V. The trimming may be set by wire bonding in addition to selective cutting of the fuse means.
[0035]
In this embodiment, in order to evaluate the operation margin of the internal circuit operating at the step-down voltage VDL, a function for setting two kinds of step-down voltages for an operation test is added in addition to the step-down voltage during normal operation. In this case, if the step-down voltage for the operation test is set independently, the difference from the step-down voltage during normal operation differs depending on the individual dynamic RAM due to process variations, etc., and the process variation component is included in the evaluation of the operation margin. It will be.
[0036]
In this embodiment, focusing on the fact that the evaluation of the operation margin of the internal circuit should be set in relation to the test voltage during normal operation, the divided voltage forming the step-down voltage during normal operation Is used to form a test reference voltage. That is, the trimming signals TRM0 to TRM7 are used to simultaneously select the reference voltage corresponding to the normal operation and the upper and lower divided voltages at the same time. For example, in the case of the trimming signal TRM3, the switch MOSFET 32 is turned on, the divided voltage at the voltage dividing point T + 4 is selected, and the first reference voltage for normal operation is selected. At the same time, the switch MOSFETs 31 and 33 are turned on, and the divided voltages at the voltage dividing points T + 3 and T + 5 are selected to select the second and third reference voltages for testing.
[0037]
Also in the other trimming signals TRM0 to TRM7, the first reference voltage for normal operation selected by the same and the upper and lower divided voltages centering on the first reference voltage are selected as described above. However, at the lowest voltage dividing point T + 1, there is no divided voltage lower than that, so only the third reference voltage such as the divided point T + 2 is selected as the test reference voltage. Similarly, since there is no higher voltage at the highest voltage dividing point T + 8, only the second reference voltage such as the voltage dividing point T + 7 is selected as the test reference voltage.
[0038]
The first reference voltage for normal operation is supplied to the input of a voltage follower circuit comprising an operational amplifier circuit 37 and a P-channel output MOSFET 38 through a MOSFET 35 that is switch-controlled by a control signal NOR during normal operation. The second reference voltage for the test operation is supplied to the input of a voltage follower circuit composed of the operational amplifier circuit 37 and the P-channel output MOSFET 38 through the MOSFET 34 that is switch-controlled by the control signal DW during the test operation. Similarly, the third reference voltage for the test operation is supplied to the input of the voltage follower circuit composed of the operational amplifier circuit 37 and the P-channel output MOSFET 38 through the MOSFET 36 that is switch-controlled by the control signal UP during the test operation. Is done. Only one of the control signals NOR, DW, and UP is at a high level, and one of the first to third reference voltages is selected and output through the voltage follower circuit. Thereby, the internal step-down voltage VDL can be switched to the above three voltages.
[0039]
FIG. 4 is a voltage characteristic diagram of the dynamic RAM according to the present invention. In the figure, although not particularly limited, the characteristics VPP-NOR, VDL-NOR, and VBB-NOR indicated by solid lines are voltage characteristics of the internal voltage during normal operation, and the power supply voltage VDD is 2.5 V ± 10%. Sometimes, the voltage is constant such that VPP = 3.6V, VDL = 2.0V, VBB = −1.0V. In order to increase the efficiency of the burn-in test, when the power supply voltage VDD is increased to about 3 V or more, power supply dependency is given so that each VPP and VDL rises corresponding to the rise of the power supply voltage VDD. On the other hand, characteristics VPP-DW, VDL-DW, and VBB-DW indicated by dotted lines are voltage characteristics when the voltage value is reduced in absolute value during the test operation, and characteristics VPP- UP, VDL-UP, and VBB-UP are voltage characteristics when the voltage value is increased in absolute value during the test operation.
[0040]
By adding such a voltage switching function, it is possible to identify those that operate normally under each internal voltage during normal operation but that become defective when the operation test voltage is severe. Can do. For example, a memory cell transfer leak failure or isolation failure, which is a typical failure of a dynamic RAM, is worst when the power supply voltage or the word line potential is high and the substrate potential is shallow. In order to efficiently detect these defects, it is effective to set the voltage conditions to the worst side, and this can be easily implemented by the voltage switching described above.
[0041]
The internal voltage circuit tends to depend on the operating period of the device. For example, when the operation is performed with a relatively long period and when the operation is performed with a short period, the internal step-down voltage VDL and the like are lower than the former because of the power consumption of the device. If the failure that occurs in a short cycle is mainly due to a decrease in the internal step-down voltage VDL, the equivalent failure can be detected without using a high-speed and expensive memory test device by reducing the internal voltage. Quality assurance and cost reduction can be achieved. Conversely, in the case of a failure that occurs in a long cycle and is caused by a high internal step-down voltage VDL, the failure can be detected more effectively by increasing the internal voltage VDL, and at the same time, a long test time is required. It is possible to substitute a test with a long cycle that is required with a short cycle, ensuring quality and reducing costs.
[0042]
FIG. 5 is a schematic layout diagram showing an embodiment of a dynamic RAM to which the present invention is applied. In the figure, the main part of each of the circuit blocks constituting the dynamic RAM to which the present invention is applied is shown so that it can be seen from a single crystal silicon by a known semiconductor integrated circuit manufacturing technique. Are formed on one semiconductor substrate.
[0043]
In this embodiment, although not particularly limited, the memory array is divided into four as a whole. The central portion 14 is provided with an input / output interface circuit including an address input circuit, a data input / output circuit, and a bonding pad row, a power supply circuit including a booster circuit and a step-down circuit, and the like. . A column decoder region 13 is disposed in a portion in contact with the memory array on both sides of the central portion 14.
[0044]
As described above, in each of the four memory arrays divided into two on the left and right with respect to the longitudinal direction of the semiconductor chip and two on the upper and lower sides, the main row decoder area (memory An array control circuit) 11 is provided. A main word driver region 12 is formed above and below the main row decoder, and a drive circuit for driving the main word lines of the memory array divided above and below is provided. And a memory array control circuit for driving the sense amplifier.
[0045]
The memory cell array (hereinafter referred to as a subarray) 15 is formed surrounded by a sense amplifier region 16 and a subword driver region 17 as shown in the enlarged view. An intersection of the sense amplifier region 16 and the sub word driver region 17 is an intersection region (cross area) 18. The sense amplifiers provided in the sense amplifier region 16 are configured by a shared sense system, and except for those corresponding to the subarrays arranged at both ends of the memory array, complementary bit lines are arranged on the left and right with the sense amplifier as the center. Provided, and selectively connected to the complementary bit line of either the left or right sub-array 15.
[0046]
As described above, the memory arrays divided into four pieces on the left and right with respect to the longitudinal direction of the semiconductor chip are arranged in groups of two. In the two memory arrays arranged in groups of two in this way, the main row decoder area 11 and the main word driver 12 are arranged in the central portion. The main word driver 12 generates a selection signal for a main word line that extends so as to penetrate the one memory array. The main word driver region 12 is also provided with a sub word selection line driver (FX driver) for selecting a sub word, and is extended in parallel with the main word line to form a selection signal for the sub word selection line as will be described later. A switch MOSFET (described later) for driving the sense amplifier is also provided.
[0047]
Although one memory cell array (subarray) 15 shown as an enlarged view is not particularly limited, there are 256 subword lines and 256 pairs of complementary bit lines (or data lines) orthogonal thereto. In the one memory array, since 16 subarrays 15 are provided in the bit line direction, approximately 4K sub word lines are provided, and since 16 sub arrays 15 are provided in the word line direction, complementary bit lines are provided for approximately 4K. Since four memory arrays are provided as a whole, the memory capacity of the entire memory chip 10 is set to 4 × 4K × 4K = 64 Mbits.
[0048]
The one memory array is divided into 16 in the main word line direction. A sub word driver (sub word line drive circuit) 17 is provided for each of the divided sub arrays 15. The sub word driver 17 is divided into a length of 1/16 with respect to the main word line and forms a selection signal for the sub word line extending in parallel therewith. In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. 8 sub word lines are arranged. In order to select one sub word line from among the sub word lines that are divided into 8 in the main word line direction and 8 are assigned in the complementary bit line direction, the sub word selection driver Be placed. This subword selection driver forms a selection signal for selecting one of eight subword selection lines extended in the arrangement direction of the subword drivers.
[0049]
FIG. 6 is a schematic layout diagram showing one embodiment of a sub-array and its peripheral circuit in the dynamic RAM according to the present invention. In the figure, four subarrays SBARY in the memory array shown in FIG. 5 are shown as representatives. In FIG. 6, a region where the subarray SBARY is formed is hatched to distinguish a subword driver region, a sense amplifier region, and a cross area provided around the region.
[0050]
The subarray SBARY is divided into the following four types. That is, assuming that the extending direction of the word lines is the horizontal direction, the first sub-array SBARY arranged at the lower right in the figure has 256 sub-word lines SWL and 256 complementary bit line pairs. Therefore, the 256 sub word drivers SWD corresponding to the 256 sub word lines SWL are divided into 128 pieces on the left and right sides of the sub array. In addition to the shared sense amplifier system as described above, the 256 sense amplifiers SA provided corresponding to the 256 pairs of complementary bit lines BL are further arranged alternately and divided into 128 pieces above and below the subarray. Arranged.
[0051]
The second sub-array SBARY arranged in the upper right of the figure is not particularly limited, but in addition to 256 regular sub-word lines SWL, eight spare (redundant) word lines are provided, and complementary bit line pairs are 256 pairs. Consists of Therefore, 264 sub word drivers SWD corresponding to the 256 + 8 sub word lines SWL are divided into 132 on the left and right sides of the sub array. As above, 128 sense amplifiers are arranged one above the other. In other words, 128 complementary bit lines out of 256 pairs formed in the subarray SBARY arranged on the upper and lower sides of the right side are commonly connected to the sense amplifier SA sandwiched therebetween via the shared switch MOSFET. .
[0052]
The third sub-array SBARY arranged at the lower left in the figure includes 256 sub-word lines SWL as in the right adjacent sub-array SBARY. Similarly to the above, 128 subword drivers are divided and arranged. Of the 256 subarrays SBARY arranged on the left and right sides of the lower side, 128 subword lines SWL are commonly connected to 128 subword drivers SWD formed in a region sandwiched therebetween. As described above, the sub-array SBARY arranged at the lower left is provided with four pairs of spare (redundant) bit lines 4RED in addition to 256 pairs of normal complementary bit lines BL. Therefore, the 260 sense amplifiers SA corresponding to the 260 pairs of complementary bit lines BL are divided into 130 pieces above and below the subarray.
[0053]
The fourth sub-array SBARY arranged in the upper left of the figure is provided with 256 normal sub-word lines SWL and 8 spare sub-word lines similarly to the right adjacent sub-array SBARY, and normal complementary similar to the lower adjacent sub-array. Since four spare bit lines are provided in addition to 256 bit line pairs, subword drivers are divided into 132 pieces on the left and right sides, and sense amplifiers SA are arranged divided into 130 pieces on the top and bottom. Is done.
[0054]
The main word line MWL is extended in the horizontal direction as described above, one of which is exemplarily shown as a representative. Further, the column selection line YS is extended in the vertical direction so that one of them is exemplified as a representative. A sub word line SWL is arranged in parallel with the main word line MWL, and a complementary bit line BL (not shown) is arranged in parallel with the column selection line YS. In this embodiment, although there is no particular limitation, in the 16 Mbit DRAM as shown in FIG. 5 with the four subarrays as one set of basic units, eight sets of subarrays are formed in the bitline direction, and in the wordline direction. Consists of 8 subarrays. Since one set is composed of four subarrays, 8 × 8 × 4 = 256 subarrays are provided in the 16 Mbit memory array. Since four memory arrays having the 256 sub-arrays are provided in the entire chip, 256 × 4 = 1024 sub-arrays are formed in the entire memory chip.
[0055]
With respect to the four subarrays, eight subword selection lines FX0B to FX7B are extended so as to penetrate eight sets (16 pieces) of subarrays similarly to the main word line MWL. Then, the four sub word select lines FX0B to FX3B and the four sub word select lines FX4B to FX7B are divided and extended on the upper and lower subarrays. The reason for assigning a set of subword selection lines FX0B to FX7B to the two subarrays and extending them on the subarrays is to reduce the memory chip size.
[0056]
In other words, when the eight sub word selection lines FX0B to FX7B are assigned to each subarray and are formed in the wiring channel on the sense amplifier area, as many as 32 in the short side direction as in the memory array of FIG. The sense amplifier requires 8 × 32 = 256 wiring channels. On the other hand, in the above embodiment, the eight sub word selection lines FX0B to FX7B are commonly assigned to the upper and lower two subarrays in the above-described wiring, and they are arranged on the subarray in parallel with the main word line. By arranging so as to be mixed, it can be formed without providing a special wiring dedicated region.
[0057]
On the subarray, one main word line is provided for eight subword lines, and subword selection lines FX0B to FX7B are provided to select one of the eight subword lines. It is necessary. Since the main word lines MWL are formed at a ratio of one to eight sub word lines SWL formed in accordance with the pitch of the memory cells, the wiring pitch of the main word lines MWL becomes gentle. Yes. Therefore, using the same wiring layer as the main word line MWL, the sub-word selection line can be formed between the main word lines relatively easily with a slight sacrifice of the wiring pitch. .
[0058]
The sub word driver SWD of this embodiment adopts a configuration in which one sub word line SWL is selected using a selection signal supplied through the sub word selection line FX0B and the like and a selection signal obtained by inverting the selection signal. The sub word driver SWD is configured to simultaneously select the sub word lines SWL of the sub arrays arranged on the left and right with the sub word driver SWD as the center. Therefore, for the two subarrays sharing FX0B and the like as described above, the four subword selection lines are allocated and supplied to as many as 128 × 2 = 256 subword drivers. That is, paying attention to the sub word selection line FX0B, it is necessary to supply selection signals to 256 ÷ 4 = 64 sub word drivers SWD for two sub arrays.
[0059]
If the first sub-word selection line FX0B is extended in parallel with the main word line MWL, the sub-word selection line drive is provided in the upper left cross area and receives a selection signal from the first sub-word selection line FX0B. A second subword selection line FX0 is provided through the circuit FXD to supply a selection signal to the 64 subword drivers arranged above and below. The first sub-word selection line FX0B extends in parallel with the main word line MWL and the sub-word line SWL, whereas the second sub-word selection line includes a column selection line YS and a complementary bit line BL orthogonal to the first sub-word selection line FX0B. The sub word driver area is extended in parallel. Similar to the eight first subword selection lines FX0B to FX7B, the second subword selection lines FX0 to FX7 are also divided into even number FX0, 2, 4, 6 and odd number FX1, 3, 5, 7. The sub-word drivers SWD provided on the left and right of the sub-array SBARY are distributed and arranged.
[0060]
The sub-word selection line driving circuits FXD are distributed and arranged two by two above and below one cross area, as indicated by (2) in FIG. That is, as described above, in the upper left cross area, the sub word selection line driving circuit arranged on the lower side corresponds to the first sub word selection line FX0B, and two sub words provided in the left middle cross area. The selection line driving circuit FXD corresponds to the first sub-word selection lines FX2B and FX4B, and the sub-word selection line driving circuit arranged above the lower left cross area corresponds to the first sub-word selection line FX6B. .
[0061]
In the cross area in the upper center, the sub word selection line drive circuit arranged on the lower side corresponds to the first sub word selection line FX1B, and the two sub word selection line drive circuits FXD provided in the cross area in the middle middle part The sub-word selection line driving circuit corresponding to the first sub-word selection lines FX3B and FX5B and disposed above the cross area at the lower center corresponds to the first sub-word selection line FX7B. In the upper right cross area, the sub word selection line driving circuits arranged on the lower side correspond to the first sub word selection line FX0B, and two sub word selection line driving circuits provided in the right middle cross area. FXD corresponds to the first sub-word selection lines FX2B and FX4B, and the sub-word selection line driving circuit arranged above the lower right cross area corresponds to the first sub-word selection line FX6B. In this way, the sub word driver SWD provided at the end of the memory array drives only the sub word line SWL of the left sub array because there is no sub array on the right side.
[0062]
In the configuration in which the sub word selection line FXB is arranged in the gap between the main word lines MWL on the sub array as in this embodiment, a special wiring channel can be dispensed with, so that eight sub word selection lines are arranged in one sub array. This does not increase the size of the memory chip. However, since the sub-word selection line driving circuit FXD as described above is formed, the area of the cross region increases, which hinders high integration. That is, in the cross area, an IO switch provided corresponding to a main input / output line (also referred to as a main IO line) MIO or a local input / output line (also referred to as a local IO line) LIO as indicated by a dotted line in FIG. Since it is necessary to form peripheral circuits such as a circuit IOSW, a power MOSFET for driving a sense amplifier, a drive circuit for driving a shared switch MOSFET, and a drive circuit for driving a precharge MOSFET, the number of elements is reduced. There is a need. In the embodiment of FIG. 6, the upper / lower two subarrays share the subword selection line driving circuit FXD to suppress the area increase.
[0063]
Of the cross areas, the second sub-word selection lines arranged in the extension direction A of FX0 to FX6 corresponding to even numbers are supplied with overdrive power supply voltage VDD for the sense amplifier as will be described later. An N-channel power MOSFET Q16 for supplying, an N-channel power switch MOSFET Q15 for supplying the internal step-down voltage VDL, and an N-channel power MOSFET Q14 for supplying the circuit ground potential VSS to the sense amplifier are provided.
[0064]
Among the cross areas, the second sub-word selection lines arranged in the extension direction B of FX1 to FX7 corresponding to the odd numbers are connected to the IO switch circuit (between the local IO (LIO) and the main IO (MIO)). Switch), an inverter circuit for turning off the precharge and equalize MOSFETs of the bit line, and an N-channel power MOSFET for supplying the circuit ground potential VSS to the sense amplifier, although not particularly limited. Provided. The N-channel power MOSFET supplies a ground potential to the common source line (CSN) of the amplification MOSFET of the N-channel MOSFET constituting the sense amplifier from both sides of the sense amplifier row. That is, for 128 or 130 sense amplifiers provided in the sense amplifier area, an N-channel power MOSFET provided in the A-side cross area and an N-channel power MOSFET provided in the B-side cross area. The ground potential is supplied by both channel type power MOSFETs.
[0065]
As described above, the sub-word line drive circuit SWD selects the sub-word lines of the sub-arrays on the left and right sides with the center thereof. On the other hand, the left and right two sense amplifiers are activated corresponding to the sub word lines of the two selected sub arrays. That is, when the sub word line is set to the selected state, the address selection MOSFET is turned on, and the charge of the storage capacitor is combined with the bit line charge, so that it is possible to restore the original charge state even when the sense amplifier is activated. This is because it is necessary to perform a write operation. For this reason, except for the one corresponding to the subarray at the end, the power MOSFET is used to activate the sense amplifiers on both sides of the power MOSFET. On the other hand, in the sub word line drive circuit SWD provided on the right or left side of the sub array provided at the end of the sub array group, only the sub word line of the sub array is selected. Only the sense amplifier group is activated.
[0066]
The sense amplifier is a shared sense system, and among the subarrays arranged on both sides of the sense amplifier, the shared switch MOSFET corresponding to the complementary bit line on the side where the subword line is not selected is turned off and disconnected. As a result, the rewrite operation of amplifying the read signal of the complementary bit line corresponding to the selected sub word line and returning the storage capacitor of the memory cell to the original charge state is performed. In this case, when the amplification is started by the overdrive MOSFET, a high voltage such as the power supply voltage VDD is supplied, so that the change of the bit line to be set to the high level can be accelerated, and the potential of the bit line becomes VDL. When it reaches, VDL is given by the common power switch MOSFET.
[0067]
FIG. 7 shows a simplified circuit diagram of an embodiment from address input to data output centering on the sense amplifier portion of the dynamic RAM according to the present invention. In the figure, a sense amplifier 16 sandwiched between two subarrays 15 from above and below and a circuit provided in the intersection area 18 are shown as an example, and others are shown as block diagrams. The circuit blocks indicated by dotted lines are indicated by the reference numerals.
[0068]
As the dynamic memory cell, one of the dynamic memory cells provided between the sub word line SWL provided in the one subarray 15 and one of the complementary bit lines BL and BLB is exemplarily shown as a representative. ing. The dynamic memory cell includes an address selection MOSFET Qm and a storage capacitor Cs. The gate of the address selection MOSFET Qm is connected to the sub word line SWL, the drain of the MOSFET Qm is connected to the bit line BL, and the storage capacitor Cs is connected to the source. The other electrode of the storage capacitor Cs is made common to receive the plate voltage VPLT. A negative back bias voltage VBB is applied to the substrate (channel) of the MOSFET Qm. Although not particularly limited, the back bias voltage VBB is set to a voltage such as -1.0V. The selection level of the sub word line SWL is set to a high voltage VPP that is higher than the high level of the bit line by the threshold voltage of the address selection MOSFET Qm.
[0069]
When the sense amplifier is operated at the internal step-down voltage VDL, the high level amplified by the sense amplifier and applied to the bit line is set to the internal voltage VDL level. Therefore, the high voltage VPP corresponding to the selection level of the word line is set to VDL + Vth + α. A pair of complementary bit lines BL and BLB in the sub-array provided on the left side of the sense amplifier are arranged in parallel as shown in FIG. The complementary bit lines BL and BLB are connected to input / output nodes of the unit circuit of the sense amplifier by shared switch MOSFETs Q1 and Q2.
[0070]
The unit circuit of the sense amplifier is composed of a CMOS latch circuit composed of N-channel type amplification MOSFETs Q5 and Q6 and P-channel type amplification MOSFETs Q7 and Q8 whose gates and drains are cross-connected to form a latch. The sources of N-channel MOSFETs Q5 and Q6 are connected to a common source line CSN. The sources of P-channel MOSFETs Q7 and Q8 are connected to a common source line CSP. A power switch MOSFET is connected to each of the common source lines CSN and CSP. Although not particularly limited, an operating voltage corresponding to the ground potential is applied to the common source line CSN connected to the sources of the N-channel amplification MOSFETs Q5 and Q6 by the N-channel power switch MOSFET Q14 provided in the cross area 18. Given.
[0071]
Although not particularly limited, an N channel power MOSFET Q16 for overdrive provided in the cross area 18 and the internal voltage are connected to the common source line CSP to which the sources of the P channel amplification MOSFETs Q7 and Q8 are connected. An N channel type power MOSFET Q15 for supplying VDL is provided. The overdrive voltage is not particularly limited, but a power supply voltage VDD supplied from an external terminal is used. Alternatively, in order to reduce the dependency of the sense amplifier operating speed on the power supply voltage VDD, the voltage is slightly lowered as the voltage is obtained from the source of the N-channel MOSFET in which VPP is applied to the gate and the power supply voltage VDD is supplied to the drain. May be.
[0072]
The sense amplifier overdrive activation signal SAP1 supplied to the gate of the N-channel type power MOSFET Q16 is a signal in phase with the activation signal SAP2 supplied to the gate of the N-channel type MOSFET Q15, and SAP1 and SAP2 are It is made high level in time series. Although not particularly limited, the high levels of SAP1 and SAP2 are signals of the boosted voltage VPP level. That is, since the boosted voltage VPP is about 3.6 V, the N-channel MOSFETs Q15 and Q16 can be sufficiently turned on. After the MOSFET Q16 is turned off (the signal SAP1 is at a low level), a voltage corresponding to the internal voltage VDL can be output from the source side by turning on the MOSFET Q15 (the signal SAP2 is at a high level).
[0073]
At the input / output node of the unit circuit of the sense amplifier, there are provided an equalize MOSFET Q11 for short-circuiting the complementary bit line and a precharge (equalize) circuit comprising switch MOSFETs Q9 and Q10 for supplying a half precharge voltage VBLR to the complementary bit line. . The gates of these MOSFETs Q9 to Q11 are commonly supplied with a precharge signal PCB. Although not shown, the driver circuit for forming the precharge signal PCB is provided with an inverter circuit in the cross area so as to make the rise and rise fast. That is, at the start of memory access, the MOSFETs Q9 to Q11 constituting the precharge circuit are switched at high speed through the inverter circuits distributed in the respective cross areas prior to the word line selection timing.
[0074]
In the cross area 18, an IO switch circuit IOSW (switch MOSFETs Q19 and Q20 connecting the local IO and the main IO) is placed. In addition to the circuit shown in FIG. 3, if necessary, the common source lines CSP and CSN of the sense amplifier are half precharged, the local input / output line LIO is half precharged, and the main input / output line is VDL precharged. A charge circuit, a distributed driver circuit for shared selection signal lines SHR and SHL, and the like are also provided.
[0075]
The unit circuit of the sense amplifier is connected to similar complementary bit lines BL and BLB of the subarray 15 on the lower side of the figure via shared switch MOSFETs Q3 and Q4. For example, when the sub word line SWL of the upper sub array is selected, the upper shared switch MOSFETs Q1 and Q2 of the sense amplifier are turned on, and the lower shared switch MOSFETs Q3 and Q4 are turned off. The switch MOSFETs Q12 and Q13 constitute a column (Y) switch circuit. The switch MOSFETs Q12 and Q13 are turned on when the selection signal YS is set to a selection level (high level). The input / output lines LIO1 and LIO1B, LIO2, LIO2B, etc. are connected.
[0076]
As a result, the input / output node of the sense amplifier is connected to the upper complementary bit lines BL and BLB, amplifies a minute signal of the memory cell connected to the selected sub word line SWL, and the column switch circuit (Q12 And Q13) to the local input / output lines LIO1 and LIO1B. The local input / output lines LIO1 and LIO1B extend along the sense amplifier row, that is, in the horizontal direction in FIG. The local input / output lines LIO1 and LIO1B are connected to main input / output lines MIO and MIOB to which the input terminals of the main amplifier 61 are connected via an IO switch circuit composed of N-channel MOSFETs Q19 and Q20 provided in the cross area 18. Is done. The IO switch circuit is switch-controlled by a selection signal formed by decoding an X-system address signal. The IO switch circuit may have a CMOS switch configuration in which a P-channel MOSFET is connected in parallel to each of the N-channel MOSFETs Q19 and Q20.
[0077]
In the configuration in which two pairs of complementary bit lines are selected by the column selection signal YS as described above, the local input / output line LIO and the main input / output line MIO indicated by two dotted lines in the embodiment of FIG. It corresponds to two pairs of input / output lines. In the burst mode of the synchronous DRAM, the column selection signal YS is switched by a counter operation, and the connection between the local input / output lines LIO1, LIO1B and LIO2, LIO2B and two pairs of complementary bit lines BL and BLB in sequence is sequentially performed. Can be switched to.
[0078]
The address signal Ai is supplied to the address buffer 51. This address buffer operates in a time-sharing manner and takes in the X address signal and the Y address signal. The X address signal is supplied to the predecoder 52, and a selection signal for the main word line MWL is formed via the main row decoder 11 and the main word driver 12. Since the address buffer 51 receives the address signal Ai supplied from the external terminal, the address buffer 51 is operated by the power supply voltage VDD supplied from the external terminal, the predecoder is operated by the step-down voltage VPERI, The main word driver 12 is operated by the boosted voltage VPP. As the main word driver 12, a logic circuit with a level conversion function for receiving the predecode signal as described below is used. The column decoder (driver) 53 receives the Y address signal supplied by the time-division operation of the address buffer 51, and forms the selection signal YS.
[0079]
The main amplifier 61 is operated by the step-down voltage VPERI and is output from the external terminal Dout through the output buffer 62 operated by the power supply voltage VDD supplied from the external terminal. A write signal input from the external terminal Din is taken in through the input buffer 63 and supplied to the main input / output lines MIO and MIOB through a write amplifier (write driver) included in the main amplifier 61 in FIG. The input section of the output buffer 62 is provided with a level conversion circuit and a logic section for outputting the output signal in synchronization with the timing signal corresponding to the clock signal.
[0080]
Although not particularly limited, the power supply voltage VDD supplied from the external terminal is set to 3.3 V in the first embodiment, the step-down voltage VPERI supplied to the internal circuit is set to 2.5 V, and the operation of the sense amplifier is performed. The voltage VDL is 2.0V. The word line selection signal (boosted voltage) is set to 3.6V. The bit line precharge voltage VBLR is set to 1.0 V corresponding to VDL / 2, and the plate voltage VPLT is also set to 1.0 V. The substrate voltage VBB is set to -1.0V. The power supply voltage VDD supplied from the external terminal is set to a low voltage such as 2.5V in the second embodiment. At such a low power supply voltage VDD, the step-down voltage VPERI is omitted, the peripheral circuit such as the decoder circuit is operated by the power supply voltage VDD of 2.5 V, and other voltages are the same as described above.
[0081]
In the dynamic RAM of this embodiment, the power supply voltage VDD is 3.3 V and the internal step-down voltage is formed in two ways, VPERI and VDL. Is added. Also, the voltage characteristics are such that each voltage becomes flat when the power supply voltage VDD is in the range of 3.3V ± 10%, as compared with FIG. The control signals UP, DW and the like for switching to the test voltage are formed in the test mode. Alternatively, if there is a margin in the external terminal, it may be input directly.
[0082]
The effects obtained from the above embodiment are as follows.
(1) An internal power supply circuit that receives the first voltage and the second voltage supplied from the first and second external terminals and forms an internal voltage different from the first voltage, and an internal that operates at the internal voltage In a semiconductor integrated circuit device having a circuit, since the internal power supply circuit is provided with a function that can be changed to a voltage different from the normal operation, an operation test under more severe conditions becomes possible. And high reliability can be obtained.
[0083]
(2) As the internal power supply circuit, a charge pump circuit which receives a pulse signal corresponding to the first voltage and the second voltage and forms an internal voltage different from the first voltage or the second voltage, and the charge pump circuit By providing a plurality of level detection circuits for detecting the internal voltage formed by the above, and controlling the operation of the charge pump circuit by switching to obtain a desired internal voltage, the voltage can be obtained by adding a simple circuit. The effect of realizing the switching function is obtained.
[0084]
(3) The internal power supply circuit is constituted by a voltage follower circuit that operates at the first voltage and the second voltage and forms a step-down voltage corresponding to a reference voltage formed by dividing the first voltage. A first reference voltage corresponding to normal operation, a second reference voltage higher than the first reference voltage, and the first reference voltage among a plurality of reference voltages formed to correct variations. A lower third reference voltage is selected by the trimming signal, and the first, second and third reference voltages selected by the trimming signal are switched, so that the accuracy linked with the normal operation can be obtained. The effect that a high margin evaluation can be performed is obtained.
[0085]
(4) A plurality of word lines, a plurality of complementary bit line pairs, and a plurality of dynamic memory cells provided at intersections thereof, provided with a memory array and an internal circuit for forming an address selection signal, A step-up voltage circuit for setting a selection level, a negative voltage generation circuit for setting a substrate back bias voltage to be applied to a semiconductor region in which the memory cell is formed, and a step-down voltage circuit for an internal circuit for forming an address selection signal. By adding the voltage switching function, it is possible to achieve the effect of ensuring the quality of the dynamic RAM and improving the efficiency of the test.
[0086]
The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the dynamic RAM shown in FIGS. 5 to 7, the configuration of the memory mat and sense amplifier can take various embodiments, and the input / output interface of the dynamic RAM has a synchronous specification or a Rambus specification. It is possible to adopt various embodiments such as those adapted to the above. The word line may adopt a word shunt method in addition to the hierarchical word line method as described above.
[0087]
The voltage switching function according to the present invention includes an internal voltage generating circuit that uses a power supply voltage supplied from an external terminal in addition to the dynamic RAM as described above, and forms a boosted voltage, a stepped-down voltage, or an internal voltage of reverse polarity. The present invention can be applied to various semiconductor integrated circuit devices provided. The present invention can be widely used for a semiconductor integrated circuit device provided with the internal voltage generating circuit as described above.
[0088]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, an internal power supply circuit that receives the first voltage and the second voltage supplied from the first and second external terminals and forms an internal voltage different from the first voltage, and an internal circuit that operates at the internal voltage In the semiconductor integrated circuit device equipped with the above, the internal power supply circuit is provided with a function that can be changed to a voltage different from the normal operation, thereby enabling an operation test under more severe conditions. And high reliability can be ensured.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of a booster circuit provided in a dynamic RAM to which the present invention is applied.
FIG. 2 is a circuit diagram showing one embodiment of a substrate voltage generating circuit provided in a dynamic RAM to which the present invention is applied.
FIG. 3 is a circuit diagram showing one embodiment of an internal step-down circuit provided in a dynamic RAM to which the present invention is applied.
FIG. 4 is a voltage characteristic diagram of a dynamic RAM to which the present invention is applied.
FIG. 5 is a schematic layout diagram showing one embodiment of a dynamic RAM to which the present invention is applied.
FIG. 6 is a schematic layout diagram showing one embodiment of a subarray and its peripheral circuits in the dynamic RAM according to the present invention.
FIG. 7 is a circuit diagram showing a simplified embodiment from address input to data output centering on the sense amplifier section of the dynamic RAM according to the present invention;
[Explanation of symbols]
31-34 ... MOSFET, 37 ... operational amplifier circuit, 38 ... MOSFET, 41-49 ... MOSFET, 50-53 ... gate circuit, 60-69 ... MOSFET, 60-72 ... gate circuit, VPP-Gen. , VBB-Gen. DESCRIPTION OF SYMBOLS Voltage generator, 10 Memory chip, 11 Main row decoder area, 12 Main word driver area, 13 Column decoder area, 14 Peripheral circuit, Bonding pad area, 15 Memory cell array (subarray), 16 ... sense amplifier area, 17 ... subword driver area, 18 ... intersection area (cross area),
DESCRIPTION OF SYMBOLS 51 ... Address buffer, 52 ... Predecoder, 53 ... Decoder, 61 ... Main amplifier, 62 ... Output buffer, 63 ... Input buffer, SBARY ... Subarray, SWD ... Subword driver, SA ... Sense amplifier, IOSW ... IO switch circuit, Q1 ~ Q38 MOSFET.

Claims (5)

A first voltage supplied from the first external terminal, an internal power supply circuit receives the ground potential of the circuit which is supplied from the second external terminal, forming different internal voltages from the first voltage,
And an internal circuit which operates with the internal voltage,
The internal power circuit is
A charge pump circuit that forms an internal voltage different from a first voltage or a ground potential, stops its operation upon receiving a detection signal at one level, and restarts operation upon receiving the detection signal at the other level A charge pump circuit;
A first level detection circuit that receives the internal voltage, detects that the internal voltage has reached a first internal voltage corresponding to a normal operation of the internal circuit, and outputs a detection signal of the one level;
In response to the internal voltage, the one level is detected by detecting that the internal voltage has reached a second internal voltage higher than the first internal voltage in consideration of an operation margin corresponding to a test operation of the internal circuit. A second level detection circuit for outputting a detection signal of
Receiving the internal voltage, detecting that the internal voltage has reached a third internal voltage lower than the first internal voltage in consideration of an operation margin corresponding to a test operation of the internal circuit; A third level detection circuit for outputting a detection signal of
The detection signal from the first level detection circuit Te odor during normal operation is applied to the charge pump circuit, the detection signal is the charge pump from the first level detection circuit in the first test operation of the test operation A semiconductor integrated circuit device, wherein a detection signal from the third level detection circuit is supplied to the charge pump circuit in a second test operation among the test operations. Each of the level detection circuits corresponds to an N-channel MOSFET that functions as a high-resistance element with one end grounded, and the first to third internal voltages connected in series to the other end of the N-channel MOSFET. 1 to 3 P-channel MOSFETs,
The N-channel MOSFET of the third level detection circuit is cut off during normal operation, and the N-channel MOSFET of the first and third level detection circuits is cut off during the first test operation. The semiconductor integrated circuit device according to claim 1, wherein: The internal circuit includes a memory array provided with a plurality of word lines, a plurality of complementary bit line pairs, and a plurality of dynamic memory cells provided at intersections thereof, and an address selection circuit for forming an address selection signal. Including
3. The semiconductor integrated circuit device according to claim 1, wherein the internal power supply circuit is used to form a boosted voltage that sets a selection level of the word line . Each of the level detection circuits corresponds to a P-channel MOSFET that functions as a high-resistance element with one end grounded, and the first to third internal voltages connected in series to the other end of the P-channel MOSFET. 1 to 3 N-channel MOSFETs,
The P-channel MOSFET of the first level detection circuit is cut off during the normal operation, and the P-channel MOSFETs of the first and second level detection circuits are cut off during the second test operation. The semiconductor integrated circuit device according to claim 1, wherein: The internal circuit includes a memory array provided with a plurality of word lines, a plurality of complementary bit line pairs, and a plurality of dynamic memory cells provided at intersections thereof, and an address selection circuit for forming an address selection signal. Including
5. The semiconductor integrated circuit device according to claim 1, wherein the internal power supply circuit is used for setting a negative substrate back bias voltage applied to a semiconductor region in which the memory cell is formed .

Images