WO2011155333A1 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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Publication number
WO2011155333A1
WO2011155333A1 PCT/JP2011/061975 JP2011061975W WO2011155333A1 WO 2011155333 A1 WO2011155333 A1 WO 2011155333A1 JP 2011061975 W JP2011061975 W JP 2011061975W WO 2011155333 A1 WO2011155333 A1 WO 2011155333A1
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WO
WIPO (PCT)
Prior art keywords
clock signal
circuit
clock
signal selection
semiconductor integrated
Prior art date
Application number
PCT/JP2011/061975
Other languages
French (fr)
Japanese (ja)
Inventor
忠幸 松村
古田　太
長田　健一
Original Assignee
株式会社日立製作所
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Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Publication of WO2011155333A1 publication Critical patent/WO2011155333A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the present invention relates to a clock signal supply technique in a semiconductor integrated circuit device, and more particularly to a technique effective for distributing a clock signal in a configuration in which a plurality of semiconductor chips are stacked.
  • This type of stacking technique includes a homochip stacking technique in which a plurality of semiconductor chips manufactured from the same mask are stacked, and a hetero chip stacking technique in which a plurality of semiconductor chips manufactured from a plurality of different masks are stacked.
  • a technique for electrically connecting the laminated semiconductor chips is required.
  • a connection technology between the stacked semiconductor chips for example, a through-silicon via (TSV: Through Silicon Via) that electrically connects the front surface and the back surface of the chip by opening a hole in the silicon of the semiconductor chip and filling the hole with a conductor.
  • TSV Through Silicon Via
  • This TSV method is expected to be capable of miniaturizing electrodes in the stacking direction (three-dimensional electrodes) as it approaches metal wiring on a semiconductor chip, and is promising as a next-generation connection technology.
  • reconfigurable circuits such as FPGA (Field Programmable Gate Gate Array) that can correct circuit configuration information in a timely manner after the manufacture of a semiconductor integrated circuit device are attracting attention for the reason of increasing the use cost of the most advanced processes. .
  • FPGA Field Programmable Gate Gate Array
  • logic circuits connected to each other by three-dimensional wiring are formed across a plurality of semiconductor integrated circuit devices, and reconfigurable circuits such as FPGAs are also connected to each other by three-dimensional wiring. It is thought that it becomes.
  • the logic circuit has two mounting systems: a synchronous circuit system in which the entire circuit performs operations and data transmission / reception in synchronization with a clock signal, and an asynchronous circuit system in which the circuits constituting the logic circuit independently perform operations and data transmission / reception There is.
  • the clock skew occurs due to variations in various conditions such as variations in transistor performance due to manufacturing variations and variations in transistor performance due to temperature variations in the semiconductor integrated circuit device during circuit operation.
  • Non-Patent Document 1 As a technique for suppressing clock skew due to temperature variations between semiconductor chips in this type of semiconductor integrated circuit device, for example, the clock signal distribution in the horizontal direction of the semiconductor chip is concentrated on the semiconductor chip of a specific layer, and at the end of the clock signal distribution circuit. There has been proposed one that supplies a clock signal to upper and lower separate semiconductor chips via through silicon vias (see Non-Patent Document 1).
  • the clock signal distribution circuit in the horizontal direction is concentrated on a specific semiconductor chip, so that it is possible to solve the problem of clock skew due to variations between semiconductor chips.
  • each memory element on the circuit is uncertain when designing a semiconductor integrated circuit device, and therefore a clock signal to be input to each memory element cannot be determined. .
  • each storage element receives an appropriate clock signal from among the plurality of types of distributed clock signals.
  • a structure that can be selected is required.
  • FIG. 9 is a diagram illustrating a configuration of a clock supply circuit in a reconfigurable circuit exemplified by an FPGA or the like.
  • the clock signal is selected multiple times in a hierarchical manner.
  • the clock signal generation circuit 101 Based on the reference oscillation signal CRY input from the outside of the semiconductor integrated circuit device 100, the clock signal generation circuit 101 performs frequency division, phase adjustment, and the like to generate a plurality of types of clock signals.
  • the generated clock signal is supplied to a storage element 104 such as a flip-flop, which finally operates in synchronization with a terminal clock signal, via clock signal selection circuits 102 and 103 that can be composed of a plurality of stages.
  • the clock signal selection circuits 102 and 103 are composed of programmable switches capable of reconfiguring the connection relationship between the input / output wirings after manufacturing the semiconductor integrated circuit device. Based on the control signal output from the control circuit 105, the connection relation information is appropriately set to the clock signal selection circuits 102 and 103, thereby supplying an appropriate clock signal to each storage element.
  • connection relationship between the input and output wirings in the clock signal selection circuit is when the connection path from the input wiring to all the output wirings is prepared or when only the connection path from the input wiring to some output wirings is prepared There are two possible cases.
  • FIG. 10 is an explanatory diagram showing the connection configuration of the programmable switches in the clock signal selection circuits 102 and 103.
  • Each dotted line in the clock signal selection circuits 102 and 103 indicates that there is a programmable switch between the respective terminals.
  • the clock signal selection circuit 102 shows an example in which only a connection path from the input wiring to a part of the output wiring is prepared.
  • the clock signal generation circuit 101 and the clock signal selection circuit 102 are connected via wirings H100 to H103, and the clock signal selection circuit 102 and the clock signal selection circuit 103 are connected via wirings H104 to H106. Yes.
  • the clock signal selection circuit 103 and the memory element 104 are connected via a wiring H107.
  • a connection path via a programmable switch is prepared between two wirings H104 and H105 among the wirings H104 to H106.
  • the clock signal selection circuit 103 is a case where a connection path from the wirings H104 to H106 to the wiring H107 is prepared.
  • the on / off information of the programmable switch is held in a storage element that holds the on / off information when setting the configuration of the reconfigurable circuit, and the control circuit 105 determines the on / off of each programmable switch based on the on / off information. Control off.
  • the clock signal distribution circuit of the reconfigurable circuit not only suppresses clock skew but also can select an appropriate clock signal from a plurality of clock signals.
  • Non-Patent Document 1 When the technology of supplying a clock signal to a semiconductor chip of another layer via a TSV at the end of the clock signal distribution circuit is applied to a reconfigurable circuit such as an FPGA by the configuration of Non-Patent Document 1, there are a plurality of problems. appear.
  • the TSV 113 is not formed normally. For example, when the TSV 113 is opened or short-circuited with another signal line, all the TSVs connected to the TSV 113 are connected. There is a problem that the clock signal cannot be normally distributed to the storage element.
  • the clock signal cannot be normally supplied to all the memory elements 114 to 116 connected to the TSV 113.
  • the clock signal distribution circuit when the clock signal distribution circuit is concentrated on a single semiconductor chip, the power is generated due to the clock signal distribution, and the power consumption varies among the semiconductor chips.
  • An object of the present invention is to provide a technique capable of supplying a clock signal efficiently without degrading the selectivity of the clock signal when distributing a plurality of types of clock signals to a plurality of stacked semiconductor chips. There is.
  • the present invention is a semiconductor integrated circuit device having a plurality of stacked semiconductor chips and through-wirings that pass through and connect between the semiconductor chips, and the plurality of semiconductor chips have a frequency and a phase.
  • a clock signal generation circuit that generates a plurality of different types of clock signals, a clock signal selection circuit that selects and outputs an arbitrary clock signal among input clock signals based on a control signal, and the clock signal selection circuit And a logic block to which the clock signal selected by each is supplied, and the clock signal selection circuit is input via an arbitrary clock signal generated by the clock signal generation circuit and a through wiring based on the control signal
  • Arbitrary clock signals are selected from clock signals generated by clock signal generation circuits provided on other semiconductor chips. And it is intended to switch to supply to the logic block.
  • the clock signal selection circuit is provided in the preceding stage of the clock input terminal of the logic block that operates in synchronization with the clock signal.
  • each of the plurality of semiconductor chips includes a delay circuit that delays a clock signal supplied to the logic block for an arbitrary time based on a control signal.
  • the clock signal selection circuit includes a programmable switch whose connection destination can be reconfigured according to a control signal.
  • the present invention is a semiconductor integrated circuit device having a plurality of stacked semiconductor chips and through wirings that penetrate and connect between the respective semiconductor chips, and the plurality of semiconductor chips have a frequency
  • a clock signal generation circuit that generates a plurality of types of clock signals having different phases
  • a first clock signal selection circuit that selects and outputs an arbitrary clock signal among the input clock signals based on the control signal
  • a second clock signal selection circuit provided after the first clock signal selection circuit for selecting and outputting an arbitrary clock signal and a clock signal selected by the second clock signal selection circuit are supplied.
  • a first clock signal selection circuit that generates an arbitrary clock generated by the clock signal generation circuit based on the control signal.
  • the second clock signal selection circuit Based on the control signal, the clock signal output from the first clock signal selection circuit and the clock signal output from the first clock signal selection circuit provided in another semiconductor chip input through the through wiring Is switched so that an arbitrary clock signal is selected and supplied to the logic block.
  • the second clock signal selection circuit is provided in a stage preceding the clock input terminal of the logic block.
  • each of the plurality of semiconductor chips includes a delay circuit that delays a clock signal supplied to the logic block for an arbitrary time based on a control signal.
  • the first and second clock signal selection circuits are composed of programmable switches whose connection destinations can be reconfigured according to a control signal.
  • the present invention provides at least one clock among a plurality of clock signal selection circuits provided in each semiconductor chip.
  • the clock signal is supplied to the synchronous memory element (logic block) in another layer via the signal selection circuit, and the clock signal options can be supplied to the memory element.
  • the through wiring is configured to be connected through a programmable switch that can change connection information after manufacture without physically connecting directly to the clock signal distribution circuit wiring provided in the semiconductor chip.
  • the wiring is not formed normally, the corresponding through wiring can be separated from the clock distribution circuit.
  • each semiconductor chip has a clock signal generation circuit, and each clock signal generation circuit is configured to distribute each clock signal to the entire laminated semiconductor chip by independently distributing the clock signal generation circuits.
  • each clock signal generation circuit is configured to distribute each clock signal to the entire laminated semiconductor chip by independently distributing the clock signal generation circuits.
  • a plurality of types of clock signals can be distributed to the stacked semiconductor chips without increasing the area of the circuit for distributing and supplying the clock signals.
  • FIG. 1 is an explanatory diagram showing an example of a semiconductor integrated circuit device according to a first embodiment of the present invention.
  • FIG. 2 is an explanatory diagram illustrating an example of a configuration of a part of programmable switches in a clock signal selection circuit provided in the semiconductor integrated circuit device of FIG. 1.
  • FIG. 3 is a cross-sectional view showing a cross section A-A ′ of FIG. 2.
  • FIG. 2 is an explanatory diagram illustrating an example of a more specific configuration of the semiconductor integrated circuit device of FIG. 1. It is explanatory drawing which shows an example of the semiconductor integrated circuit device by Embodiment 2 of this invention. It is explanatory drawing which shows an example of the semiconductor integrated circuit device by Embodiment 3 of this invention.
  • FIG. 1 is an explanatory diagram showing an example of a semiconductor integrated circuit device according to a first embodiment of the present invention.
  • FIG. 2 is a configuration of a part of programmable switches in a clock signal selection circuit provided in the semiconductor integrated circuit device of FIG.
  • FIG. 3 is a sectional view showing an AA ′ section of FIG. 2
  • FIG. 4 is an explanatory view showing an example of a more specific configuration of the semiconductor integrated circuit device of FIG.
  • the semiconductor integrated circuit device 1 has a so-called stacked structure in which semiconductor chips 2 to 4 are stacked as shown in FIG.
  • the semiconductor integrated circuit device 1 is provided with an interposer (not shown) which is a wiring board.
  • interposer On the back surface of the interposer, connection electrodes (not shown) arranged in an array are formed.
  • semiconductor chips 2 to 4 are stacked on the main surface of the interposer.
  • the semiconductor chip 2 has a configuration including a clock distribution circuit 5, a control circuit 6, and a logic circuit 7 such as a flip-flop serving as a logic block.
  • the semiconductor chip 3 includes a logic circuit 10 serving as a logic block such as a clock distribution circuit 8, a control circuit 9, and a flip-flop.
  • the semiconductor chip 4 includes a clock distribution circuit 11, a control circuit 12, and a flip-flop.
  • the configuration includes a logic circuit 13 serving as a logic block.
  • the clock distribution circuit 5 includes a clock signal generation circuit 14, a clock signal selection circuit 15, and a clock signal selection circuit 16.
  • the clock distribution circuit 8 includes a clock signal generation circuit 17, a clock signal selection circuit 18, and a clock signal selection circuit 19.
  • the clock distribution circuit 11 includes a clock signal generation circuit 20, a clock signal selection circuit 21, and a clock signal selection circuit 22.
  • the clock signal selection circuit 16 provided in the lowermost semiconductor chip 2 and the clock signal selection circuit 19 provided in the semiconductor chip 3 stacked on the semiconductor chip 2 are formed through silicon vias. 23 and 24, respectively.
  • the clock signal selection circuit 19 provided in the semiconductor chip 3 and the clock signal selection circuit 22 provided in the uppermost semiconductor chip 4 stacked on the semiconductor chip 3 are formed by through silicon vias 25, 26, respectively.
  • the through-silicon vias 23 to 26 are formed by forming holes in the silicon of the semiconductor chips 2 to 4 and filling the holes with conductors, thereby allowing the surface of the semiconductor chip 2 and the back surface of the semiconductor chip 3 and the surface of the semiconductor chip 3 and the semiconductor to be filled.
  • the back surfaces of the chips 4 are electrically connected to each other.
  • the clock signal generation circuits 14, 17, and 20 independently generate a plurality of types of clock signals having different frequencies and phases based on a reference oscillation signal CRY inputted from the outside, and these clock signals are connected to the subsequent stage. Are supplied to the clock signal selection circuits 15, 18, 21 and the like.
  • the clock signal selection circuits 15, 16, 18, 19, 21, and 22 are composed of a plurality of programmable switches that can be reconfigured after manufacture, and by appropriately setting these programmable switches, Distribute the clock signal.
  • clock signal selection circuits are provided for one semiconductor chip.
  • the number of clock signal selection circuits is not limited to this, and the number is three or more. Also good.
  • the number of input units and output units of the clock signal selection circuit is shown when the number of input units is larger than the number of output signal lines, but the present invention is limited to this configuration. There is no essential difference when the number of input parts is less than or equal to the number of output parts.
  • the clock signal selection circuits 15, 18, and 21 have, for example, five input units and two output units, respectively, and five types of clock signals generated by the clock signal generation circuits 14, 17, and 20 are respectively provided. Connected to input.
  • the clock signal selection circuits 15, 18, and 21 are arbitrarily selected from the five types of clock signals generated by the clock signal generation circuits 14, 17, and 20 based on the control signals output from the control circuits 6, 9, and 12. Two clock signals are selected and output to the two output units, respectively.
  • the clock signal selection circuits 16, 19, and 22 are each provided with terminals T1 to T7. Two output portions of the clock signal selection circuits 15, 18, and 21 are connected to the terminals T1 and T2, respectively, and input portions of the logic circuits 7, 10, and 13 are connected to the terminal T3, respectively.
  • one connection portion of the through silicon vias 23 and 24 is connected to the terminals T6 and T7 of the clock signal selection circuit 16, and the through silicon via is connected to the terminals T4 and T5 of the clock signal selection circuit 19.
  • the other connecting portions 23 and 24 are connected to each other.
  • connection portion of the through silicon vias 25 and 26 is connected to the terminals T6 and T7 of the clock signal selection circuit 19, respectively, and the through silicon via 25 and 25 are connected to the terminals T4 and T5 of the clock signal selection circuit 22, respectively.
  • the other connection part of 26 is connected.
  • the clock signal selection circuits 16, 19, and 22 have a configuration in which programmable switches are arranged between all the terminals T1 to T7.
  • the dotted lines shown in the figure each represent the connection configuration of the programmable switches between the terminals T1 to T7.
  • the terminal T3 includes all the other terminals T1, T2, and T2. This shows a configuration in which a programmable switch is provided between T4 and T7.
  • the clock signal selection circuits 16 and 22 have a configuration in which programmable switches are arranged between all the terminals T1 to T7.
  • the on / off information (control signal) of the programmable switches in the clock signal selection circuits 16, 19, and 22 is stored in advance in, for example, a memory or a register, and the control circuits 6, 9, and 12 are stored in the on / off information stored therein.
  • the on / off state of the programmable switch is controlled based on the off information (control signal).
  • FIG. 2 is an explanatory diagram showing an example of the configuration of some programmable switches in the clock signal selection circuit 19 of the semiconductor chip 3 and the clock signal selection circuit 22 of the semiconductor chip 4 stacked above the semiconductor chip 3. .
  • programmable switches SW1 to SW6 connected to terminals T1 to T5 in the clock signal selection circuit 19 and programmable switches SW7 connected to terminals T1 to T5 in the clock signal selection circuit 22 for simplification. Only SW12 is shown.
  • a terminal T5 is connected to one connection portion of the programmable switch SW1, and a terminal T4 is connected to the other connection portion of the programmable switch SW1.
  • one connection part is composed of two connection parts including a first connection part and a second connection part, and the terminal T1 is connected to the first connection part, and the second connection part. Is connected to a terminal T2.
  • a terminal T5 is connected to the other connection portion of the programmable switch SW4.
  • one connection portion is composed of two connection portions, a first connection portion and a second connection portion.
  • a terminal T1 is connected to the first connection portion of the programmable switch SW1
  • a terminal T2 is connected to the second connection portion
  • a terminal T4 is connected to the other connection portion of the programmable switch SW1.
  • the terminal T4 is connected to one connection part of the programmable switch SW3, and the terminal T3 is connected to the other connection part of the programmable switch SW3.
  • a terminal T5 is connected to one connection portion of the programmable switch SW6, and a terminal T3 is connected to the other connection portion of the programmable switch SW6.
  • one connection part is comprised from two connection parts of the 1st and 2nd connection part.
  • a terminal T1 is connected to the first connection portion of the programmable switch SW5
  • a terminal T2 is connected to the second connection portion
  • a terminal T3 is connected to the other connection portion of the programmable switch SW5. It is connected.
  • clock signal selection circuit 22 is manufactured from the same mask, and thus has the same connection configuration as the clock signal selection circuit 19.
  • FIG. 3 is a cross-sectional view showing the A-A ′ cross section of FIG.
  • FIG. 3 is a diagram focusing on the programmable switch SW1 provided in the clock signal selection circuit 19 and the programmable switch SW7 provided in the clock signal selection circuit 22, except for the wiring connected to the programmable switches SW1 and SW7. Is omitted.
  • the programmable switches SW1 (SW2 to SW6) and SW7 (to SW12) are formed by MOS (Metal Oxide Semiconductor) transistors.
  • the terminal T4 is connected to one connection part of the transistor constituting the programmable switch SW1, and the terminal T5 is connected to the other connection part of the transistor.
  • the terminal T5 is connected to one connection portion of the through silicon via 25 via an electrode D such as a bump, for example.
  • connection portion of the through silicon via 25 is connected to the terminal T4 of the clock signal selection circuit 22, and one connection portion of the transistor constituting the programmable switch SW7 is connected to the terminal T4.
  • a terminal T5 is connected to the other connection portion of the transistor constituting the programmable switch SW7.
  • FIG. 3 shows an example in which the programmable switch is formed by a MOS transistor, but the programmable switch is not limited to a MOS transistor.
  • it can be configured by a switch or the like with an element having two or more terminals, which is nonlinear as represented by a fuse and has a hysteresis characteristic.
  • the through silicon vias 23 and 25 are not formed as a continuous conductor, but are connected via the programmable switches SW1 and SW7, respectively (the same applies to the through silicon vias 24 and 26). They are not formed as a series of conductors, but are connected via programmable switches).
  • FIG. 4 is an explanatory diagram showing an example of a more specific configuration of the semiconductor integrated circuit device 1.
  • the semiconductor integrated circuit device 1 includes semiconductor chips 2 to 4.
  • the semiconductor chip 2 includes a clock distribution circuit 5, a control circuit 6, and logic circuits 7, 7a, 7b. *
  • the semiconductor chip 3 includes a clock distribution circuit 8, a control circuit 9, and logic circuits 10, 10a, and 10b.
  • the semiconductor chip 4 includes a clock distribution circuit 11, a control circuit 12, and logic circuits 13, 13a, and 13b. It is the composition provided with.
  • the clock distribution circuit 5 includes a clock signal generation circuit 14 and clock signal selection circuits 15 and 16, and the clock distribution circuit 8 includes a clock signal generation circuit 17 and clock signal selection circuits 18 and 19.
  • the circuit 11 includes a clock signal generation circuit 20 and clock signal selection circuits 21 and 22.
  • the semiconductor integrated circuit device 1 shown in FIG. 4 shows an example in which three types of clock signals CK1 to CK3 are input to the logic circuits 7, 7a, 7b, 10, 10a, 10b, 13, 13a, 13b. Yes.
  • the clock signal generation circuits 14, 17, and 20 independently generate six types of clock signals having different frequencies and phases based on the reference oscillation signal CRY inputted from the outside, and these clock signals are provided in the subsequent stages.
  • the clock signals are supplied to the connected clock signal selection circuits 15, 18, 21 and the like.
  • the clock signal selection circuits 15, 18, 21 are based on the control signals from the control circuits 6, 9, 12, and any four types of clocks from the six types of clock signals generated by the clock signal generation circuits 14, 17, 20 respectively. Select and output the signal.
  • the clock signal selection circuits 16, 19, and 22 have a configuration in which terminals T8 to T15 are newly provided in the clock signal selection circuits 16, 19, and 22 of FIG.
  • the through vias 23a, 24a, 25a, and 26a are newly added.
  • the terminals T8 and T9 are connected to the output section of the clock signal selection circuit 18.
  • the terminal T10 is connected to one connecting portion of the through silicon via 23a, and the terminal T11 is connected to one connecting portion of the through silicon via 24a.
  • the terminal T12 of the clock signal selection circuit 19 is connected to one connection part of the through silicon via 25a, and the terminal T13 is connected to one connection part of the through silicon via 26a.
  • the terminals T14 and T15 of the clock signal selection circuit 19 are connected to the input parts of the logic circuits 10a and 10b, respectively.
  • the terminals T8 and T9 of the clock signal selection circuit 16 are connected to the output part of the clock signal selection circuit 15, and the terminals T12 and T13 are connected to the other connection part of the through silicon vias 23a and 24a, respectively.
  • the terminals T14 and T15 of the clock signal selection circuit 16 are connected to the input parts of the logic circuits 7a and 7b, respectively.
  • the terminals T8 and T9 of the clock signal selection circuit 22 are connected to the output part of the clock signal selection circuit 21, and the terminals T10 and T11 are connected to the other connection part of the through silicon vias 25a and 26a, respectively.
  • the terminals T14 and T15 of the clock signal selection circuit 22 are connected to the input parts of the logic circuits 13a and 13b, respectively.
  • the other connection configurations are the same as those shown in FIG.
  • the clock signal CK1 generated by the clock signal generation circuit 14 is supplied to the logic circuits 7, 10, and 13, respectively, and the clock signal CK2 generated by the clock signal generation circuit 17 is supplied to the logic circuits 7a, 10a, and 13a, respectively.
  • the clock signal CK3 generated by the clock signal generation circuit 20 is supplied to the logic circuits 7b, 10b, and 13b, and the paths shown by the solid lines are the supply paths of the clock signals CK1 to CK3.
  • the clock signal CK3 is supplied to the logic circuits 7b and 10b via the through-silicon via 26a.
  • the through-silicon via 26a is not normally formed, the through-silicon via All programmable switches connected to 26a are turned off and clock signals are supplied using other normally formed through-silicon vias that are not utilized.
  • the programmable switch is operated so that the path indicated by the alternate long and short dash line is formed using the through silicon via 25a, and the clock signal CK3 is supplied to the logic circuits 7b and 10b, respectively.
  • the semiconductor chip 2 to 4 are provided with the clock distribution circuits 5, 8, and 11, respectively, the layout area of the semiconductor chips 2 to 4 is reduced as compared with the case where the clock distribution circuit is provided in one semiconductor chip. be able to.
  • clock distribution circuit in each of the semiconductor chips 2 to 4, it is possible to suppress variations in power consumption of each of the semiconductor chips 2 to 4, thereby reducing temperature variations between the semiconductor chips. In addition, clock skew caused by temperature variation can be suppressed.
  • the clock signal is supplied to other semiconductor chips by the clock signal selection circuits 16, 19, and 22 provided in the preceding stage of the logic circuits 7, 7a, 7b, 10, 10a, 10b, 13, 13a, and 13b. It is possible to reduce the influence of clock skew due to manufacturing variations of semiconductor chips.
  • FIG. 5 is an explanatory diagram showing an example of a semiconductor integrated circuit device according to the second embodiment of the present invention.
  • the semiconductor integrated circuit device 1 has a stacked structure similar to that of FIG. 4 of the first embodiment, in which the semiconductor chips 2 to 4 are laminated, as shown in FIG.
  • the semiconductor chips 2 to 4 include clock distribution circuits 5, 8, 11, control circuits 6, 9, 12, and logic circuits 7, 7 a, 7 b, 10, 10 a, and flip-flops. 10b, 13, 13a, and 13b are provided.
  • the clock distribution circuit 5 includes a clock signal generation circuit 14 and clock signal selection circuits 15 and 16 as in FIG.
  • the clock distribution circuit 8 includes a clock signal generation circuit 17 and clock signal selection circuits 18 and 19, and the clock distribution circuit 11 includes a clock signal generation circuit 20 and clock signal selection circuits 21 and 22.
  • the semiconductor integrated circuit device 1 shown in FIG. 5 is different from FIG. 4 in that it is provided in the clock signal selection circuit 15 provided in the lowermost semiconductor chip 2 and the semiconductor chip 3 stacked on the semiconductor chip 2.
  • the clock signal selection circuit 18 is connected through the through silicon via 27, and the clock signal selection circuit 18 provided in the semiconductor chip 3 and the clock signal provided in the semiconductor chip 4 stacked above the semiconductor chip 3 are connected.
  • the selection circuit 21 is connected through a through silicon via 28.
  • clock signal selection circuit 16 of the semiconductor chip 2 and the clock signal selection circuit 19 of the semiconductor chip 3 are connected via the through silicon via 23, and the clock signal selection circuit 19 and the clock signal selection circuit 22 of the semiconductor chip 4 are connected. However, the connection is made through the through-silicon via 25.
  • the clock signal selection circuits 15, 18, and 21 are configured to include terminals T14 to T21, respectively, and the clock signal selection circuits 16, 19, and 22 are configured to include terminals T22 to T28, respectively.
  • the terminals T14 to T17 are connected to the four types of clock signals generated by the clock signal generation circuits 14, 17, and 20, respectively.
  • terminal T18 is connected to the terminal T23 of the clock signal selection circuits 16, 19, and 22, respectively, and the terminal T19 is connected to the terminal T22 of the clock signal selection circuits 16, 19, and 22, respectively.
  • connection portion of the through silicon via 27 is connected to the terminal T21 of the clock signal selection circuit 15, and the terminal T20 of the clock signal selection circuit 18 is connected to the other connection portion of the through silicon via 27. ing.
  • connection portion of the through silicon via 28 is connected to the terminal T21 of the clock signal selection circuit 18, and the terminal T20 of the clock signal selection circuit 21 is connected to the other connection portion of the through silicon via 28. ing.
  • the input portions of the logic circuits 7, 7a, 7b, the logic circuits 10, 10a, 10b, and the logic circuits 13, 13a, 13b are connected to the terminals T24 to T26 of the clock signal selection circuits 16, 19, 22, respectively.
  • connection portion of the through silicon via 23 is connected to the terminal T28 of the clock signal selection circuit 16, and the terminal T27 of the clock signal selection circuit 19 is connected to the other connection portion of the through silicon via 28. ing.
  • connection portion of the through silicon via 25 is connected to the terminal T28 of the clock signal selection circuit 19, and the terminal T27 of the clock signal selection circuit 22 is connected to the other connection portion of the through silicon via 25. ing.
  • the clock signal selection circuits 15, 18, and 21 have a configuration in which programmable switches are arranged between all the terminals T14 to T21.
  • the clock signal selection circuits 16, 19, and 22 have all the terminals T22 to T28. Each of them has a configuration in which programmable switches are arranged therebetween.
  • the clock signal can be distributed to other semiconductor chips via through silicon vias at a level closer to the end of the clock distribution circuits 5, 8, and 11, so that The horizontal distribution distance can be shortened, and the clock skew can be further suppressed.
  • the clock signal CK4 generated by the clock signal generation circuit 14 is supplied to the logic circuit 13a of the semiconductor chip 4, and the clock signal CK5 generated by the clock signal generation circuit 17 is supplied to the logic circuit 13b of the semiconductor chip 4.
  • the connection paths of the respective programmable switches are indicated by solid lines in the clock signal selection circuits 15, 16, 18, 19, 21, and 22.
  • the through silicon via 27 that connects the clock signal selection circuit 15 and the clock signal selection circuit 18 and the through silicon via 28 that connects the clock signal selection circuit 18 and the clock signal selection circuit 21, respectively.
  • the clock signals CK4 and CK5 generated by the semiconductor chips 2 and 3 can be supplied to the logic circuits 13, 13a and 13b of the semiconductor chip 4, respectively. Therefore, the degree of freedom for distributing the clock signal can be increased.
  • which of the clock signals CK4 and CK5 is supplied to another semiconductor chip by the clock signal selection circuit at the end of the clock distribution circuits 5 and 8 is a circuit that operates in synchronization with the clock signals CK4 and CK5. Is determined by the size of the clock skew allowed.
  • the through-silicon via 25 which is as far as possible to the end of the clock distribution circuit is provided for the distribution of the clock signal CK5. I use it.
  • one through-silicon via (19, 22) is connected to the clock signal selection circuit 16, the clock signal selection circuit 19, and the clock signal selection circuit 16 and the clock signal selection circuit 22, respectively.
  • the number of these through silicon vias is not limited and may be plural.
  • the number of programmable switches in the clock signal selection circuits 15, 18, and 21 is not provided so as to be connected to all terminals, but may be configured to reduce the number of programmable switches connected to arbitrary terminals. .
  • FIG. 6 is an explanatory diagram showing an example of a semiconductor integrated circuit device according to the third embodiment of the present invention.
  • the semiconductor integrated circuit device 1 has a stacked structure in which semiconductor chips 2 and 3 are stacked.
  • the semiconductor chip 2 includes a clock distribution circuit 5 and a control circuit. 6 and a logic circuit 7 such as a flip-flop, a variable delay element circuit 29 is newly provided in the same configuration as in FIG. 1, and the semiconductor chip 3 includes a clock distribution circuit 8, a control circuit 9, and a flip-flop.
  • a variable delay element circuit 29a is newly provided in the same configuration as that of FIG.
  • the clock distribution circuit 5 includes a clock signal generation circuit 14 and clock signal selection circuits 15 and 16.
  • the clock distribution circuit 8 includes a clock signal generation circuit 17 and a clock signal selection circuit 18. , 19.
  • the clock signal selection circuits 16 and 19 have terminals T29 to T37, respectively. In the clock signal selection circuits 16 and 19, the terminals T29 and T30 are connected so that two types of clock signals output from the clock signal selection circuits 15 and 18 are input.
  • One connection portion of the through silicon vias 23, 24, and 24a is connected to the terminals T35 to T37 of the clock signal selection circuit 16, respectively, and the other connection portion of the through silicon vias 23, 24, and 24a is connected to the terminals T35 to T37.
  • the terminals T32 to T34 of the clock signal selection circuit 19 are connected to each other.
  • variable delay element circuit 29 is connected to the terminal T31 of the clock signal selection circuit 16 and the input portion of the variable delay element circuit 29a is connected to the terminal T31 of the clock signal selection circuit 19. Yes.
  • variable delay element circuit 29 The output section of the variable delay element circuit 29 is connected to the input section of the logic circuit 7, and the output section of the variable delay element circuit 29a is connected to the input section of the logic circuit 10. Based on the control signal output from the control circuit 6, the variable delay element circuit 29 delays the clock signal output from the clock signal selection circuit 16 by an arbitrary time and outputs it. The variable delay element circuit 29a delays the clock signal output from the clock signal selection circuit 19 by an arbitrary time based on the control signal output from the control circuit 9, and outputs the delayed signal.
  • variable delay element circuits 29 and 29a are provided for the purpose of adjusting the clock skew by the propagation of the clock signal through the through silicon via.
  • the delay time of the variable delay element circuit 29 is adjusted, and the logic The arrival times of the clock signals to the circuits 7 and 10 are made substantially the same.
  • the delay amounts of the variable delay element circuits 29 and 29a can be determined based on the information because the respective paths are known when the distribution paths of the respective clock signals are determined.
  • control circuits 6 and 9 are reconfigured similarly to the control of the on / off information of the programmable switch of the clock signal selection circuit. Control the amount of delay when configuring possible circuits.
  • variable delay element If a variable delay element is used, clock skew due to variations between semiconductor chips can be suppressed in principle. However, clock skew suppression by a variable delay element generally increases the required circuit scale according to the amount of delay time to be compensated.
  • variable delay element circuits 29 and 29a have a structure for compensating for the difference in distribution distance due to the through silicon vias. Therefore, the characteristics of the through silicon vias in the use manufacturing process are evaluated in advance. In this case, the variable delay amount can be easily controlled automatically at the stage of the placement and routing process. Further, since the expected clock skew is smaller than the clock skew due to the variation between the semiconductor chips, the circuit area required for the variable delay element circuits 29 and 29a can be kept small.
  • FIG. 7 is an explanatory diagram showing an example of the configuration of some programmable switches in the clock signal selection circuit provided in the semiconductor integrated circuit device according to the fourth embodiment of the present invention.
  • the semiconductor integrated circuit device 1 has a stacked structure in which the semiconductor chips 2 to 4 are stacked, as in FIG. 1 of the first embodiment.
  • the configuration of the semiconductor chips 2 to 4 is the same as that of FIG. 1 of the first embodiment, but the connection configuration of the programmable switches in the clock signal selection circuits 16, 19, and 22 is different.
  • FIG. 7 is an explanatory diagram showing an example of the configuration of part of the programmable switches in the clock signal selection circuit 19 of the semiconductor chip 3 and the clock signal selection circuit 22 of the semiconductor chip 4 stacked above the semiconductor chip 3. .
  • the clock signal selection circuits 19 and 22 have terminals T1 to T7.
  • the programmable switches SW13 to SW5 connected to the terminals T1 to T5 in the clock signal selection circuit 19 are provided.
  • SW15 and programmable switches SW16 to SW18 connected to terminals T1 to T5 in the clock signal selection circuit 22 are shown.
  • a terminal T5 is connected to one connection portion of the programmable switch SW13, and a terminal T4 is connected to the other connection portion of the programmable switch SW13.
  • one connection portion is composed of two connection portions including a first connection portion and a second connection portion, and the terminal T1 is connected to the first connection portion, and the second connection portion. Is connected to a terminal T2.
  • a terminal T4 is connected to the other connection portion of the programmable switch SW14.
  • the terminal T4 is connected to one connection portion of the programmable switch SW15, and the terminal T3 is connected to the other connection portion of the programmable switch SW15.
  • the programmable switches SW16 to SW18 of the clock signal selection circuit 21 have the same connection configuration.
  • the load capacity of the clock signal distribution circuit is reduced by reducing the number of programmable switches connected to the terminal T5, for example, without providing programmable switches for all the terminals T1 to T7. It becomes possible. Therefore, the delay time, area, power consumption, etc. of the clock signal distribution circuit can be further improved.
  • FIG. 8 is an explanatory diagram showing an example of a semiconductor integrated circuit device according to the fifth embodiment of the present invention.
  • the semiconductor integrated circuit device 1 has a stacked structure in which semiconductor chips 2 to 4 are stacked as shown in FIG.
  • the semiconductor chip 2 is provided with a clock distribution circuit 5, a peripheral circuit 30, and a reconfigurable circuit 31.
  • the semiconductor chip 3 is provided with a reconfigurable circuit 33 such as a clock distribution circuit 8, a peripheral circuit 32, and an FPGA.
  • the semiconductor chip 4 includes a clock distribution circuit 11, a peripheral circuit 34, and an FPGA.
  • a reconfigurable circuit 35 is provided.
  • peripheral circuits 30, 32, and 34 are, for example, peripheral circuits such as a central processing circuit (CPU) and a memory circuit, and the reconfigurable circuits 31, 33, and 35 are, for example, an FPGA.
  • the clock distribution circuit 5 includes a clock signal generation circuit 14 and clock signal selection circuits 15 and 16 shown in FIG.
  • the clock distribution circuit 8 includes a clock signal generation circuit 17 and clock signal selection circuits 18 and 19 shown in FIG. 1.
  • the clock distribution circuit 11 includes a clock signal generation circuit 20 and a clock signal selection circuit shown in FIG. 21 and 22.
  • the clock signal generation circuits 14, 17, and 20 are connected so that the reference oscillation signal CRY input from the outside is input through the through silicon vias 36 and 37, respectively.
  • the clock signal generation circuits 14, 17, and 20 generate a plurality of types of clock signals having different frequencies and phases from the reference oscillation signal CRY.
  • the reconfigurable circuit 31 includes circuit blocks 31a to 31d
  • the reconfigurable circuit 33 includes circuit blocks 33a to 33d
  • the reconfigurable circuit 35 includes circuit blocks 35a to 35d. Each is provided.
  • the reconfigurable circuit 31 and the reconfigurable circuit 33 are connected via through silicon vias 23 and 24, and the reconfigurable circuit 33 and the reconfigurable circuit 35 are connected through silicon through vias 25 and 26. Connected.
  • Reconfigurable circuits 31, 33, and 35 are each supplied with a clock signal by the technique shown in the first embodiment.
  • the specific clock signal supply technique is the same as that of the first embodiment, and thus the description thereof is omitted here.
  • the clock signal generated by the clock distribution circuit 5 of the semiconductor chip 2 is distributed to the circuit blocks 31b, 31d, 33a, and 35d, and the circuit blocks 31c, 33c, 33d,
  • the clock signal generated by the clock distribution circuit 8 of the semiconductor chip 3 is distributed to 35a
  • the synchronized clock generated by the clock distribution circuit 11 of the semiconductor chip 4 is distributed to the circuit blocks 31a, 33b, 35b, and 35d. The signal is distributed.
  • the circuit blocks 31b, 33c, and 35b are circuits formed at the interface between the reconfigurable circuits 31, 33, and 35 and the peripheral circuits 30, 32, and 34, respectively.
  • the circuit block 31b is provided with the clock signal selection circuits 15 and 16 shown in FIG. 1, and the circuit blocks 33c and 35b are the clock signal selection circuits 18 and 19 (FIG. 1) and the clock signal selection circuits 21 and 22, respectively. (FIG. 1) is provided.
  • peripheral circuit 30 and the circuit blocks 31b, 31d, 33a, and 35c are respectively input with the clock signal CK1 generated by the clock signal generation circuit 14 of the semiconductor chip 2, and the peripheral circuit 32 and the circuit blocks 31c, 33c,
  • the clock signal CK2 generated by the clock signal generation circuit 17 of the semiconductor chip 3 is input to 33d and 35a, respectively.
  • clock signal CK3 generated by the clock signal generation circuit 20 of the semiconductor chip 4 is input to the peripheral circuit 34 and the circuit blocks 31a, 33b, 35b, and 35d, respectively.
  • the hatching, vertical line, and horizontal line shown in FIG. 8 indicate clock signals to be supplied.
  • the clock signal CK1 is indicated by a vertical line in the hatched block.
  • the clock signal CK2 is supplied, and in the block with the horizontal line, the clock signal CK3 is supplied.
  • the synchronized clock signal CK1 generated by the clock signal generation circuit 14 is input to the peripheral circuit 30 and the circuit blocks 31b and 31d, they are synchronized without being affected by variations between semiconductor chips. It is possible to perform an operation.
  • the synchronized clock signals CK2 and CK3 generated by the clock signal generation circuits 17 and 20 are input, respectively. Synchronous operation can be performed without being affected by variations between chips.
  • circuit blocks 31b, 31d, 33a, and 35c can supply the synchronized clock signal CK1 by the technique described in the first embodiment, the circuit blocks can perform the synchronous operation. .
  • circuit blocks 31c, 33c, 33d, and 35a and the circuit blocks 31a, 33b, 35b, and 35d also supply synchronized clock signals CK2 and CK2, respectively, by the technique described in the first embodiment.
  • Each of these circuit blocks can perform a synchronous operation.
  • the peripheral circuit 30 can perform a synchronous operation with the circuit blocks 33a and 35c of the other semiconductor chip 3 via the circuit block 31b which is an interface circuit in the reconfigurable circuit 31.
  • peripheral circuit 32 is connected to the circuit block 31c of the semiconductor chip 2 and the circuit block 35a of the semiconductor chip 4 via the circuit block 33c that is an interface circuit
  • peripheral circuit 34 is a circuit that is an interface circuit. Synchronous operations can be performed between the circuit block 33b of the semiconductor chip 3 and the circuit block 31a of the semiconductor chip 2 via the block 35b.
  • the present invention is suitable for a clock supply technique in a semiconductor integrated circuit device having a configuration in which a plurality of semiconductor chips are stacked.

Abstract

When distributing various types of clock signals to a plurality of laminated semiconductor chips, the clock signals are efficiently supplied without reducing the selectivity of the clock signals. Clock signal selecting circuits (15, 18, 21) respectively select, on the basis of control signals outputted from control circuits (6, 9, 12), two given clock signals from among five types of clock signals generated by means of clock signal generating circuits (14, 17, 20), and respectively output each of the selected clock signals to two output units. Clock signal selecting circuits (16, 19, 22) are configured from a plurality of programmable switches capable of reconfiguring after a connection destination is established. The clock signals outputted from the clock signal selecting circuits (15, 18, 21) are respectively distributed to logic circuits (7, 10, 13) by properly setting the programmable switches.

Description

半導体集積回路装置Semiconductor integrated circuit device
　本発明は、半導体集積回路装置におけるクロック信号の供給技術に関し、特に、複数の半導体チップが積層された構成におけるクロック信号の分配に有効な技術に関する。 The present invention relates to a clock signal supply technique in a semiconductor integrated circuit device, and more particularly to a technique effective for distributing a clock signal in a configuration in which a plurality of semiconductor chips are stacked.
　近年、半導体集積回路装置は、素子サイズの微細化により、回路規模・性能の両面において進歩を遂げている。すなわち、面積あたりに搭載可能な素子数増加により、より複雑で大規模な回路を単一の半導体チップ上に集積することが可能となると同時に、素子のスイッチング特性向上により、回路の動作速度向上が図られてきた。 In recent years, semiconductor integrated circuit devices have advanced in both circuit scale and performance due to miniaturization of element size. In other words, an increase in the number of elements that can be mounted per area makes it possible to integrate a more complex and large-scale circuit on a single semiconductor chip, and at the same time improves the operation speed of the circuit by improving the switching characteristics of the elements. It has been planned.
　しかし、素子の微細化技術そのものの限界、配線遅延時間の増大、最先端プロセスの利用コストの増大などの理由から、回路を単一の半導体チップの水平面上に集積化することによる性能向上が必ずしも最適解ではなくなってきている。 However, due to the limitations of element miniaturization technology itself, an increase in wiring delay time, and an increase in the cost of using cutting-edge processes, it is not always possible to improve performance by integrating circuits on the horizontal plane of a single semiconductor chip It is no longer the optimal solution.
　そこで、更なる集積化技術として、複数の半導体チップを積層化する、いわゆるチップオンチップ技術が注目されている。このチップオンチップ技術による半導体集積回路装置では、半導体チップが積層されていない半導体集積回路装置に比べて回路の平均配線長を減らす効果が見込まれるため、配線遅延時間の減少が見込まれる。 Therefore, as a further integration technique, a so-called chip-on-chip technique in which a plurality of semiconductor chips are stacked is attracting attention. In the semiconductor integrated circuit device based on this chip-on-chip technology, the effect of reducing the average wiring length of the circuit is expected as compared with the semiconductor integrated circuit device in which the semiconductor chips are not stacked, so that the wiring delay time is expected to decrease.
　この種の積層技術には、同一のマスクから製造される複数の半導体チップを積層するホモチップ積層技術と、異なる複数のマスクから製造される複数の半導体チップを積層するヘテロチップ積層技術がある。 This type of stacking technique includes a homochip stacking technique in which a plurality of semiconductor chips manufactured from the same mask are stacked, and a hetero chip stacking technique in which a plurality of semiconductor chips manufactured from a plurality of different masks are stacked.
　積層半導体チップにより所望の機能および性能を実現するには、積層される半導体チップ間を電気的に接続する技術が必要となる。積層半導体チップ間の接続技術には、たとえば、半導体チップのシリコンに孔を開け、その孔に導体を充填することでチップの表面と裏面を電気的に接続するシリコン貫通ビア（ＴＳＶ：Through Silicon Via）方式がある。 In order to realize a desired function and performance with a laminated semiconductor chip, a technique for electrically connecting the laminated semiconductor chips is required. As a connection technology between the stacked semiconductor chips, for example, a through-silicon via (TSV: Through Silicon Via) that electrically connects the front surface and the back surface of the chip by opening a hole in the silicon of the semiconductor chip and filling the hole with a conductor. ) There is a method.
　このＴＳＶ方式は、半導体チップ上の金属配線に迫るほど積層方向の電極（３次元電極）を微細化できると見込まれており、次世代の接続技術として有望視されている。 This TSV method is expected to be capable of miniaturizing electrodes in the stacking direction (three-dimensional electrodes) as it approaches metal wiring on a semiconductor chip, and is promising as a next-generation connection technology.
　一方、同様に最先端プロセスの利用コスト増大などの理由から、半導体集積回路装置の製造後に回路構成情報を適時修正可能なＦＰＧＡ(Field Programmable Gate Array)などの再構成可能回路が注目を集めている。 On the other hand, reconfigurable circuits such as FPGA (Field Programmable Gate Gate Array) that can correct circuit configuration information in a timely manner after the manufacture of a semiconductor integrated circuit device are attracting attention for the reason of increasing the use cost of the most advanced processes. .
　将来は複数の半導体集積回路装置に跨って３次元配線で相互に接続された論理回路が構成されるようになると考えられ、ＦＰＧＡなどの再構成可能回路も３次元配線で相互に接続されるようになると考えられる。 In the future, it is considered that logic circuits connected to each other by three-dimensional wiring are formed across a plurality of semiconductor integrated circuit devices, and reconfigurable circuits such as FPGAs are also connected to each other by three-dimensional wiring. It is thought that it becomes.
　論理回路は、クロック信号に同期して回路全体が演算やデータの送受信を行う同期回路方式と、論理回路を構成する回路同士が独立に演算やデータの送受信を行う非同期回路方式の２つの実装方式がある。 The logic circuit has two mounting systems: a synchronous circuit system in which the entire circuit performs operations and data transmission / reception in synchronization with a clock signal, and an asynchronous circuit system in which the circuits constituting the logic circuit independently perform operations and data transmission / reception There is.
　現在は、タイミング解析の容易さ、およびそのタイミング解析容易性に由来する設計自動化技術化の普及により、論理回路を実装する場合、同期回路方式による実装が主流である。 At present, due to the ease of timing analysis and the spread of design automation technology derived from the ease of timing analysis, the implementation by the synchronous circuit method is the mainstream when mounting logic circuits.
　同期回路方式では、データの送受信を行うそれぞれの記憶素子に入力されるクロック信号の時間的なずれ、クロックスキューを極力抑える必要がある。特に、同期させる回路を複数の半導体チップに跨る積層半導体チップに実装する場合、複数の積層された半導体チップ間においてデータをクロック信号に同期させる必要がある。そのため、複数の半導体チップ間に跨る記憶素子へ入力されるクロック信号のスキューを抑えることが必要となる。 In the synchronous circuit method, it is necessary to suppress the time lag and clock skew of the clock signal input to each storage element that transmits and receives data as much as possible. In particular, when a circuit to be synchronized is mounted on a stacked semiconductor chip across a plurality of semiconductor chips, it is necessary to synchronize data with a clock signal between the plurality of stacked semiconductor chips. For this reason, it is necessary to suppress the skew of the clock signal input to the memory element across the plurality of semiconductor chips.
　クロックスキューは、製造上のばらつきに起因するトランジスタの性能のばらつきや、回路動作時の半導体集積回路装置内の温度ばらつきに起因するトランジスタ性能のばらつきなど、様々な条件のばらつきにより発生する。 The clock skew occurs due to variations in various conditions such as variations in transistor performance due to manufacturing variations and variations in transistor performance due to temperature variations in the semiconductor integrated circuit device during circuit operation.
　単一の半導体チップ内で水平方向に回路を展開する場合、同期回路は単一のウエハに製造されるため、ウエハ内の製造ばらつきを考慮したクロックスキュー抑制技術が多く研究開発されてきた。 When developing a circuit in a horizontal direction within a single semiconductor chip, a synchronous circuit is manufactured on a single wafer, and therefore many clock skew suppression techniques that take into account manufacturing variations within the wafer have been researched and developed.
　しかし、複数の半導体チップを積層して実装する場合、それら半導体チップ間のばらつきも併せて考慮する必要がある。半導体チップ間ばらつきは、半導体チップ内ばらつきよりもばらつきの絶対量が大きいため、半導体チップを積層した半導体集積回路装置では、よりクロックスキューが大きくなる。そのため、半導体チップが積層された半導体集積回路装置においては、クロックスキューの抑制技術がより重要な課題となる。 However, when a plurality of semiconductor chips are stacked and mounted, it is necessary to consider variations between the semiconductor chips. Since the variation between semiconductor chips has a larger absolute amount than the variation within a semiconductor chip, a clock skew is further increased in a semiconductor integrated circuit device in which semiconductor chips are stacked. Therefore, in a semiconductor integrated circuit device in which semiconductor chips are stacked, a technique for suppressing clock skew becomes a more important issue.
　この種の半導体集積回路装置における半導体チップ間の温度ばらつきによるクロックスキュー抑制技術として、たとえば、特定層の半導体チップに半導体チップの水平方向のクロック信号分配を集約し、クロック信号分配回路の末端にてシリコン貫通ビアを介して上下の別層半導体チップへクロック信号を供給するものが提案されている(非特許文献１参照)。 As a technique for suppressing clock skew due to temperature variations between semiconductor chips in this type of semiconductor integrated circuit device, for example, the clock signal distribution in the horizontal direction of the semiconductor chip is concentrated on the semiconductor chip of a specific layer, and at the end of the clock signal distribution circuit. There has been proposed one that supplies a clock signal to upper and lower separate semiconductor chips via through silicon vias (see Non-Patent Document 1).
　この構成によれば、特定の半導体チップに水平方向のクロック信号分配回路が集約されるため、半導体チップ間ばらつきによるクロックスキューの問題を解決することが可能となる。 According to this configuration, the clock signal distribution circuit in the horizontal direction is concentrated on a specific semiconductor chip, so that it is possible to solve the problem of clock skew due to variations between semiconductor chips.
　また、ＦＰＧＡなどの再構成可能回路においては、半導体集積回路装置の設計時に各記憶素子の回路上での意味が不確定であるため、各記憶素子へ入力すべきクロック信号を決定することができない。 Further, in a reconfigurable circuit such as an FPGA, the meaning of each memory element on the circuit is uncertain when designing a semiconductor integrated circuit device, and therefore a clock signal to be input to each memory element cannot be determined. .
　そのため、再構成可能回路では、予め複数種のクロック信号を分配するための配線を用意しておき、各記憶素子はそれら分配される複数種のクロック信号の中からそれぞれが、適切なクロック信号を選択することが可能な構造が必要となる。 For this reason, in the reconfigurable circuit, wiring for distributing a plurality of types of clock signals is prepared in advance, and each storage element receives an appropriate clock signal from among the plurality of types of distributed clock signals. A structure that can be selected is required.
　図９は、ＦＰＧＡなどに例示される再構成可能回路におけるクロック供給回路の構成を示す図である。 FIG. 9 is a diagram illustrating a configuration of a clock supply circuit in a reconfigurable circuit exemplified by an FPGA or the like.
　図示するように、クロック信号の選択は階層的に複数回行われる。半導体集積回路装置１００の外部から入力された基準発振信号ＣＲＹに基づいて、クロック信号生成回路１０１により分周、位相調整などが施され複数種のクロック信号が生成される。 As shown in the figure, the clock signal is selected multiple times in a hierarchical manner. Based on the reference oscillation signal CRY input from the outside of the semiconductor integrated circuit device 100, the clock signal generation circuit 101 performs frequency division, phase adjustment, and the like to generate a plurality of types of clock signals.
　生成されたクロック信号は、複数段から構成されうるクロック信号選択回路１０２，１０３を経由し、最終的に末端のクロック信号に同期して動作する、フリップフロップなどの記憶素子１０４に供給される。 The generated clock signal is supplied to a storage element 104 such as a flip-flop, which finally operates in synchronization with a terminal clock signal, via clock signal selection circuits 102 and 103 that can be composed of a plurality of stages.
　クロック信号選択回路１０２，１０３は、半導体集積回路装置の製造後に入出力配線間の接続関係を再構成することが可能なプログラマブルスイッチから構成されている。クロック信号選択回路１０２，１０３には、制御回路１０５から出力された制御信号に基づいて、その接続関係情報が適切に設定されることで、各記憶素子に適切なクロック信号を供給する。 The clock signal selection circuits 102 and 103 are composed of programmable switches capable of reconfiguring the connection relationship between the input / output wirings after manufacturing the semiconductor integrated circuit device. Based on the control signal output from the control circuit 105, the connection relation information is appropriately set to the clock signal selection circuits 102 and 103, thereby supplying an appropriate clock signal to each storage element.
　クロック信号選択回路における入出力配線間の接続関係は、入力配線からすべての出力配線への接続経路が用意される場合と、入力配線から一部の出力配線への接続経路のみが用意される場合の２つの場合が考えられる。 The connection relationship between the input and output wirings in the clock signal selection circuit is when the connection path from the input wiring to all the output wirings is prepared or when only the connection path from the input wiring to some output wirings is prepared There are two possible cases.
　図１０は、クロック信号選択回路１０２，１０３におけるプログラマブルスイッチの接続構成を示す説明図である。 FIG. 10 is an explanatory diagram showing the connection configuration of the programmable switches in the clock signal selection circuits 102 and 103.
　クロック信号選択回路１０２，１０３における各点線は、それぞれの端子間にプログラマブルスイッチがあることを表している。図１０の場合、クロック信号選択回路１０２は、入力配線から一部の出力配線への接続経路のみが用意される例を示している。 Each dotted line in the clock signal selection circuits 102 and 103 indicates that there is a programmable switch between the respective terminals. In the case of FIG. 10, the clock signal selection circuit 102 shows an example in which only a connection path from the input wiring to a part of the output wiring is prepared.
　クロック信号生成回路１０１とクロック信号選択回路１０２とは、配線Ｈ１００～Ｈ１０３を介して接続されており、クロック信号選択回路１０２とクロック信号選択回路１０３とは、配線Ｈ１０４～Ｈ１０６を介して接続されている。クロック信号選択回路１０３と記憶素子１０４とは、配線Ｈ１０７を介して接続されている。 The clock signal generation circuit 101 and the clock signal selection circuit 102 are connected via wirings H100 to H103, and the clock signal selection circuit 102 and the clock signal selection circuit 103 are connected via wirings H104 to H106. Yes. The clock signal selection circuit 103 and the memory element 104 are connected via a wiring H107.
　配線Ｈ１００は、配線Ｈ１０４～Ｈ１０６のうち、配線Ｈ１０４，Ｈ１０５の２つの配線との間にプログラマブルスイッチを介した接続経路が用意されている。 In the wiring H100, a connection path via a programmable switch is prepared between two wirings H104 and H105 among the wirings H104 to H106.
　また、クロック信号選択回路１０３は、配線Ｈ１０４～Ｈ１０６から配線Ｈ１０７への接続経路が用意される場合である。これらプログラマブルスイッチのオン／オフ情報は、再構成可能回路の構成を設定する時にオン／オフ情報を保持する記憶素子に保持され、制御回路１０５がそれらオン／オフ情報に基づき各プログラマブルスイッチのオン／オフを制御する。 The clock signal selection circuit 103 is a case where a connection path from the wirings H104 to H106 to the wiring H107 is prepared. The on / off information of the programmable switch is held in a storage element that holds the on / off information when setting the configuration of the reconfigurable circuit, and the control circuit 105 determines the on / off of each programmable switch based on the on / off information. Control off.
　以上の説明の通り、再構成可能回路のクロック信号分配回路は、クロックスキューの抑制だけではなく、複数のクロック信号から適切なクロック信号を選択可能であることが、併せて重要である。 As described above, it is important that the clock signal distribution circuit of the reconfigurable circuit not only suppresses clock skew but also can select an appropriate clock signal from a plurality of clock signals.
　今後、半導体チップの積層化技術を再構成可能回路に適用する場合、その３次元積層再構成可能回路におけるクロック信号分配回路は上述の２点を考慮することが重要となる。 In the future, when the semiconductor chip stacking technology is applied to a reconfigurable circuit, it is important that the clock signal distribution circuit in the three-dimensional stacked reconfigurable circuit take the above two points into consideration.
　ところが、上記のような半導体集積回路装置におけるクロックスキュー抑制技術では、次のような問題点があることが本発明者により見い出された。 However, the present inventors have found that the clock skew suppression technology in the semiconductor integrated circuit device as described above has the following problems.
　非特許文献１の構成により、クロック信号分配回路の末端にてＴＳＶを介して、別層の半導体チップへクロック信号を供給する技術をＦＰＧＡなどの再構成可能回路に適用した場合、複数の問題が発生する。 When the technology of supplying a clock signal to a semiconductor chip of another layer via a TSV at the end of the clock signal distribution circuit is applied to a reconfigurable circuit such as an FPGA by the configuration of Non-Patent Document 1, there are a plurality of problems. appear.
　まず、第１の問題として、図１１に示すように、半導体チップ１１０にて分配したクロック信号をクロック分配回路の末端にて、ＴＳＶ１１３を介して別層の半導体チップ１１１，１１２に供給する場合、３つの層にそれぞれ存在する記憶素子１１４～１１６へ供給されるクロック信号が同じクロック信号に限定されるという問題点がある。そのため再構成可能回路のクロック信号分配回路において必要となる、各記憶素子へ給するクロック信号の選択性が失われる。 First, as a first problem, as shown in FIG. 11, when the clock signal distributed by the semiconductor chip 110 is supplied to the semiconductor chips 111 and 112 in different layers via the TSV 113 at the end of the clock distribution circuit, There is a problem that the clock signals supplied to the storage elements 114 to 116 existing in the three layers are limited to the same clock signal. Therefore, the selectivity of the clock signal supplied to each storage element, which is necessary in the clock signal distribution circuit of the reconfigurable circuit, is lost.
　第２の問題点として、図１１の構造によれば、ＴＳＶ１１３が正常に形成されず、たとえば、ＴＳＶ１１３がオープンとなった場合、または他の信号線とショートする場合に、そのＴＳＶが繋がるすべての記憶素子へ正常にクロック信号を分配することができないという問題がある。 As a second problem, according to the structure of FIG. 11, the TSV 113 is not formed normally. For example, when the TSV 113 is opened or short-circuited with another signal line, all the TSVs connected to the TSV 113 are connected. There is a problem that the clock signal cannot be normally distributed to the storage element.
　たとえば、図１１において、ＴＳＶ１１３が正常に形成されない場合、ＴＳＶ１１３に接続されるすべての記憶素子１１４～１１６にクロック信号を正常に供給することができないことになる。 For example, in FIG. 11, when the TSV 113 is not formed normally, the clock signal cannot be normally supplied to all the memory elements 114 to 116 connected to the TSV 113.
　第３の問題として、ホモチップ積層ＬＳＩにおいては、非特許文献１の構成のように、単一の半導体チップにクロック分配回路を集中させる場合、単一半導体チップあたりのクロック信号分配回路の面積が増大することがある。 As a third problem, in the homochip stacked LSI, when the clock distribution circuit is concentrated on a single semiconductor chip as in the configuration of Non-Patent Document 1, the area of the clock signal distribution circuit per single semiconductor chip increases. There are things to do.
　また、単一の半導体チップにクロック信号分配回路を集中させると、クロック信号分配のために生じる消費電力がある半導体チップに集中し、半導体チップ間で消費電力のばらつきが生じる。 Further, when the clock signal distribution circuit is concentrated on a single semiconductor chip, the power is generated due to the clock signal distribution, and the power consumption varies among the semiconductor chips.
　そのため、半導体チップ間でチップ温度にばらつきが生じる可能性があり、温度のばらつきによるクロックスキューが発生する可能性がある。 Therefore, there is a possibility that the chip temperature varies among the semiconductor chips, and there is a possibility that the clock skew is caused by the temperature variation.
　本発明の目的は、積層された複数の半導体チップに複数種のクロック信号を分配する際に、該クロック信号の選択性を低下させず、効率よくクロック信号を供給することのできる技術を提供することにある。 An object of the present invention is to provide a technique capable of supplying a clock signal efficiently without degrading the selectivity of the clock signal when distributing a plurality of types of clock signals to a plurality of stacked semiconductor chips. There is.
　本発明の前記ならびにそのほかの目的と新規な特徴については、本明細書の記述および添付図面から明らかになるであろう。 The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
　本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
　本発明は、積層された複数の半導体チップと、各々の半導体チップ間を貫通してそれぞれ接続する貫通配線とを有した半導体集積回路装置であって、複数の半導体チップは、周波数、および位相の異なる複数種類のクロック信号を生成するクロック信号生成回路と、制御信号に基づいて、入力されたクロック信号のうち、任意のクロック信号を選択して出力するクロック信号選択回路と、該クロック信号選択回路によって選択されたクロック信号が供給される論理ブロックとをそれぞれ備え、クロック信号選択回路は、制御信号に基づいて、クロック信号生成回路が生成した任意のクロック信号、および貫通配線を介して入力される他の半導体チップに設けられたクロック信号生成回路が生成したクロック信号から任意のクロック信号を選択し、論理ブロックに供給するように切り替えるものである。 The present invention is a semiconductor integrated circuit device having a plurality of stacked semiconductor chips and through-wirings that pass through and connect between the semiconductor chips, and the plurality of semiconductor chips have a frequency and a phase. A clock signal generation circuit that generates a plurality of different types of clock signals, a clock signal selection circuit that selects and outputs an arbitrary clock signal among input clock signals based on a control signal, and the clock signal selection circuit And a logic block to which the clock signal selected by each is supplied, and the clock signal selection circuit is input via an arbitrary clock signal generated by the clock signal generation circuit and a through wiring based on the control signal Arbitrary clock signals are selected from clock signals generated by clock signal generation circuits provided on other semiconductor chips. And it is intended to switch to supply to the logic block.
　また、本発明は、前記クロック信号選択回路が、クロック信号に同期して動作する論理ブロックのクロック入力端子の前段にそれぞれ備えられるものである。 Further, according to the present invention, the clock signal selection circuit is provided in the preceding stage of the clock input terminal of the logic block that operates in synchronization with the clock signal.
　さらに、本発明は、複数の前記半導体チップが、制御信号に基づいて、論理ブロックに供給されるクロック信号を任意の時間遅延させる遅延回路をそれぞれ備えたものである。 Further, according to the present invention, each of the plurality of semiconductor chips includes a delay circuit that delays a clock signal supplied to the logic block for an arbitrary time based on a control signal.
　また、本発明は、前記クロック信号選択回路が、制御信号にしたがって接続先を再構成可能なプログラマブルスイッチから構成されるものである。 Further, according to the present invention, the clock signal selection circuit includes a programmable switch whose connection destination can be reconfigured according to a control signal.
　さらに、本発明は、積層された複数の半導体チップと、各々の半導体チップ間を貫通してそれぞれ接続する貫通配線とを有した半導体集積回路装置であって、複数の半導体チップは、周波数、および位相の異なる複数種類のクロック信号を生成するクロック信号生成回路と、制御信号に基づいて、入力されたクロック信号のうち、任意のクロック信号を選択して出力する第１のクロック信号選択回路と、該第１のクロック信号選択回路の後段に設けられ、任意のクロック信号を選択して出力する第２のクロック信号選択回路と、該第２のクロック信号選択回路によって選択されたクロック信号が供給される論理ブロックとをそれぞれ備え、第１のクロック信号選択回路は、制御信号に基づいて、クロック信号生成回路が生成した任意のクロック信号、および貫通配線を介して入力される他の半導体チップに設けられたクロック信号生成回路が生成したクロック信号から任意のクロック信号を選択して出力し、第２のクロック信号選択回路は、制御信号に基づいて、第１のクロック信号選択回路から出力されたクロック信号、および貫通配線を介して入力される他の半導体チップに設けられた第１のクロック信号選択回路から出力されるクロック信号から任意のクロック信号を選択して論理ブロックに供給するように切り替えるものである。 Furthermore, the present invention is a semiconductor integrated circuit device having a plurality of stacked semiconductor chips and through wirings that penetrate and connect between the respective semiconductor chips, and the plurality of semiconductor chips have a frequency, and A clock signal generation circuit that generates a plurality of types of clock signals having different phases; a first clock signal selection circuit that selects and outputs an arbitrary clock signal among the input clock signals based on the control signal; A second clock signal selection circuit provided after the first clock signal selection circuit for selecting and outputting an arbitrary clock signal and a clock signal selected by the second clock signal selection circuit are supplied. And a first clock signal selection circuit that generates an arbitrary clock generated by the clock signal generation circuit based on the control signal. A clock signal and a clock signal generated by a clock signal generation circuit provided in another semiconductor chip that is input via a through wiring, and outputs an arbitrary clock signal. The second clock signal selection circuit Based on the control signal, the clock signal output from the first clock signal selection circuit and the clock signal output from the first clock signal selection circuit provided in another semiconductor chip input through the through wiring Is switched so that an arbitrary clock signal is selected and supplied to the logic block.
　また、本発明は、前記第２のクロック信号選択回路が、論理ブロックのクロック入力端子の前段に備えられるものである。 In the present invention, the second clock signal selection circuit is provided in a stage preceding the clock input terminal of the logic block.
　さらに、本発明は、複数の前記半導体チップが、制御信号に基づいて、論理ブロックに供給されるクロック信号を任意の時間遅延させる遅延回路をそれぞれ備えたものである。 Further, according to the present invention, each of the plurality of semiconductor chips includes a delay circuit that delays a clock signal supplied to the logic block for an arbitrary time based on a control signal.
　また、本発明は、前記第１、および前記第２のクロック信号選択回路が、制御信号にしたがって接続先を再構成可能なプログラマブルスイッチから構成されるものである。 Further, according to the present invention, the first and second clock signal selection circuits are composed of programmable switches whose connection destinations can be reconfigured according to a control signal.
　さらに、本願のその他の発明の概要を簡単に示す。 Furthermore, the outline of other inventions of the present application will be briefly described.
　本発明は、積層された複数の半導体チップに、貫通配線を介してクロック信号を分配する場合、各半導体チップに設けられた複数段存在しうるクロック信号選択回路のうち、少なくとも1つ以上のクロック信号選択回路を経由して別層の同期記憶素子（論理ブロック）にクロック信号を供給する構成とし、記憶素子にクロック信号の選択肢を供給することを可能とする。 When distributing clock signals to a plurality of stacked semiconductor chips via through wires, the present invention provides at least one clock among a plurality of clock signal selection circuits provided in each semiconductor chip. The clock signal is supplied to the synchronous memory element (logic block) in another layer via the signal selection circuit, and the clock signal options can be supplied to the memory element.
　また、貫通配線は、半導体チップに設けられたクロック信号分配回路の配線と物理的に直接接続することなく、製造後に接続情報を変更することが可能なプログラマブルスイッチを介して接続する構成とし、貫通配線が正常に形成されない場合、該当の貫通配線をクロック分配回路から分離することを可能とする。 In addition, the through wiring is configured to be connected through a programmable switch that can change connection information after manufacture without physically connecting directly to the clock signal distribution circuit wiring provided in the semiconductor chip. When the wiring is not formed normally, the corresponding through wiring can be separated from the clock distribution circuit.
　さらに、半導体チップには、クロック信号生成回路をそれぞれ有し、それらクロック信号生成回路がそれぞれ独立に分散してクロック信号を積層半導体チップ全体に分配する構成とし、各半導体チップあたりのクロック信号生成回路、およびクロック信号選択回路などからなるクロック信号分配回路の面積増大を抑え、また該クロック分配回路による消費電力の偏りを抑えることを可能とする。 Furthermore, each semiconductor chip has a clock signal generation circuit, and each clock signal generation circuit is configured to distribute each clock signal to the entire laminated semiconductor chip by independently distributing the clock signal generation circuits. In addition, it is possible to suppress an increase in the area of the clock signal distribution circuit including the clock signal selection circuit and the like, and to suppress a bias in power consumption by the clock distribution circuit.
　本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。 Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
　（１）クロック信号を分配供給する回路の面積を増大させることなく、積層された半導体チップに複数種類のクロック信号を分配することができる。 (1) A plurality of types of clock signals can be distributed to the stacked semiconductor chips without increasing the area of the circuit for distributing and supplying the clock signals.
　（２）また、クロック信号を供給する回路を各半導体チップに分散させて配置するので、１つの半導体チップに消費電力が集中することを防止でき、積層された半導体チップにクロック信号を安定して供給することができる。 (2) Since the circuit for supplying the clock signal is distributed and arranged in each semiconductor chip, power consumption can be prevented from being concentrated on one semiconductor chip, and the clock signal can be stably supplied to the stacked semiconductor chips. Can be supplied.
本発明の実施の形態１による半導体集積回路装置の一例を示す説明図である。1 is an explanatory diagram showing an example of a semiconductor integrated circuit device according to a first embodiment of the present invention. 図１の半導体集積回路装置に設けられたクロック信号選択回路における一部のプログラマブルスイッチの構成の一例を示す説明図である。FIG. 2 is an explanatory diagram illustrating an example of a configuration of a part of programmable switches in a clock signal selection circuit provided in the semiconductor integrated circuit device of FIG. 1. 図２のＡ－Ａ’断面を示す断面図である。FIG. 3 is a cross-sectional view showing a cross section A-A ′ of FIG. 2. 図１の半導体集積回路装置のより具体的な構成の一例を示す説明図である。FIG. 2 is an explanatory diagram illustrating an example of a more specific configuration of the semiconductor integrated circuit device of FIG. 1. 本発明の実施の形態２による半導体集積回路装置の一例を示す説明図である。It is explanatory drawing which shows an example of the semiconductor integrated circuit device by Embodiment 2 of this invention. 本発明の実施の形態３による半導体集積回路装置の一例を示す説明図である。It is explanatory drawing which shows an example of the semiconductor integrated circuit device by Embodiment 3 of this invention. 本発明の実施の形態４による半導体集積回路装置に設けられたクロック信号選択回路における一部のプログラマブルスイッチの構成の一例を示す説明図である。It is explanatory drawing which shows an example of a structure of the one part programmable switch in the clock signal selection circuit provided in the semiconductor integrated circuit device by Embodiment 4 of this invention. 本発明の実施の形態５による半導体集積回路装置の一例を示す説明図である。It is explanatory drawing which shows an example of the semiconductor integrated circuit device by Embodiment 5 of this invention. 本発明者が検討したＦＰＧＡなどに例示される再構成可能回路におけるクロック供給回路の構成を示す図である。It is a figure which shows the structure of the clock supply circuit in the reconfigurable circuit illustrated by FPGA etc. which this inventor examined. 図９のクロック信号選択回路におけるプログラマブルスイッチの接続構成を示す説明図である。It is explanatory drawing which shows the connection structure of the programmable switch in the clock signal selection circuit of FIG. 本発明者が検討したクロック信号選択回路、およびシリコン貫通ビアを用いて積層構造の半導体チップにクロック信号を供給する際の一例を示した説明図である。It is explanatory drawing which showed an example at the time of supplying a clock signal to the semiconductor chip of a laminated structure using the clock signal selection circuit which this inventor examined, and a through-silicon via.
　以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の部材には原則として同一の符号を付し、その繰り返しの説明は省略する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.
　（実施の形態１）
　図１は、本発明の実施の形態１による半導体集積回路装置の一例を示す説明図、図２は、図１の半導体集積回路装置に設けられたクロック信号選択回路における一部のプログラマブルスイッチの構成の一例を示す説明図、図３は、図２のＡ－Ａ’断面を示す断面図、図４は、図１の半導体集積回路装置のより具体的な構成の一例を示す説明図である。 (Embodiment 1)
1 is an explanatory diagram showing an example of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 2 is a configuration of a part of programmable switches in a clock signal selection circuit provided in the semiconductor integrated circuit device of FIG. FIG. 3 is a sectional view showing an AA ′ section of FIG. 2, and FIG. 4 is an explanatory view showing an example of a more specific configuration of the semiconductor integrated circuit device of FIG.
　本実施の形態１において、半導体集積回路装置１は、図１に示すように、半導体チップ２～４がそれぞれ積層された、いわゆるスタックド構造となっている。半導体集積回路装置１は、配線基板であるインタポーザ(図示せず)が設けられている。このインタポーザの裏面には、アレイ状に並べられた接続用電極(図示せず)が形成されている。 In the first embodiment, the semiconductor integrated circuit device 1 has a so-called stacked structure in which semiconductor chips 2 to 4 are stacked as shown in FIG. The semiconductor integrated circuit device 1 is provided with an interposer (not shown) which is a wiring board. On the back surface of the interposer, connection electrodes (not shown) arranged in an array are formed.
　また、インタポーザの主面には、半導体チップ２～４がそれぞれ積層されている。半導体チップ２は、クロック分配回路５、制御回路６、および論理ブロックとなるフリップフロップなどの論理回路７を備えた構成となっている。 Also, semiconductor chips 2 to 4 are stacked on the main surface of the interposer. The semiconductor chip 2 has a configuration including a clock distribution circuit 5, a control circuit 6, and a logic circuit 7 such as a flip-flop serving as a logic block.
　同様に、半導体チップ３は、クロック分配回路８、制御回路９、およびフリップフロップなどの論理ブロックとなる論理回路１０を備え、半導体チップ４は、クロック分配回路１１、制御回路１２、およびフリップフロップなどの論理ブロックとなる論理回路１３を備えた構成となっている。 Similarly, the semiconductor chip 3 includes a logic circuit 10 serving as a logic block such as a clock distribution circuit 8, a control circuit 9, and a flip-flop. The semiconductor chip 4 includes a clock distribution circuit 11, a control circuit 12, and a flip-flop. The configuration includes a logic circuit 13 serving as a logic block.
　また、クロック分配回路５は、クロック信号生成回路１４、クロック信号選択回路１５、およびクロック信号選択回路１６から構成されている。 The clock distribution circuit 5 includes a clock signal generation circuit 14, a clock signal selection circuit 15, and a clock signal selection circuit 16.
　クロック分配回路８は、クロック信号生成回路１７、クロック信号選択回路１８、ならびにクロック信号選択回路１９からなる。クロック分配回路１１は、クロック信号生成回路２０、クロック信号選択回路２１、およびクロック信号選択回路２２から構成されている。 The clock distribution circuit 8 includes a clock signal generation circuit 17, a clock signal selection circuit 18, and a clock signal selection circuit 19. The clock distribution circuit 11 includes a clock signal generation circuit 20, a clock signal selection circuit 21, and a clock signal selection circuit 22.
　また、最下層の半導体チップ２に設けられたクロック信号選択回路１６と該半導体チップ２の上部に積層される半導体チップ３に設けられたクロック信号選択回路１９とは、貫通配線となるシリコン貫通ビア２３，２４を介してそれぞれ接続されている。 The clock signal selection circuit 16 provided in the lowermost semiconductor chip 2 and the clock signal selection circuit 19 provided in the semiconductor chip 3 stacked on the semiconductor chip 2 are formed through silicon vias. 23 and 24, respectively.
　半導体チップ３に設けられたクロック信号選択回路１９と該半導体チップ３の上部に積層される最上層の半導体チップ４に設けられたクロック信号選択回路２２とは、貫通配線となるシリコン貫通ビア２５，２６を介してそれぞれ接続されている。 The clock signal selection circuit 19 provided in the semiconductor chip 3 and the clock signal selection circuit 22 provided in the uppermost semiconductor chip 4 stacked on the semiconductor chip 3 are formed by through silicon vias 25, 26, respectively.
　シリコン貫通ビア２３～２６は、半導体チップ２～４のシリコンに孔を開け、その孔に導体を充填することで、半導体チップ２の表面と半導体チップ３の裏面、および半導体チップ３の表面と半導体チップ４の裏面をそれぞれ電気的に接続する。 The through-silicon vias 23 to 26 are formed by forming holes in the silicon of the semiconductor chips 2 to 4 and filling the holes with conductors, thereby allowing the surface of the semiconductor chip 2 and the back surface of the semiconductor chip 3 and the surface of the semiconductor chip 3 and the semiconductor to be filled. The back surfaces of the chips 4 are electrically connected to each other.
　クロック信号生成回路１４，１７，２０は、外部から入力される基準発振信号ＣＲＹをもとに周波数や位相の異なる複数種のクロック信号を独立にそれぞれ生成し、それらのクロック信号を後段に接続されているクロック信号選択回路１５，１８，２１などにそれぞれ供給する。 The clock signal generation circuits 14, 17, and 20 independently generate a plurality of types of clock signals having different frequencies and phases based on a reference oscillation signal CRY inputted from the outside, and these clock signals are connected to the subsequent stage. Are supplied to the clock signal selection circuits 15, 18, 21 and the like.
　クロック信号選択回路１５，１６，１８，１９，２１，２２は、接続先を製造後に再構成することが可能な複数のプログラマブルスイッチから構成されており、これらプログラマブルスイッチを適切に設定することで、クロック信号を分配する。 The clock signal selection circuits 15, 16, 18, 19, 21, and 22 are composed of a plurality of programmable switches that can be reconfigured after manufacture, and by appropriately setting these programmable switches, Distribute the clock signal.
　ここで、図１では、簡単のため、１つの半導体チップについてクロック信号選択回路を２つ設けた構成としたが、クロック信号選択回路の個数は、これに限定するものではなく、３つ以上としてもよい。 Here, in FIG. 1, for the sake of simplicity, two clock signal selection circuits are provided for one semiconductor chip. However, the number of clock signal selection circuits is not limited to this, and the number is three or more. Also good.
　また、クロック信号選択回路の入力部と出力部のそれぞれの数は、入力部の数の方が出力信号線の本数よりも多い場合を図示しているが、本発明はこの構成に限定されるものではなく、入力部の数は出力部の数よりも少ない場合、あるいは等しい場合において本質的な違いはない。 The number of input units and output units of the clock signal selection circuit is shown when the number of input units is larger than the number of output signal lines, but the present invention is limited to this configuration. There is no essential difference when the number of input parts is less than or equal to the number of output parts.
　クロック信号選択回路１５，１８，２１は、たとえば、５つの入力部と、２つの出力部とをそれぞれ有しており、クロック信号生成回路１４，１７，２０が生成した５種類のクロック信号がそれぞれ入力されるように接続されている。 The clock signal selection circuits 15, 18, and 21 have, for example, five input units and two output units, respectively, and five types of clock signals generated by the clock signal generation circuits 14, 17, and 20 are respectively provided. Connected to input.
　クロック信号選択回路１５，１８，２１は、制御回路６，９，１２から出力される制御信号に基づいて、クロック信号生成回路１４，１７，２０が生成した５種類のクロック信号のうち、任意の２つのクロック信号を選択して２つの出力部にそれぞれ出力する。 The clock signal selection circuits 15, 18, and 21 are arbitrarily selected from the five types of clock signals generated by the clock signal generation circuits 14, 17, and 20 based on the control signals output from the control circuits 6, 9, and 12. Two clock signals are selected and output to the two output units, respectively.
　クロック信号選択回路１６，１９，２２は、端子Ｔ１～Ｔ７をそれぞれ備えた構成となっている。端子Ｔ１，Ｔ２には、クロック信号選択回路１５，１８，２１の２つの出力部がそれぞれ接続されており、端子Ｔ３には、論理回路７，１０，１３の入力部がそれぞれ接続されている。 The clock signal selection circuits 16, 19, and 22 are each provided with terminals T1 to T7. Two output portions of the clock signal selection circuits 15, 18, and 21 are connected to the terminals T1 and T2, respectively, and input portions of the logic circuits 7, 10, and 13 are connected to the terminal T3, respectively.
　また、クロック信号選択回路１６の端子Ｔ６，Ｔ７には、シリコン貫通ビア２３，２４の一方の接続部がそれぞれ接続されており、該クロック信号選択回路１９の端子Ｔ４，Ｔ５には、シリコン貫通ビア２３，２４の他方の接続部がそれぞれ接続されている。 Further, one connection portion of the through silicon vias 23 and 24 is connected to the terminals T6 and T7 of the clock signal selection circuit 16, and the through silicon via is connected to the terminals T4 and T5 of the clock signal selection circuit 19. The other connecting portions 23 and 24 are connected to each other.
　クロック信号選択回路１９の端子Ｔ６，Ｔ７には、シリコン貫通ビア２５，２６の一方の接続部がそれぞれ接続されており、該クロック信号選択回路２２の端子Ｔ４，Ｔ５には、シリコン貫通ビア２５，２６の他方の接続部がそれぞれ接続されている。 One connection portion of the through silicon vias 25 and 26 is connected to the terminals T6 and T7 of the clock signal selection circuit 19, respectively, and the through silicon via 25 and 25 are connected to the terminals T4 and T5 of the clock signal selection circuit 22, respectively. The other connection part of 26 is connected.
　クロック信号選択回路１６，１９，２２は、端子Ｔ１～Ｔ７のすべての端子間にそれぞれプログラマブルスイッチを配置した構成からなる。クロック信号選択回路１９において、図中に示す点線は、それぞれが各端子Ｔ１～Ｔ７間のプログラマブルスイッチの接続構成を表したものであり、たとえば、端子Ｔ３は、他の全ての端子Ｔ１，Ｔ２，Ｔ４～Ｔ７との間にプログラマブルスイッチが設けられた構成であることを示している。同様に、クロック信号選択回路１６，２２においても、端子Ｔ１～Ｔ７のすべての端子間にそれぞれプログラマブルスイッチが配置された構成からなる。 The clock signal selection circuits 16, 19, and 22 have a configuration in which programmable switches are arranged between all the terminals T1 to T7. In the clock signal selection circuit 19, the dotted lines shown in the figure each represent the connection configuration of the programmable switches between the terminals T1 to T7. For example, the terminal T3 includes all the other terminals T1, T2, and T2. This shows a configuration in which a programmable switch is provided between T4 and T7. Similarly, the clock signal selection circuits 16 and 22 have a configuration in which programmable switches are arranged between all the terminals T1 to T7.
　よって、論理回路７，１０，１３には、クロック信号選択回路１６，１９，２２における各プログラマブルスイッチを適切に設定することで、端子Ｔ１，Ｔ２，Ｔ４～Ｔ７から入力されるクロック信号のうち、任意のクロック信号を選択して供給することが可能となる。 Therefore, among the clock signals input from the terminals T1, T2, T4 to T7 by appropriately setting the programmable switches in the clock signal selection circuits 16, 19, and 22 in the logic circuits 7, 10, and 13, An arbitrary clock signal can be selected and supplied.
　これらクロック信号選択回路１６，１９，２２におけるプログラマブルスイッチのオン／オフ情報（制御信号）は、たとえば、メモリやレジスタなどに予め格納されおり、制御回路６，９，１２は、格納されたオン／オフ情報（制御信号）に基づいて、プログラマブルスイッチのオン／オフ状態をそれぞれ制御する。 The on / off information (control signal) of the programmable switches in the clock signal selection circuits 16, 19, and 22 is stored in advance in, for example, a memory or a register, and the control circuits 6, 9, and 12 are stored in the on / off information stored therein. The on / off state of the programmable switch is controlled based on the off information (control signal).
　図２は、半導体チップ３のクロック信号選択回路１９と該半導体チップ３の上方に積層された半導体チップ４のクロック信号選択回路２２とにおける一部のプログラマブルスイッチの構成の一例を示す説明図である。 FIG. 2 is an explanatory diagram showing an example of the configuration of some programmable switches in the clock signal selection circuit 19 of the semiconductor chip 3 and the clock signal selection circuit 22 of the semiconductor chip 4 stacked above the semiconductor chip 3. .
　この図２では、簡単化のため、クロック信号選択回路１９における端子Ｔ１～Ｔ５に接続されているプログラマブルスイッチＳＷ１～ＳＷ６、およびクロック信号選択回路２２における端子Ｔ１～Ｔ５に接続されているプログラマブルスイッチＳＷ７～ＳＷ１２のみを示している。 In FIG. 2, programmable switches SW1 to SW6 connected to terminals T1 to T5 in the clock signal selection circuit 19 and programmable switches SW7 connected to terminals T1 to T5 in the clock signal selection circuit 22 for simplification. Only SW12 is shown.
　クロック信号選択回路１９において、プログラマブルスイッチＳＷ１の一方の接続部には、端子Ｔ５が接続されており、該プログラマブルスイッチＳＷ１の他方の接続部には、端子Ｔ４が接続されている。プログラマブルスイッチＳＷ４は、一方の接続部が第１、および第２の接続部からなる２つの接続部から構成されており、第１の接続部には、端子Ｔ１が接続され、第２の接続部には、端子Ｔ２が接続されている。このプログラマブルスイッチＳＷ４の他方の接続部には、端子Ｔ５が接続されている。 In the clock signal selection circuit 19, a terminal T5 is connected to one connection portion of the programmable switch SW1, and a terminal T4 is connected to the other connection portion of the programmable switch SW1. In the programmable switch SW4, one connection part is composed of two connection parts including a first connection part and a second connection part, and the terminal T1 is connected to the first connection part, and the second connection part. Is connected to a terminal T2. A terminal T5 is connected to the other connection portion of the programmable switch SW4.
　プログラマブルスイッチＳＷ２も同様に、一方の接続部が第１、および第２の接続部の２つの接続部から構成されている。プログラマブルスイッチＳＷ１の第１の接続部には、端子Ｔ１が接続され、第２の接続部には、端子Ｔ２が接続されており、該プログラマブルスイッチＳＷ１の他方の接続部には、端子Ｔ４が接続されている。 Similarly, in the programmable switch SW2, one connection portion is composed of two connection portions, a first connection portion and a second connection portion. A terminal T1 is connected to the first connection portion of the programmable switch SW1, a terminal T2 is connected to the second connection portion, and a terminal T4 is connected to the other connection portion of the programmable switch SW1. Has been.
　プログラマブルスイッチＳＷ３の一方の接続部には、端子Ｔ４が接続されており、該プログラマブルスイッチＳＷ３の他方の接続部には、端子Ｔ３が接続されている。また、プログラマブルスイッチＳＷ６の一方の接続部には、端子Ｔ５が接続されており、該プログラマブルスイッチＳＷ６の他方の接続部には、端子Ｔ３が接続されている。 The terminal T4 is connected to one connection part of the programmable switch SW3, and the terminal T3 is connected to the other connection part of the programmable switch SW3. A terminal T5 is connected to one connection portion of the programmable switch SW6, and a terminal T3 is connected to the other connection portion of the programmable switch SW6.
　プログラマブルスイッチＳＷ５は、一方の接続部が第１、および第２の接続部の２つの接続部から構成されている。このプログラマブルスイッチＳＷ５の第１の接続部には、端子Ｔ１が接続され、第２の接続部には、端子Ｔ２が接続されており、該プログラマブルスイッチＳＷ５の他方の接続部には、端子Ｔ３が接続されている。 As for programmable switch SW5, one connection part is comprised from two connection parts of the 1st and 2nd connection part. A terminal T1 is connected to the first connection portion of the programmable switch SW5, a terminal T2 is connected to the second connection portion, and a terminal T3 is connected to the other connection portion of the programmable switch SW5. It is connected.
　なお、クロック信号選択回路２２においても、同じマスクから製造されているために、クロック信号選択回路１９と同様の接続構成となっている。 Note that the clock signal selection circuit 22 is manufactured from the same mask, and thus has the same connection configuration as the clock signal selection circuit 19.
　図３は、図２のＡ－Ａ’断面を示す断面図である。この図３においては、クロック信号選択回路１９に設けられたプログラマブルスイッチＳＷ１、およびクロック信号選択回路２２に設けられたプログラマブルスイッチＳＷ７に着目した図であり、プログラマブルスイッチＳＷ１，ＳＷ７に接続される配線以外は省略している。 FIG. 3 is a cross-sectional view showing the A-A ′ cross section of FIG. FIG. 3 is a diagram focusing on the programmable switch SW1 provided in the clock signal selection circuit 19 and the programmable switch SW7 provided in the clock signal selection circuit 22, except for the wiring connected to the programmable switches SW1 and SW7. Is omitted.
　この場合、図示するように、プログラマブルスイッチＳＷ１（ＳＷ２～ＳＷ６），ＳＷ７（～ＳＷ１２）は、ＭＯＳ(Metal Oxide Semiconductor)トランジスタにより形成されている。 In this case, as shown in the figure, the programmable switches SW1 (SW2 to SW6) and SW7 (to SW12) are formed by MOS (Metal Oxide Semiconductor) transistors.
　プログラマブルスイッチＳＷ１を構成するトランジスタの一方の接続部には、端子Ｔ４が接続されており、該トランジスタの他方の接続部には、端子Ｔ５が接続されている。端子Ｔ５は、たとえば、バンプなどの電極Ｄを介してシリコン貫通ビア２５の一方の接続部に接続されている。 The terminal T4 is connected to one connection part of the transistor constituting the programmable switch SW1, and the terminal T5 is connected to the other connection part of the transistor. The terminal T5 is connected to one connection portion of the through silicon via 25 via an electrode D such as a bump, for example.
　シリコン貫通ビア２５の他方の接続部は、クロック信号選択回路２２の端子Ｔ４に接続されており、該端子Ｔ４は、プログラマブルスイッチＳＷ７を構成するトランジスタの一方の接続部が接続されている。プログラマブルスイッチＳＷ７を構成するトランジスタの他方の接続部には、端子Ｔ５が接続されている。 The other connection portion of the through silicon via 25 is connected to the terminal T4 of the clock signal selection circuit 22, and one connection portion of the transistor constituting the programmable switch SW7 is connected to the terminal T4. A terminal T5 is connected to the other connection portion of the transistor constituting the programmable switch SW7.
　図３では、プログラマブルスイッチをＭＯＳトランジスタにより形成している例を示したが、該プログラマブルスイッチは、ＭＯＳトランジスタに限定されることはない。 FIG. 3 shows an example in which the programmable switch is formed by a MOS transistor, but the programmable switch is not limited to a MOS transistor.
　たとえば、ヒューズなどに代表されるような非線形であり、かつヒステリシスな特性を持つ２端子以上の素子によるスイッチなどで構成することが可能である。 For example, it can be configured by a switch or the like with an element having two or more terminals, which is nonlinear as represented by a fuse and has a hysteresis characteristic.
　図３に示すとおり、シリコン貫通ビア２３，２５は、一続きの導体として形成せず、プログラマブルスイッチＳＷ１，ＳＷ７をそれぞれ介して接続される構成となる（シリコン貫通ビア２４，２６においても、同様に一続きの導体として形成せず、プログラマブルスイッチをそれぞれ介して接続される）。 As shown in FIG. 3, the through silicon vias 23 and 25 are not formed as a continuous conductor, but are connected via the programmable switches SW1 and SW7, respectively (the same applies to the through silicon vias 24 and 26). They are not formed as a series of conductors, but are connected via programmable switches).
　これにより、あるシリコン貫通ビアが、オープンとなったり、他の配線とショートした場合であっても、すべての論理回路に正常にクロック信号を分配することができないという問題を解決することが可能となる。 This makes it possible to solve the problem that a clock signal cannot be normally distributed to all logic circuits even when a through silicon via is open or short-circuited with another wiring. Become.
　たとえば、図２において、シリコン貫通ビア２３が正常に形成されていない場合、該シリコン貫通ビア２３に接続されるすべてのプログラマブルスイッチをオフにすることで、クロック分配回路８から、シリコン貫通ビア２３を分離することが可能となる。 For example, in FIG. 2, when the through silicon via 23 is not normally formed, all the programmable switches connected to the through silicon via 23 are turned off, so that the through silicon via 23 is connected from the clock distribution circuit 8. It becomes possible to separate.
　図４は、より具体的な半導体集積回路装置１の構成の一例を示す説明図である。 FIG. 4 is an explanatory diagram showing an example of a more specific configuration of the semiconductor integrated circuit device 1.
　半導体集積回路装置１は、図示するように、半導体チップ２～４を備え、半導体チップ２は、クロック分配回路５、制御回路６、および論理回路７，７ａ，７ｂを有している。　　　 As shown in the figure, the semiconductor integrated circuit device 1 includes semiconductor chips 2 to 4. The semiconductor chip 2 includes a clock distribution circuit 5, a control circuit 6, and logic circuits 7, 7a, 7b. *
　同様に、半導体チップ３は、クロック分配回路８、制御回路９、および論理回路１０，１０ａ，１０ｂを備え、半導体チップ４は、クロック分配回路１１、制御回路１２、および論理回路１３，１３ａ，１３ｂを備えた構成となっている。 Similarly, the semiconductor chip 3 includes a clock distribution circuit 8, a control circuit 9, and logic circuits 10, 10a, and 10b. The semiconductor chip 4 includes a clock distribution circuit 11, a control circuit 12, and logic circuits 13, 13a, and 13b. It is the composition provided with.
　また、クロック分配回路５は、クロック信号生成回路１４、およびクロック信号選択回路１５，１６からなり、クロック分配回路８は、クロック信号生成回路１７、ならびにクロック信号選択回路１８，１９からなり、クロック分配回路１１は、クロック信号生成回路２０、およびクロック信号選択回路２１，２２から構成されている。 The clock distribution circuit 5 includes a clock signal generation circuit 14 and clock signal selection circuits 15 and 16, and the clock distribution circuit 8 includes a clock signal generation circuit 17 and clock signal selection circuits 18 and 19. The circuit 11 includes a clock signal generation circuit 20 and clock signal selection circuits 21 and 22.
　また、図４に示す半導体集積回路装置１は、３種類のクロック信号ＣＫ１～ＣＫ３を論理回路７，７ａ，７ｂ，１０，１０ａ，１０ｂ，１３，１３ａ，１３ｂに入力する場合の例を示している。 The semiconductor integrated circuit device 1 shown in FIG. 4 shows an example in which three types of clock signals CK1 to CK3 are input to the logic circuits 7, 7a, 7b, 10, 10a, 10b, 13, 13a, 13b. Yes.
　さらに、クロック信号生成回路１４，１７，２０は、外部から入力される基準発振信号ＣＲＹをもとに周波数や位相の異なる６種のクロック信号を独立にそれぞれ生成し、それらのクロック信号を後段に接続されているクロック信号選択回路１５，１８，２１などにそれぞれ供給する。 Further, the clock signal generation circuits 14, 17, and 20 independently generate six types of clock signals having different frequencies and phases based on the reference oscillation signal CRY inputted from the outside, and these clock signals are provided in the subsequent stages. The clock signals are supplied to the connected clock signal selection circuits 15, 18, 21 and the like.
　クロック信号選択回路１５，１８，２１は、制御回路６，９，１２の制御信号に基づいて、クロック信号生成回路１４，１７，２０がそれぞれ生成した６種のクロック信号から任意の４種類のクロック信号を選択して出力する。 The clock signal selection circuits 15, 18, 21 are based on the control signals from the control circuits 6, 9, 12, and any four types of clocks from the six types of clock signals generated by the clock signal generation circuits 14, 17, 20 respectively. Select and output the signal.
　クロック信号選択回路１６，１９，２２は、図１のクロック信号選択回路１６，１９，２２に、端子Ｔ８～Ｔ１５が新たに設けられた構成となっており、半導体チップ２～４には、シリコン貫通ビア２３ａ，２４ａ，２５ａ，２６ａが新たに追加された構成となっている。 The clock signal selection circuits 16, 19, and 22 have a configuration in which terminals T8 to T15 are newly provided in the clock signal selection circuits 16, 19, and 22 of FIG. The through vias 23a, 24a, 25a, and 26a are newly added.
　クロック信号選択回路１９において、端子Ｔ８，Ｔ９は、クロック信号選択回路１８の出力部に接続されている。端子Ｔ１０は、シリコン貫通ビア２３ａの一方の接続部に接続されており、端子Ｔ１１は、シリコン貫通ビア２４ａの一方の接続部に接続されている。　　　 In the clock signal selection circuit 19, the terminals T8 and T9 are connected to the output section of the clock signal selection circuit 18. The terminal T10 is connected to one connecting portion of the through silicon via 23a, and the terminal T11 is connected to one connecting portion of the through silicon via 24a. *
　また、クロック信号選択回路１９の端子Ｔ１２は、シリコン貫通ビア２５ａの一方の接続部に接続されており、端子Ｔ１３は、シリコン貫通ビア２６ａの一方の接続部に接続されている。クロック信号選択回路１９の端子Ｔ１４，Ｔ１５は、論理回路１０ａ，１０ｂの入力部にそれぞれ接続されている。 The terminal T12 of the clock signal selection circuit 19 is connected to one connection part of the through silicon via 25a, and the terminal T13 is connected to one connection part of the through silicon via 26a. The terminals T14 and T15 of the clock signal selection circuit 19 are connected to the input parts of the logic circuits 10a and 10b, respectively.
　クロック信号選択回路１６の端子Ｔ８，Ｔ９は、クロック信号選択回路１５の出力部に接続されており、端子Ｔ１２，Ｔ１３は、シリコン貫通ビア２３ａ，２４ａの他方の接続部にそれぞれ接続されている。クロック信号選択回路１６の端子Ｔ１４，Ｔ１５は、論理回路７ａ，７ｂの入力部にそれぞれ接続されている。 The terminals T8 and T9 of the clock signal selection circuit 16 are connected to the output part of the clock signal selection circuit 15, and the terminals T12 and T13 are connected to the other connection part of the through silicon vias 23a and 24a, respectively. The terminals T14 and T15 of the clock signal selection circuit 16 are connected to the input parts of the logic circuits 7a and 7b, respectively.
　クロック信号選択回路２２の端子Ｔ８，Ｔ９は、クロック信号選択回路２１の出力部に接続されており、端子Ｔ１０，Ｔ１１は、シリコン貫通ビア２５ａ，２６ａの他方の接続部にそれぞれ接続されている。クロック信号選択回路２２の端子Ｔ１４，Ｔ１５は、論理回路１３ａ，１３ｂの入力部にそれぞれ接続されている。なお、その他の接続構成については、図１と同様となっているので、説明は省略する。 The terminals T8 and T9 of the clock signal selection circuit 22 are connected to the output part of the clock signal selection circuit 21, and the terminals T10 and T11 are connected to the other connection part of the through silicon vias 25a and 26a, respectively. The terminals T14 and T15 of the clock signal selection circuit 22 are connected to the input parts of the logic circuits 13a and 13b, respectively. The other connection configurations are the same as those shown in FIG.
　この図４では、クロック信号生成回路１４が生成したクロック信号ＣＫ１を論理回路７，１０，１３にそれぞれ供給し、クロック信号生成回路１７が生成したクロック信号ＣＫ２を論理回路７ａ，１０ａ，１３ａにそれぞれ供給し、クロック信号生成回路２０が生成したクロック信号ＣＫ３を論理回路７ｂ，１０ｂ，１３ｂにそれぞれ供給する場合について示しており、実線で示す経路がクロック信号ＣＫ１～ＣＫ３の供給経路となる。 In FIG. 4, the clock signal CK1 generated by the clock signal generation circuit 14 is supplied to the logic circuits 7, 10, and 13, respectively, and the clock signal CK2 generated by the clock signal generation circuit 17 is supplied to the logic circuits 7a, 10a, and 13a, respectively. In this example, the clock signal CK3 generated by the clock signal generation circuit 20 is supplied to the logic circuits 7b, 10b, and 13b, and the paths shown by the solid lines are the supply paths of the clock signals CK1 to CK3.
　図４において、クロック信号ＣＫ３は、シリコン貫通ビア２６ａを介して論理回路７ｂ，１０ｂにそれぞれ供給されているが、たとえば、シリコン貫通ビア２６ａが正常に形成されていない場合には、該シリコン貫通ビア２６ａに接続されるすべてのプログラマブルスイッチをオフにし、利用されていない他の正常に形成されているシリコン貫通ビアを用いてクロック信号を供給するようにする。 In FIG. 4, the clock signal CK3 is supplied to the logic circuits 7b and 10b via the through-silicon via 26a. For example, when the through-silicon via 26a is not normally formed, the through-silicon via All programmable switches connected to 26a are turned off and clock signals are supplied using other normally formed through-silicon vias that are not utilized.
　この場合、シリコン貫通ビア２５ａを用いて一点鎖線で示す経路が形成されるように、プログラマブルスイッチを動作させ、論理回路７ｂ，１０ｂにそれぞれクロック信号ＣＫ３を供給する。 In this case, the programmable switch is operated so that the path indicated by the alternate long and short dash line is formed using the through silicon via 25a, and the clock signal CK3 is supplied to the logic circuits 7b and 10b, respectively.
　このように、プログラマブルスイッチを介して各論理回路にクロック信号を供給することにより、あるシリコン貫通ビアが正常に形成されていない場合でも、適切なクロック信号を供給することができる。 Thus, by supplying a clock signal to each logic circuit via the programmable switch, an appropriate clock signal can be supplied even if a certain through silicon via is not formed normally.
　また、各半導体チップ２～４にクロック分配回路５，８，１１がそれぞれ備えられているので、１つの半導体チップにクロック分配回路を設ける場合と比べて半導体チップ２～４のレイアウト面積を小さくすることができる。 Further, since the semiconductor chip 2 to 4 are provided with the clock distribution circuits 5, 8, and 11, respectively, the layout area of the semiconductor chips 2 to 4 is reduced as compared with the case where the clock distribution circuit is provided in one semiconductor chip. be able to.
　また、クロック分配回路を半導体チップ２～４にそれぞれ設けることにより、各半導体チップ２～４の消費電力のばらつきを抑えることができ、それにより、半導体チップ間の温度ばらつきを低減させることが可能となり、温度ばらつきに起因するクロックスキューを抑制することができる。 In addition, by providing the clock distribution circuit in each of the semiconductor chips 2 to 4, it is possible to suppress variations in power consumption of each of the semiconductor chips 2 to 4, thereby reducing temperature variations between the semiconductor chips. In addition, clock skew caused by temperature variation can be suppressed.
　さらに、論理回路７，７ａ，７ｂ，１０，１０ａ，１０ｂ，１３，１３ａ，１３ｂの前段に設けられたクロック信号選択回路１６，１９，２２により、クロック信号を他の半導体チップに供給するので、半導体チップの製造ばらつきなどによるクロックスキューの影響を受けにくくすることができる。 Further, the clock signal is supplied to other semiconductor chips by the clock signal selection circuits 16, 19, and 22 provided in the preceding stage of the logic circuits 7, 7a, 7b, 10, 10a, 10b, 13, 13a, and 13b. It is possible to reduce the influence of clock skew due to manufacturing variations of semiconductor chips.
　(実施の形態２)
　図５は、本発明の実施の形態２による半導体集積回路装置の一例を示す説明図である。 (Embodiment 2)
FIG. 5 is an explanatory diagram showing an example of a semiconductor integrated circuit device according to the second embodiment of the present invention.
　本実施の形態２において、半導体集積回路装置１は、図５に示すように、半導体チップ２～４がそれぞれ積層された、前記実施の形態１の図４と同様のスタックド構造となっている。 In the second embodiment, the semiconductor integrated circuit device 1 has a stacked structure similar to that of FIG. 4 of the first embodiment, in which the semiconductor chips 2 to 4 are laminated, as shown in FIG.
　また、半導体チップ２～４には、図４と同様に、クロック分配回路５，８，１１、制御回路６，９，１２、およびフリップフロップなどの論理回路７，７ａ，７ｂ，１０，１０ａ，１０ｂ，１３，１３ａ，１３ｂがそれぞれ備えられている。 Similarly to FIG. 4, the semiconductor chips 2 to 4 include clock distribution circuits 5, 8, 11, control circuits 6, 9, 12, and logic circuits 7, 7 a, 7 b, 10, 10 a, and flip-flops. 10b, 13, 13a, and 13b are provided.
　クロック分配回路５は、図４と同様に、クロック信号生成回路１４、およびクロック信号選択回路１５，１６から構成されている。クロック分配回路８は、クロック信号生成回路１７、ならびにクロック信号選択回路１８，１９からなり、クロック分配回路１１は、クロック信号生成回路２０、およびクロック信号選択回路２１，２２から構成されている。 The clock distribution circuit 5 includes a clock signal generation circuit 14 and clock signal selection circuits 15 and 16 as in FIG. The clock distribution circuit 8 includes a clock signal generation circuit 17 and clock signal selection circuits 18 and 19, and the clock distribution circuit 11 includes a clock signal generation circuit 20 and clock signal selection circuits 21 and 22.
　図５に示す半導体集積回路装置１が図４と異なる点は、最下層の半導体チップ２に設けられたクロック信号選択回路１５と該半導体チップ２の上部に積層される半導体チップ３に設けられたクロック信号選択回路１８とが、シリコン貫通ビア２７を介して接続され、半導体チップ３に設けられたクロック信号選択回路１８と該半導体チップ３の上方に積層される半導体チップ４に設けられたクロック信号選択回路２１とが、シリコン貫通ビア２８を介して接続されているところである。 The semiconductor integrated circuit device 1 shown in FIG. 5 is different from FIG. 4 in that it is provided in the clock signal selection circuit 15 provided in the lowermost semiconductor chip 2 and the semiconductor chip 3 stacked on the semiconductor chip 2. The clock signal selection circuit 18 is connected through the through silicon via 27, and the clock signal selection circuit 18 provided in the semiconductor chip 3 and the clock signal provided in the semiconductor chip 4 stacked above the semiconductor chip 3 are connected. The selection circuit 21 is connected through a through silicon via 28.
　さらに、半導体チップ２のクロック信号選択回路１６と半導体チップ３のクロック信号選択回路１９とが、シリコン貫通ビア２３を介して接続され、クロック信号選択回路１９と半導体チップ４のクロック信号選択回路２２とが、シリコン貫通ビア２５を介して接続されている点も異なるところである。 Further, the clock signal selection circuit 16 of the semiconductor chip 2 and the clock signal selection circuit 19 of the semiconductor chip 3 are connected via the through silicon via 23, and the clock signal selection circuit 19 and the clock signal selection circuit 22 of the semiconductor chip 4 are connected. However, the connection is made through the through-silicon via 25.
　クロック信号選択回路１５，１８，２１は、端子Ｔ１４～Ｔ２１をそれぞれ備えた構成となっており、クロック信号選択回路１６，１９，２２は、端子Ｔ２２～Ｔ２８をそれぞれ備えた構成となっている。 The clock signal selection circuits 15, 18, and 21 are configured to include terminals T14 to T21, respectively, and the clock signal selection circuits 16, 19, and 22 are configured to include terminals T22 to T28, respectively.
　クロック信号選択回路１５，１８，２１において、端子Ｔ１４～Ｔ１７には、クロック信号生成回路１４，１７，２０が生成した４種類のクロック信号がそれぞれ入力されるように接続されている。 In the clock signal selection circuits 15, 18, and 21, the terminals T14 to T17 are connected to the four types of clock signals generated by the clock signal generation circuits 14, 17, and 20, respectively.
　また、端子Ｔ１８は、クロック信号選択回路１６，１９，２２の端子Ｔ２３にそれぞれ接続されており、端子Ｔ１９は、クロック信号選択回路１６，１９，２２の端子Ｔ２２にそれぞれ接続されている。 Further, the terminal T18 is connected to the terminal T23 of the clock signal selection circuits 16, 19, and 22, respectively, and the terminal T19 is connected to the terminal T22 of the clock signal selection circuits 16, 19, and 22, respectively.
　クロック信号選択回路１５の端子Ｔ２１には、シリコン貫通ビア２７の一方の接続部が接続されており、該シリコン貫通ビア２７の他方の接続部には、クロック信号選択回路１８の端子Ｔ２０が接続されている。 One connection portion of the through silicon via 27 is connected to the terminal T21 of the clock signal selection circuit 15, and the terminal T20 of the clock signal selection circuit 18 is connected to the other connection portion of the through silicon via 27. ing.
　クロック信号選択回路１８の端子Ｔ２１には、シリコン貫通ビア２８の一方の接続部が接続されており、該シリコン貫通ビア２８の他方の接続部には、クロック信号選択回路２１の端子Ｔ２０が接続されている。 One connection portion of the through silicon via 28 is connected to the terminal T21 of the clock signal selection circuit 18, and the terminal T20 of the clock signal selection circuit 21 is connected to the other connection portion of the through silicon via 28. ing.
　クロック信号選択回路１６，１９，２２の端子Ｔ２４～Ｔ２６には、論理回路７，７ａ，７ｂ、論理回路１０，１０ａ，１０ｂ、論理回路１３，１３ａ，１３ｂの入力部がそれぞれ接続されている。 The input portions of the logic circuits 7, 7a, 7b, the logic circuits 10, 10a, 10b, and the logic circuits 13, 13a, 13b are connected to the terminals T24 to T26 of the clock signal selection circuits 16, 19, 22, respectively.
　クロック信号選択回路１６の端子Ｔ２８には、シリコン貫通ビア２３の一方の接続部が接続されており、該シリコン貫通ビア２８の他方の接続部には、クロック信号選択回路１９の端子Ｔ２７が接続されている。 One connection portion of the through silicon via 23 is connected to the terminal T28 of the clock signal selection circuit 16, and the terminal T27 of the clock signal selection circuit 19 is connected to the other connection portion of the through silicon via 28. ing.
　クロック信号選択回路１９の端子Ｔ２８には、シリコン貫通ビア２５の一方の接続部が接続されており、該シリコン貫通ビア２５の他方の接続部には、クロック信号選択回路２２の端子Ｔ２７が接続されている。 One connection portion of the through silicon via 25 is connected to the terminal T28 of the clock signal selection circuit 19, and the terminal T27 of the clock signal selection circuit 22 is connected to the other connection portion of the through silicon via 25. ing.
　クロック信号選択回路１５，１８，２１は、端子Ｔ１４～Ｔ２１のすべての端子間にそれぞれプログラマブルスイッチを配置した構成からなり、クロック信号選択回路１６，１９，２２は、端子Ｔ２２～Ｔ２８のすべての端子間にそれぞれプログラマブルスイッチを配置した構成からなる。 The clock signal selection circuits 15, 18, and 21 have a configuration in which programmable switches are arranged between all the terminals T14 to T21. The clock signal selection circuits 16, 19, and 22 have all the terminals T22 to T28. Each of them has a configuration in which programmable switches are arranged therebetween.
　この構成とすることにより、クロック分配回路５，８，１１のより末端に近い階層で、シリコン貫通ビアを介して他の半導体チップにクロック信号を分配することができるので、他の半導体チップでの水平方向の分配距離を短くすることが可能となり、よりクロックスキューを抑えることができる。 With this configuration, the clock signal can be distributed to other semiconductor chips via through silicon vias at a level closer to the end of the clock distribution circuits 5, 8, and 11, so that The horizontal distribution distance can be shortened, and the clock skew can be further suppressed.
　この図５では、一例として、クロック信号生成回路１４が生成したクロック信号ＣＫ４を半導体チップ４の論理回路１３ａに供給し、クロック信号生成回路１７が生成したクロック信号ＣＫ５を半導体チップ４の論理回路１３ｂに供給している場合を示しており、それぞれのプログラマブルスイッチの接続経路は、クロック信号選択回路１５，１６，１８，１９，２１，２２に実線で示している。 In FIG. 5, as an example, the clock signal CK4 generated by the clock signal generation circuit 14 is supplied to the logic circuit 13a of the semiconductor chip 4, and the clock signal CK5 generated by the clock signal generation circuit 17 is supplied to the logic circuit 13b of the semiconductor chip 4. The connection paths of the respective programmable switches are indicated by solid lines in the clock signal selection circuits 15, 16, 18, 19, 21, and 22.
　このように、クロック信号選択回路１５とクロック信号選択回路１８とを接続するシリコン貫通ビア２７、およびクロック信号選択回路１８とクロック信号選択回路２１とを接続するシリコン貫通ビア２８をそれぞれ設けることにより、たとえば、半導体チップ２，３で生成したクロック信号ＣＫ４，ＣＫ５を半導体チップ４の論理回路１３，１３ａ，１３ｂにそれぞれ供給することが可能となる。 よって、クロック信号を分配する自由度を高くすることができる。 Thus, by providing the through silicon via 27 that connects the clock signal selection circuit 15 and the clock signal selection circuit 18 and the through silicon via 28 that connects the clock signal selection circuit 18 and the clock signal selection circuit 21, respectively. For example, the clock signals CK4 and CK5 generated by the semiconductor chips 2 and 3 can be supplied to the logic circuits 13, 13a and 13b of the semiconductor chip 4, respectively. Therefore, the degree of freedom for distributing the clock signal can be increased.
　ここで、クロック信号ＣＫ４，ＣＫ５のどちらが、クロック分配回路５，８のより末端のクロック信号選択回路で他の半導体チップへ供給されるかは、該クロック信号ＣＫ４，ＣＫ５に同期して動作する回路が許容するクロックスキューの大きさにより決定される。 Here, which of the clock signals CK4 and CK5 is supplied to another semiconductor chip by the clock signal selection circuit at the end of the clock distribution circuits 5 and 8 is a circuit that operates in synchronization with the clock signals CK4 and CK5. Is determined by the size of the clock skew allowed.
　よりクロックスキューを小さく抑えることが必要な回路ほど、より高い優先度で末端(論理回路に近い側)のクロック選択回路のシリコン貫通ビアを介して、他の半導体チップへクロック信号を分配する。 The circuit that needs to keep the clock skew smaller, distributes the clock signal to other semiconductor chips through the through silicon vias of the clock selection circuit at the end (closer to the logic circuit) with higher priority.
　図５の例では、クロック信号ＣＫ５がクロック信号ＣＫ４よりもクロックスキュー制約が厳しいという想定のもと、クロック信号ＣＫ５の分配の為に、可能な限りクロック分配回路末端側となるシリコン貫通ビア２５を使用している。 In the example of FIG. 5, on the assumption that the clock signal CK5 is more severely constrained by the clock skew than the clock signal CK4, the through-silicon via 25 which is as far as possible to the end of the clock distribution circuit is provided for the distribution of the clock signal CK5. I use it.
　また、図５では、クロック信号選択回路１６とクロック信号選択回路１９、およびクロック信号選択回路１６とクロック信号選択回路２２にそれぞれ１本のシリコン貫通ビア（１９，２２）が接続された構成としたが、これらシリコン貫通ビアの本数は制限されるものではなく、複数本であってもよい。 In FIG. 5, one through-silicon via (19, 22) is connected to the clock signal selection circuit 16, the clock signal selection circuit 19, and the clock signal selection circuit 16 and the clock signal selection circuit 22, respectively. However, the number of these through silicon vias is not limited and may be plural.
　同様に、クロック信号選択回路１５，１８，２１におけるプログラマブルスイッチの数も、すべての端子に接続されるように設けるのではなく、任意の端子に接続されるプログラマブルスイッチの数を減らす構成としてもよい。 Similarly, the number of programmable switches in the clock signal selection circuits 15, 18, and 21 is not provided so as to be connected to all terminals, but may be configured to reduce the number of programmable switches connected to arbitrary terminals. .
　(実施の形態３)
　図６は、本発明の実施の形態３による半導体集積回路装置の一例を示す説明図である。 (Embodiment 3)
FIG. 6 is an explanatory diagram showing an example of a semiconductor integrated circuit device according to the third embodiment of the present invention.
　本実施の形態２において、半導体集積回路装置１は、図６に示すように、半導体チップ２，３がそれぞれ積層されたスタックド構造となっており、半導体チップ２は、クロック分配回路５、制御回路６、およびフリップフロップなどの論理回路７からなる図１と同様の構成に、新たに可変遅延素子回路２９が設けられており、半導体チップ３は、クロック分配回路８、制御回路９、ならびにフリップフロップなどの論理回路１０からなる図１と同様の構成に、新たに可変遅延素子回路２９ａが設けられた構成からなる。 In the second embodiment, as shown in FIG. 6, the semiconductor integrated circuit device 1 has a stacked structure in which semiconductor chips 2 and 3 are stacked. The semiconductor chip 2 includes a clock distribution circuit 5 and a control circuit. 6 and a logic circuit 7 such as a flip-flop, a variable delay element circuit 29 is newly provided in the same configuration as in FIG. 1, and the semiconductor chip 3 includes a clock distribution circuit 8, a control circuit 9, and a flip-flop. In this configuration, a variable delay element circuit 29a is newly provided in the same configuration as that of FIG.
　クロック分配回路５は、図１と同様に、クロック信号生成回路１４、およびクロック信号選択回路１５，１６から構成されており、クロック分配回路８は、クロック信号生成回路１７、ならびにクロック信号選択回路１８，１９から構成されている。 As in FIG. 1, the clock distribution circuit 5 includes a clock signal generation circuit 14 and clock signal selection circuits 15 and 16. The clock distribution circuit 8 includes a clock signal generation circuit 17 and a clock signal selection circuit 18. , 19.
　クロック信号選択回路１６，１９は、端子Ｔ２９～Ｔ３７をそれぞれ備えた構成となっている。クロック信号選択回路１６，１９において、端子Ｔ２９，Ｔ３０は、クロック信号選択回路１５，１８から出力される２種類のクロック信号が入力されるように接続されている。 The clock signal selection circuits 16 and 19 have terminals T29 to T37, respectively. In the clock signal selection circuits 16 and 19, the terminals T29 and T30 are connected so that two types of clock signals output from the clock signal selection circuits 15 and 18 are input.
　クロック信号選択回路１６の端子Ｔ３５～Ｔ３７には、シリコン貫通ビア２３，２４，２４ａの一方の接続部がそれぞれ接続されており、該シリコン貫通ビア２３，２４，２４ａの他方の接続部には、クロック信号選択回路１９の端子Ｔ３２～Ｔ３４がそれぞれ接続されている。 One connection portion of the through silicon vias 23, 24, and 24a is connected to the terminals T35 to T37 of the clock signal selection circuit 16, respectively, and the other connection portion of the through silicon vias 23, 24, and 24a is connected to the terminals T35 to T37. The terminals T32 to T34 of the clock signal selection circuit 19 are connected to each other.
　また、クロック信号選択回路１６の端子Ｔ３１には、可変遅延素子回路２９の入力部が接続されており、クロック信号選択回路１９の端子Ｔ３１には、可変遅延素子回路２９ａの入力部が接続されている。 Further, the input portion of the variable delay element circuit 29 is connected to the terminal T31 of the clock signal selection circuit 16, and the input portion of the variable delay element circuit 29a is connected to the terminal T31 of the clock signal selection circuit 19. Yes.
　可変遅延素子回路２９の出力部には、論理回路７の入力部に接続されており、可変遅延素子回路２９ａの出力部には、論理回路１０の入力部に接続されている。可変遅延素子回路２９は、制御回路６から出力される制御信号に基づいて、クロック信号選択回路１６から出力されたクロック信号を任意の時間遅延して出力する。可変遅延素子回路２９ａは、制御回路９から出力される制御信号に基づいて、クロック信号選択回路１９から出力されたクロック信号を任意の時間遅延して出力する。 The output section of the variable delay element circuit 29 is connected to the input section of the logic circuit 7, and the output section of the variable delay element circuit 29a is connected to the input section of the logic circuit 10. Based on the control signal output from the control circuit 6, the variable delay element circuit 29 delays the clock signal output from the clock signal selection circuit 16 by an arbitrary time and outputs it. The variable delay element circuit 29a delays the clock signal output from the clock signal selection circuit 19 by an arbitrary time based on the control signal output from the control circuit 9, and outputs the delayed signal.
　この場合、半導体チップ２のクロック信号生成回路１４が生成したクロック信号を、論理回路７，１０のそれぞれに供給する際、クロック信号生成回路１４から論理回路７までの供給経路の距離とクロック信号生成回路１４から論理回路１０までの供給経路の距離とにシリコン貫通ビア２３，２４，２４ａの分のずれが生じてしまい、クロック信号がシリコン貫通ビアを伝播する時間によるクロックスキューが生じてしまう。 In this case, when the clock signal generated by the clock signal generation circuit 14 of the semiconductor chip 2 is supplied to each of the logic circuits 7 and 10, the distance of the supply path from the clock signal generation circuit 14 to the logic circuit 7 and the clock signal generation Deviations of the through silicon vias 23, 24, and 24a occur in the distance of the supply path from the circuit 14 to the logic circuit 10, and a clock skew occurs due to the time that the clock signal propagates through the through silicon via.
　このスキューは、半導体チップ間ばらつきによるクロックスキューより小さいものの、非常にクロックスキューに対する要求が厳しい高周波数で動作する同期回路などでは、問題となりうる。 Although this skew is smaller than the clock skew due to variations between semiconductor chips, it can be a problem in a synchronous circuit operating at a high frequency where the demand for the clock skew is very strict.
　よって、シリコン貫通ビアを介したクロック信号の伝播によるクロックスキュー調整を目的とし、可変遅延素子回路２９，２９ａを設けた構成としている。クロック信号生成回路１４から論理回路７までの供給経路の距離が、クロック信号生成回路１４から論理回路１０までの供給経路の距離よりも大きい場合、可変遅延素子回路２９の遅延時間を調整し、論理回路７，１０へのクロック信号の到達時間が略同じとなるようにする。 Therefore, the variable delay element circuits 29 and 29a are provided for the purpose of adjusting the clock skew by the propagation of the clock signal through the through silicon via. When the distance of the supply path from the clock signal generation circuit 14 to the logic circuit 7 is larger than the distance of the supply path from the clock signal generation circuit 14 to the logic circuit 10, the delay time of the variable delay element circuit 29 is adjusted, and the logic The arrival times of the clock signals to the circuits 7 and 10 are made substantially the same.
　これにより、論理回路７と論理回路１０との間のクロックスキューを大幅に抑えることが可能となる。可変遅延素子回路２９，２９ａの遅延量は、各クロック信号の分配経路決定時にそれぞれの経路がわかるため、その情報をもとに決定することが可能である。 Thereby, the clock skew between the logic circuit 7 and the logic circuit 10 can be greatly suppressed. The delay amounts of the variable delay element circuits 29 and 29a can be determined based on the information because the respective paths are known when the distribution paths of the respective clock signals are determined.
　決定された遅延量に基づき、必要となる制御信号を生成する情報を記憶素子などに保持し、クロック信号選択回路のプログラマブルスイッチのオン／オフ情報の制御と同様、制御回路６，９が再構成可能回路の構成時に遅延量を制御する。 Based on the determined delay amount, information for generating a necessary control signal is held in a storage element or the like, and the control circuits 6 and 9 are reconfigured similarly to the control of the on / off information of the programmable switch of the clock signal selection circuit. Control the amount of delay when configuring possible circuits.
　可変遅延素子を利用すれば、半導体チップ間ばらつきによるクロックスキューも原理的には抑制可能である。しかし、可変遅延素子によるクロックスキュー抑制は一般的に補償する遅延時間の大きさに応じて必要な回路規模が増大する。 If a variable delay element is used, clock skew due to variations between semiconductor chips can be suppressed in principle. However, clock skew suppression by a variable delay element generally increases the required circuit scale according to the amount of delay time to be compensated.
　半導体チップ間ばらつきによるクロックスキューはスキューが大きいため、可変遅延素子を利用して半導体チップ間ばらつきによるクロックスキューを抑制しようとすると、回路面積の増大を招く。 Since the clock skew due to variations between semiconductor chips has a large skew, an attempt to suppress the clock skew due to variations between semiconductor chips using a variable delay element causes an increase in circuit area.
　また、半導体チップ間ばらつきは製造後にテストをしなければ、該当論理回路経路間にどの程度のクロックスキューが生じるかの検討がつかず、それぞれの可変遅延素子の遅延量を調整する作業に多大なコストがかかる。 In addition, if the variation between semiconductor chips is not tested after manufacturing, it is impossible to examine how much clock skew is generated between the corresponding logic circuit paths, and it is very difficult to adjust the delay amount of each variable delay element. costly.
　テスト回路を半導体集積回路装置内部に組み込み、テスト結果から自動的に遅延量を調整する構成においても、テスト回路、およびその制御回路によるオーバーヘッドが生じる。 Even in the configuration in which the test circuit is incorporated in the semiconductor integrated circuit device and the delay amount is automatically adjusted based on the test result, overhead is caused by the test circuit and its control circuit.
　しかし、図６の構成では、可変遅延素子回路２９，２９ａは、シリコン貫通ビアによる分配距離の差を補償するための構造であるため、事前に利用製造プロセスにおけるシリコン貫通ビアの特性を評価しておけば、可変遅延量の制御は配置配線処理の段階で自動的に行うことが容易である。また、予想されるクロックスキューは，半導体チップ間ばらつきによるクロックスキューよりも小さいため、可変遅延素子回路２９，２９ａに要する回路面積は小さく抑えることが可能となる。 However, in the configuration of FIG. 6, the variable delay element circuits 29 and 29a have a structure for compensating for the difference in distribution distance due to the through silicon vias. Therefore, the characteristics of the through silicon vias in the use manufacturing process are evaluated in advance. In this case, the variable delay amount can be easily controlled automatically at the stage of the placement and routing process. Further, since the expected clock skew is smaller than the clock skew due to the variation between the semiconductor chips, the circuit area required for the variable delay element circuits 29 and 29a can be kept small.
　(実施の形態４)
　図７は、本発明の実施の形態４による半導体集積回路装置に設けられたクロック信号選択回路における一部のプログラマブルスイッチの構成の一例を示す説明図である。 (Embodiment 4)
FIG. 7 is an explanatory diagram showing an example of the configuration of some programmable switches in the clock signal selection circuit provided in the semiconductor integrated circuit device according to the fourth embodiment of the present invention.
　本実施の形態４において、半導体集積回路装置１は、前記実施の形態１の図１と同様に、半導体チップ２～４がそれぞれ積層されたスタックド構造からなる。また、半導体チップ２～４の構成においても、前記実施の形態１の図１と同様となっているが、クロック信号選択回路１６，１９，２２におけるプログラマブルスイッチの接続構成が異なっている。 In the fourth embodiment, the semiconductor integrated circuit device 1 has a stacked structure in which the semiconductor chips 2 to 4 are stacked, as in FIG. 1 of the first embodiment. The configuration of the semiconductor chips 2 to 4 is the same as that of FIG. 1 of the first embodiment, but the connection configuration of the programmable switches in the clock signal selection circuits 16, 19, and 22 is different.
　図７は、半導体チップ３のクロック信号選択回路１９と該半導体チップ３の上方に積層された半導体チップ４のクロック信号選択回路２２とにおける一部のプログラマブルスイッチの構成の一例を示す説明図である。 FIG. 7 is an explanatory diagram showing an example of the configuration of part of the programmable switches in the clock signal selection circuit 19 of the semiconductor chip 3 and the clock signal selection circuit 22 of the semiconductor chip 4 stacked above the semiconductor chip 3. .
　また、クロック信号選択回路１９，２２は、図１と同様に、端子Ｔ１～Ｔ７を有しており、図７では、クロック信号選択回路１９における端子Ｔ１～Ｔ５に接続されているプログラマブルスイッチＳＷ１３～ＳＷ１５、およびクロック信号選択回路２２における端子Ｔ１～Ｔ５に接続されているプログラマブルスイッチＳＷ１６～ＳＷ１８をそれぞれ示している。 Similarly to FIG. 1, the clock signal selection circuits 19 and 22 have terminals T1 to T7. In FIG. 7, the programmable switches SW13 to SW5 connected to the terminals T1 to T5 in the clock signal selection circuit 19 are provided. SW15 and programmable switches SW16 to SW18 connected to terminals T1 to T5 in the clock signal selection circuit 22 are shown.
　クロック信号選択回路１９において、プログラマブルスイッチＳＷ１３の一方の接続部には、端子Ｔ５が接続されており、該プログラマブルスイッチＳＷ１３の他方の接続部には、端子Ｔ４が接続されている。 In the clock signal selection circuit 19, a terminal T5 is connected to one connection portion of the programmable switch SW13, and a terminal T4 is connected to the other connection portion of the programmable switch SW13.
　プログラマブルスイッチＳＷ１４は、一方の接続部が第１、および第２の接続部からなる２つの接続部から構成されており、第１の接続部には、端子Ｔ１が接続され、第２の接続部には、端子Ｔ２が接続されている。このプログラマブルスイッチＳＷ１４の他方の接続部には、端子Ｔ４が接続されている。 In the programmable switch SW14, one connection portion is composed of two connection portions including a first connection portion and a second connection portion, and the terminal T1 is connected to the first connection portion, and the second connection portion. Is connected to a terminal T2. A terminal T4 is connected to the other connection portion of the programmable switch SW14.
　プログラマブルスイッチＳＷ１５の一方の接続部には、端子Ｔ４が接続されており、該プログラマブルスイッチＳＷ１５の他方の接続部には、端子Ｔ３が接続されている。クロック信号選択回路２１のプログラマブルスイッチＳＷ１６～ＳＷ１８においても同様の接続構成となっている。 The terminal T4 is connected to one connection portion of the programmable switch SW15, and the terminal T3 is connected to the other connection portion of the programmable switch SW15. The programmable switches SW16 to SW18 of the clock signal selection circuit 21 have the same connection configuration.
　前記実施の形態１の図１に示したように、すべての端子Ｔ１～Ｔ７にプログラマブルスイッチを備えた構成では、論理回路に供給するクロック信号の選択肢を多くすることができる反面、プログラマブルスイッチの数が多くなるため、面積の増大、遅延時間の増大などの問題が生じる可能性がある。 As shown in FIG. 1 of the first embodiment, in the configuration in which all the terminals T1 to T7 are provided with programmable switches, the number of clock signals supplied to the logic circuit can be increased, but the number of programmable switches Therefore, problems such as an increase in area and an increase in delay time may occur.
　しかし、図７に示すように、全ての端子Ｔ１～Ｔ７にプログラマブルスイッチを設けずに、たとえば、端子Ｔ５に接続されるプログラマブルスイッチの数を減らすことで、クロック信号分配回路の負荷容量を削減することが可能となる。そのため、クロック信号分配回路の遅延時間、面積、消費電力などをより改善することができる。 However, as shown in FIG. 7, the load capacity of the clock signal distribution circuit is reduced by reducing the number of programmable switches connected to the terminal T5, for example, without providing programmable switches for all the terminals T1 to T7. It becomes possible. Therefore, the delay time, area, power consumption, etc. of the clock signal distribution circuit can be further improved.
　(実施の形態５)
　図８は、本発明の実施の形態５による半導体集積回路装置の一例を示す説明図である。 (Embodiment 5)
FIG. 8 is an explanatory diagram showing an example of a semiconductor integrated circuit device according to the fifth embodiment of the present invention.
　本実施の形態５において、半導体集積回路装置１は、図８に示すように、半導体チップ２～４がそれぞれ積層されたスタックド構造からなる。半導体チップ２には、クロック分配回路５、周辺回路３０、および再構成可能回路３１が設けられている。 In the fifth embodiment, the semiconductor integrated circuit device 1 has a stacked structure in which semiconductor chips 2 to 4 are stacked as shown in FIG. The semiconductor chip 2 is provided with a clock distribution circuit 5, a peripheral circuit 30, and a reconfigurable circuit 31.
　また、半導体チップ３には、クロック分配回路８、周辺回路３２、およびＦＰＧＡなどの再構成可能回路３３が設けられており、半導体チップ４には、クロック分配回路１１、周辺回路３４、およびＦＰＧＡなどの再構成可能回路３５が設けられている。 The semiconductor chip 3 is provided with a reconfigurable circuit 33 such as a clock distribution circuit 8, a peripheral circuit 32, and an FPGA. The semiconductor chip 4 includes a clock distribution circuit 11, a peripheral circuit 34, and an FPGA. A reconfigurable circuit 35 is provided.
　周辺回路３０，３２，３４は、たとえば、中央演算処理回路（CPU）やメモリ回路などの周辺回路からなり、再構成可能回路３１，３３，３５は、たとえば、ＦＰＧＡなどからなる。 The peripheral circuits 30, 32, and 34 are, for example, peripheral circuits such as a central processing circuit (CPU) and a memory circuit, and the reconfigurable circuits 31, 33, and 35 are, for example, an FPGA.
　また、クロック分配回路５は、図１と同様に、クロック信号生成回路１４、および図１に示すクロック信号選択回路１５，１６から構成されている。また、クロック分配回路８は、クロック信号生成回路１７、ならびに図１に示すクロック信号選択回路１８，１９からなり、クロック分配回路１１は、クロック信号生成回路２０、および図１に示すクロック信号選択回路２１，２２からなる。 Similarly to FIG. 1, the clock distribution circuit 5 includes a clock signal generation circuit 14 and clock signal selection circuits 15 and 16 shown in FIG. The clock distribution circuit 8 includes a clock signal generation circuit 17 and clock signal selection circuits 18 and 19 shown in FIG. 1. The clock distribution circuit 11 includes a clock signal generation circuit 20 and a clock signal selection circuit shown in FIG. 21 and 22.
　クロック信号生成回路１４，１７，２０には、外部入力される基準発振信号ＣＲＹがシリコン貫通ビア３６，３７を介して入力されるようにそれぞれ接続されている。クロック信号生成回路１４，１７，２０は、基準発振信号ＣＲＹから、周波数や位相の異なる複数種のクロック信号を生成する。 The clock signal generation circuits 14, 17, and 20 are connected so that the reference oscillation signal CRY input from the outside is input through the through silicon vias 36 and 37, respectively. The clock signal generation circuits 14, 17, and 20 generate a plurality of types of clock signals having different frequencies and phases from the reference oscillation signal CRY.
　再構成可能回路３１には、回路ブロック３１ａ～３１ｄが設けられており、再構成可能回路３３には、回路ブロック３３ａ～３３ｄが、また、再構成可能回路３５には、回路ブロック３５ａ～３５ｄがそれぞれ設けられている。 The reconfigurable circuit 31 includes circuit blocks 31a to 31d, the reconfigurable circuit 33 includes circuit blocks 33a to 33d, and the reconfigurable circuit 35 includes circuit blocks 35a to 35d. Each is provided.
　再構成可能回路３１と再構成可能回路３３とは、シリコン貫通ビア２３，２４を介して接続されており、再構成可能回路３３と再構成可能回路３５とは、シリコン貫通ビア２５，２６を介して接続されている。 The reconfigurable circuit 31 and the reconfigurable circuit 33 are connected via through silicon vias 23 and 24, and the reconfigurable circuit 33 and the reconfigurable circuit 35 are connected through silicon through vias 25 and 26. Connected.
　再構成可能回路３１，３３，３５には、前記実施の形態１に示した技術によって、クロック信号がそれぞれ供給されている。具体的なクロック信号の供給技術にいては、実施の形態１と同様であるので、ここでは説明を省略する。 Reconfigurable circuits 31, 33, and 35 are each supplied with a clock signal by the technique shown in the first embodiment. The specific clock signal supply technique is the same as that of the first embodiment, and thus the description thereof is omitted here.
　図８に示した半導体集積回路装置１の場合、回路ブロック３１ｂ，３１ｄ，３３ａ，３５ｄには、半導体チップ２のクロック分配回路５が生成したクロック信号が分配され、回路ブロック３１ｃ，３３ｃ，３３ｄ，３５ａには、半導体チップ３のクロック分配回路８が生成したクロック信号が分配され、回路ブロック３１ａ，３３ｂ，３５ｂ，３５ｄには、半導体チップ４のクロック分配回路１１が生成したそれぞれ同期のとれたクロック信号が分配されている。 In the case of the semiconductor integrated circuit device 1 shown in FIG. 8, the clock signal generated by the clock distribution circuit 5 of the semiconductor chip 2 is distributed to the circuit blocks 31b, 31d, 33a, and 35d, and the circuit blocks 31c, 33c, 33d, The clock signal generated by the clock distribution circuit 8 of the semiconductor chip 3 is distributed to 35a, and the synchronized clock generated by the clock distribution circuit 11 of the semiconductor chip 4 is distributed to the circuit blocks 31a, 33b, 35b, and 35d. The signal is distributed.
　回路ブロック３１ｂ，３３ｃ，３５ｂは、それぞれ再構成可能回路３１，３３，３５と周辺回路３０，３２，３４との間のインターフェース部に形成される回路である。回路ブロック３１ｂには、図１に示すクロック信号選択回路１５，１６が設けられており、回路ブロック３３ｃ，３５ｂは、クロック信号選択回路１８，１９（図１）、およびクロック信号選択回路２１，２２（図１）がそれぞれ設けられている。 The circuit blocks 31b, 33c, and 35b are circuits formed at the interface between the reconfigurable circuits 31, 33, and 35 and the peripheral circuits 30, 32, and 34, respectively. The circuit block 31b is provided with the clock signal selection circuits 15 and 16 shown in FIG. 1, and the circuit blocks 33c and 35b are the clock signal selection circuits 18 and 19 (FIG. 1) and the clock signal selection circuits 21 and 22, respectively. (FIG. 1) is provided.
　また、周辺回路３０、および回路ブロック３１ｂ，３１ｄ，３３ａ，３５ｃには、半導体チップ２のクロック信号生成回路１４が生成したクロック信号ＣＫ１がそれぞれ入力され、周辺回路３２、ならびに回路ブロック３１ｃ，３３ｃ，３３ｄ，３５ａには、半導体チップ３のクロック信号生成回路１７が生成したクロック信号ＣＫ２がそれぞれ入力されている。 Further, the peripheral circuit 30 and the circuit blocks 31b, 31d, 33a, and 35c are respectively input with the clock signal CK1 generated by the clock signal generation circuit 14 of the semiconductor chip 2, and the peripheral circuit 32 and the circuit blocks 31c, 33c, The clock signal CK2 generated by the clock signal generation circuit 17 of the semiconductor chip 3 is input to 33d and 35a, respectively.
　さらに、周辺回路３４、および回路ブロック３１ａ，３３ｂ，３５ｂ，３５ｄには、半導体チップ４のクロック信号生成回路２０が生成したクロック信号ＣＫ３がそれぞれ入力されている。 Furthermore, the clock signal CK3 generated by the clock signal generation circuit 20 of the semiconductor chip 4 is input to the peripheral circuit 34 and the circuit blocks 31a, 33b, 35b, and 35d, respectively.
　なお、図８に示したハッチング、縦線、および横線は、供給されるクロック信号を示したものであり、図８において、ハッチングされたブロックには、クロック信号ＣＫ１が、縦線が記入されているブロックには、クロック信号ＣＫ２が、横線が記入されたブロックには、クロック信号ＣＫ３がそれぞれ供給されるブロックであることをそれぞれ示している。 The hatching, vertical line, and horizontal line shown in FIG. 8 indicate clock signals to be supplied. In FIG. 8, the clock signal CK1 is indicated by a vertical line in the hatched block. In the block, the clock signal CK2 is supplied, and in the block with the horizontal line, the clock signal CK3 is supplied.
　本構成によれば、周辺回路３０、および回路ブロック３１ｂ，３１ｄは、クロック信号生成回路１４が生成した同期のとれたクロック信号ＣＫ１が入力されるため、半導体チップ間ばらつきの影響を受けずに同期動作を行うことが可能である。 According to this configuration, since the synchronized clock signal CK1 generated by the clock signal generation circuit 14 is input to the peripheral circuit 30 and the circuit blocks 31b and 31d, they are synchronized without being affected by variations between semiconductor chips. It is possible to perform an operation.
　周辺回路３２と回路ブロック３３ｃ，３３ｄ、ならびに周辺回路３４と回路ブロック３５ｂ，３５ｄにおいても、クロック信号生成回路１７，２０が生成した同期のとれたクロック信号ＣＫ２，ＣＫ３がそれぞれ入力されるため、半導体チップ間ばらつきの影響を受けずに同期動作を行うことが可能である。 In the peripheral circuit 32 and the circuit blocks 33c and 33d, and in the peripheral circuit 34 and the circuit blocks 35b and 35d, the synchronized clock signals CK2 and CK3 generated by the clock signal generation circuits 17 and 20 are input, respectively. Synchronous operation can be performed without being affected by variations between chips.
　また、回路ブロック３１ｂ，３１ｄ，３３ａ，３５ｃは、前記実施の形態１で説明した技術により、同期のとれたクロック信号ＣＫ１を供給することができるので、これら回路ブロックが同期動作を行うことができる。 Further, since the circuit blocks 31b, 31d, 33a, and 35c can supply the synchronized clock signal CK1 by the technique described in the first embodiment, the circuit blocks can perform the synchronous operation. .
　同様に、回路ブロック３１ｃ，３３ｃ，３３ｄ，３５ａ、および回路ブロック３１ａ，３３ｂ，３５ｂ，３５ｄにおいても、前記実施の形態１で説明した技術により、同期のとれたクロック信号ＣＫ２，ＣＫ２をそれぞれ供給することができ、これら回路ブロックがそれぞれ同期動作を行うことができる。 Similarly, the circuit blocks 31c, 33c, 33d, and 35a and the circuit blocks 31a, 33b, 35b, and 35d also supply synchronized clock signals CK2 and CK2, respectively, by the technique described in the first embodiment. Each of these circuit blocks can perform a synchronous operation.
　故に、周辺回路３０は、再構成可能回路３１におけるインターフェース回路である回路ブロック３１ｂを介して、別半導体チップ３の回路ブロック３３ａ，３５ｃとの間で同期動作を行うことが可能となる。 Therefore, the peripheral circuit 30 can perform a synchronous operation with the circuit blocks 33a and 35c of the other semiconductor chip 3 via the circuit block 31b which is an interface circuit in the reconfigurable circuit 31.
　同様にして、周辺回路３２は、インターフェース回路である回路ブロック３３ｃを介して、半導体チップ２の回路ブロック３１ｃ、および半導体チップ４の回路ブロック３５ａと、また、周辺回路３４は、インターフェース回路である回路ブロック３５ｂを介して、半導体チップ３の回路ブロック３３ｂ、および半導体チップ２の回路ブロック３１ａとの間でそれぞれ同期動作を行うことができる。 Similarly, the peripheral circuit 32 is connected to the circuit block 31c of the semiconductor chip 2 and the circuit block 35a of the semiconductor chip 4 via the circuit block 33c that is an interface circuit, and the peripheral circuit 34 is a circuit that is an interface circuit. Synchronous operations can be performed between the circuit block 33b of the semiconductor chip 3 and the circuit block 31a of the semiconductor chip 2 via the block 35b.
　このように、本実施の形態５に示した半導体集積回路装置１によれば、周辺回路３０，３２，３４と再構成可能回路３１，３３，３５との間で同期動作を行うことが可能となる。 As described above, according to the semiconductor integrated circuit device 1 shown in the fifth embodiment, it is possible to perform a synchronous operation between the peripheral circuits 30, 32, and 34 and the reconfigurable circuits 31, 33, and 35. Become.
　以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
　本発明は、複数の半導体チップを積層した構成の半導体集積回路装置におけるクロック供給技術に適している。 The present invention is suitable for a clock supply technique in a semiconductor integrated circuit device having a configuration in which a plurality of semiconductor chips are stacked.
１　半導体集積回路装置
２～４　半導体チップ
５　クロック分配回路
６　制御回路
７　論理回路
７ａ，７ｂ　論理回路
８　クロック分配回路
９　制御回路
１０　論理回路
１０ａ，１０ｂ　論理回路
１１　クロック分配回路
１２　制御回路
１３　論理回路
１３ａ，１３ｂ　論理回路
１４　クロック信号生成回路
１５　クロック信号選択回路
１６　クロック信号選択回路
１７　クロック信号生成回路
１８　クロック信号選択回路
１９　クロック信号選択回路
２０　クロック信号生成回路
２１　クロック信号選択回路
２２　クロック信号選択回路
２３　シリコン貫通ビア
２３ａ　シリコン貫通ビア
２４　シリコン貫通ビア
２４ａ　シリコン貫通ビア
２５　シリコン貫通ビア
２５ａ　シリコン貫通ビア
２６　シリコン貫通ビア
２６ａ　シリコン貫通ビア
２７　シリコン貫通ビア
２８　シリコン貫通ビア
２９　可変遅延素子回路
２９ａ　可変遅延素子回路
３０　周辺回路
３１　再構成可能回路
３１ａ　回路ブロック
３１ｂ　回路ブロック
３１ｃ　回路ブロック
３１ｄ　回路ブロック
３２　周辺回路
３３　再構成可能回路
３３ａ　回路ブロック
３３ｂ　回路ブロック
３３ｃ　回路ブロック
３３ｄ　回路ブロック
３４　周辺回路
３５　再構成可能回路
３５ａ　回路ブロック
３５ｂ　回路ブロック
３５ｃ　回路ブロック
３５ｄ　回路ブロック
３６　シリコン貫通ビア
ＳＷ１～ＳＷ１６　プログラマブルスイッチ
Ｔ１～Ｔ３７　端子 DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device 2-4 Semiconductor chip 5 Clock distribution circuit 6 Control circuit 7 Logic circuit 7a, 7b Logic circuit 8 Clock distribution circuit 9 Control circuit 10 Logic circuit 10a, 10b Logic circuit 11 Clock distribution circuit 12 Control circuit 13 Logic circuit 13a, 13b Logic circuit 14 Clock signal generation circuit 15 Clock signal selection circuit 16 Clock signal selection circuit 17 Clock signal generation circuit 18 Clock signal selection circuit 19 Clock signal selection circuit 20 Clock signal generation circuit 21 Clock signal selection circuit 22 Clock signal selection circuit 22 Clock signal selection circuit 23 Through-silicon via 23a Through-silicon via 24 Through-silicon via 24a Through-silicon via 25 Through-silicon via 25a Through-silicon via 26 Through-silicon via 26a Through-silicon via 27 Through-silicon via 28 Through-silicon via 29 variable delay element circuit 29a variable delay element circuit 30 peripheral circuit 31 reconfigurable circuit 31a circuit block 31b circuit block 31c circuit block 31d circuit block 32 peripheral circuit 33 reconfigurable circuit 33a circuit block 33b circuit block 33c circuit block 33d circuit block 34 Peripheral circuit 35 Reconfigurable circuit 35a Circuit block 35b Circuit block 35c Circuit block 35d Circuit block 36 Through-silicon vias SW1 to SW16 Programmable switch T1 to T37 terminals

Claims (8)

  1. 　積層された複数の半導体チップと、前記半導体チップ間を貫通してそれぞれ接続する貫通配線とを有した半導体集積回路装置であって、
    　複数の前記半導体チップは、
    　周波数、および位相の異なる複数種類のクロック信号を生成するクロック信号生成回路と、
    　制御信号に基づいて、入力されたクロック信号のうち、任意のクロック信号を選択して出力するクロック信号選択回路と、
    　前記クロック信号選択回路によって選択されたクロック信号が供給される論理ブロックとをそれぞれ備え、
    　前記クロック信号選択回路は、
    　前記制御信号に基づいて、前記クロック信号生成回路が生成した任意のクロック信号、および前記貫通配線を介して入力される他の前記半導体チップに設けられた前記クロック信号生成回路が生成したクロック信号から任意のクロック信号を選択し、前記論理ブロックに供給するように切り替えることを特徴とする半導体集積回路装置。     A semiconductor integrated circuit device having a plurality of stacked semiconductor chips and through wirings that penetrate and connect between the semiconductor chips,
    The plurality of semiconductor chips are:
    A clock signal generation circuit for generating a plurality of types of clock signals having different frequencies and phases;
    A clock signal selection circuit that selects and outputs an arbitrary clock signal among the input clock signals based on the control signal; and
    A logic block to which a clock signal selected by the clock signal selection circuit is supplied,
    The clock signal selection circuit includes:
    Based on an arbitrary clock signal generated by the clock signal generation circuit based on the control signal and a clock signal generated by the clock signal generation circuit provided in another semiconductor chip that is input through the through wiring A semiconductor integrated circuit device, wherein an arbitrary clock signal is selected and switched to be supplied to the logic block.
  2. 　請求項１記載の半導体集積回路装置において、
    　前記クロック信号選択回路は、
    　クロック信号に同期して動作する前記論理ブロックのクロック入力端子の前段にそれぞれ備えられることを特徴とする半導体集積回路装置。     The semiconductor integrated circuit device according to claim 1.
    The clock signal selection circuit includes:
    A semiconductor integrated circuit device, which is provided in a preceding stage of a clock input terminal of the logic block that operates in synchronization with a clock signal.
  3. 　請求項１記載の半導体集積回路装置において、
    　複数の前記半導体チップは、
    　制御信号に基づいて、前記論理ブロックに供給されるクロック信号を任意の時間遅延させる遅延回路をそれぞれ備えたことを特徴とする半導体集積回路装置。     The semiconductor integrated circuit device according to claim 1.
    The plurality of semiconductor chips are:
    A semiconductor integrated circuit device comprising delay circuits for delaying a clock signal supplied to the logic block for an arbitrary time based on a control signal.
  4. 　請求項１記載の半導体集積回路装置において、
    　前記クロック信号選択回路は、
    　前記制御信号にしたがって接続先を再構成可能なプログラマブルスイッチから構成されることを特徴とする半導体集積回路装置。     The semiconductor integrated circuit device according to claim 1.
    The clock signal selection circuit includes:
    A semiconductor integrated circuit device comprising a programmable switch whose connection destination can be reconfigured in accordance with the control signal.
  5. 　積層された複数の半導体チップと、前記半導体チップ間を貫通してそれぞれ接続する貫通配線とを有した半導体集積回路装置であって、
    　複数の前記半導体チップは、
    　周波数、および位相の異なる複数種類のクロック信号を生成するクロック信号生成回路と、
    　制御信号に基づいて、入力されたクロック信号のうち、任意のクロック信号を選択して出力する第１のクロック信号選択回路と、
    　前記第１のクロック信号選択回路の後段に設けられ、任意のクロック信号を選択して出力する第２のクロック信号選択回路と、
    　前記第２のクロック信号選択回路によって選択されたクロック信号が供給される論理ブロックとをそれぞれ備え、
    　前記第１のクロック信号選択回路は、
    　前記制御信号に基づいて、前記クロック信号生成回路が生成した任意のクロック信号、および前記貫通配線を介して入力される他の前記半導体チップに設けられた前記クロック信号生成回路が生成したクロック信号から任意のクロック信号を選択して出力し、
    　前記第２のクロック信号選択回路は、
    　前記制御信号に基づいて、前記第１のクロック信号選択回路から出力されたクロック信号、および前記貫通配線を介して入力される他の前記半導体チップに設けられた前記第１のクロック信号選択回路から出力されるクロック信号から任意のクロック信号を選択して前記論理ブロックに供給するように切り替えることを特徴とする半導体集積回路装置。     A semiconductor integrated circuit device having a plurality of stacked semiconductor chips and through wirings that penetrate and connect between the semiconductor chips,
    The plurality of semiconductor chips are:
    A clock signal generation circuit for generating a plurality of types of clock signals having different frequencies and phases;
    A first clock signal selection circuit that selects and outputs an arbitrary clock signal among the input clock signals based on the control signal;
    A second clock signal selection circuit provided after the first clock signal selection circuit for selecting and outputting an arbitrary clock signal;
    A logic block to which a clock signal selected by the second clock signal selection circuit is supplied,
    The first clock signal selection circuit includes:
    Based on an arbitrary clock signal generated by the clock signal generation circuit based on the control signal and a clock signal generated by the clock signal generation circuit provided in another semiconductor chip that is input through the through wiring Select and output any clock signal,
    The second clock signal selection circuit includes:
    Based on the control signal, from the clock signal output from the first clock signal selection circuit and from the first clock signal selection circuit provided in the other semiconductor chip input via the through wiring A semiconductor integrated circuit device, wherein an arbitrary clock signal is selected from output clock signals and switched to be supplied to the logic block.
  6. 　請求項５記載の半導体集積回路装置において、
    　前記第２のクロック信号選択回路は、
    　前記論理ブロックのクロック入力端子の前段に備えられることを特徴とする半導体集積回路装置。     The semiconductor integrated circuit device according to claim 5.
    The second clock signal selection circuit includes:
    A semiconductor integrated circuit device provided in a stage preceding a clock input terminal of the logic block.
  7. 　請求項５記載の半導体集積回路装置において、
    　複数の前記半導体チップは、
    　制御信号に基づいて、前記論理ブロックに供給されるクロック信号を任意の時間遅延させる遅延回路をそれぞれ備えたことを特徴とする半導体集積回路装置。     The semiconductor integrated circuit device according to claim 5.
    The plurality of semiconductor chips are:
    A semiconductor integrated circuit device comprising delay circuits for delaying a clock signal supplied to the logic block for an arbitrary time based on a control signal.
  8. 　請求項５記載の半導体集積回路装置において、
    　前記第１、および前記第２のクロック信号選択回路は、
    　前記制御信号にしたがって接続先を再構成可能なプログラマブルスイッチから構成されることを特徴とする半導体集積回路装置。     The semiconductor integrated circuit device according to claim 5.
    The first and second clock signal selection circuits are:
    A semiconductor integrated circuit device comprising a programmable switch whose connection destination can be reconfigured in accordance with the control signal.
PCT/JP2011/061975 2010-06-11 2011-05-25 Semiconductor integrated circuit device WO2011155333A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015019030A (en) * 2013-07-12 2015-01-29 キヤノン株式会社 Semiconductor device
JP2017174394A (en) * 2016-03-16 2017-09-28 株式会社リコー Semiconductor integrated circuit and clock supply method for semiconductor integrated circuit
US20220200611A1 (en) * 2020-12-17 2022-06-23 Movellus Circuits Incorporated Field programmable platform array

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61180468A (en) * 1985-02-06 1986-08-13 Agency Of Ind Science & Technol Laminated type semiconductor device
JPH02301162A (en) * 1989-05-16 1990-12-13 Mitsubishi Electric Corp Laminated type semiconductor integrated circuit
JP2000260961A (en) * 1999-03-05 2000-09-22 Rohm Co Ltd Multichip semiconductor device
JP2006032731A (en) * 2004-07-16 2006-02-02 Advantest Corp Semiconductor integrated circuit
JP2007228145A (en) * 2006-02-22 2007-09-06 Ricoh Co Ltd Semiconductor integrated circuit
JP2008217063A (en) * 2007-02-28 2008-09-18 Ricoh Co Ltd Semiconductor device
JP2009194363A (en) * 2008-01-18 2009-08-27 National Institute Of Advanced Industrial & Technology 3-dimensional integrated circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61180468A (en) * 1985-02-06 1986-08-13 Agency Of Ind Science & Technol Laminated type semiconductor device
JPH02301162A (en) * 1989-05-16 1990-12-13 Mitsubishi Electric Corp Laminated type semiconductor integrated circuit
JP2000260961A (en) * 1999-03-05 2000-09-22 Rohm Co Ltd Multichip semiconductor device
JP2006032731A (en) * 2004-07-16 2006-02-02 Advantest Corp Semiconductor integrated circuit
JP2007228145A (en) * 2006-02-22 2007-09-06 Ricoh Co Ltd Semiconductor integrated circuit
JP2008217063A (en) * 2007-02-28 2008-09-18 Ricoh Co Ltd Semiconductor device
JP2009194363A (en) * 2008-01-18 2009-08-27 National Institute Of Advanced Industrial & Technology 3-dimensional integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015019030A (en) * 2013-07-12 2015-01-29 キヤノン株式会社 Semiconductor device
JP2017174394A (en) * 2016-03-16 2017-09-28 株式会社リコー Semiconductor integrated circuit and clock supply method for semiconductor integrated circuit
US20220200611A1 (en) * 2020-12-17 2022-06-23 Movellus Circuits Incorporated Field programmable platform array

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