JP2000260961A - Multichip semiconductor device - Google Patents

Multichip semiconductor device

Info

Publication number
JP2000260961A
JP2000260961A JP11058078A JP5807899A JP2000260961A JP 2000260961 A JP2000260961 A JP 2000260961A JP 11058078 A JP11058078 A JP 11058078A JP 5807899 A JP5807899 A JP 5807899A JP 2000260961 A JP2000260961 A JP 2000260961A
Authority
JP
Japan
Prior art keywords
chip
circuit
semiconductor device
semiconductor
fpga
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11058078A
Other languages
Japanese (ja)
Other versions
JP3754221B2 (en
Inventor
Hiroo Mochida
博雄 持田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP05807899A priority Critical patent/JP3754221B2/en
Priority to US09/517,283 priority patent/US6337579B1/en
Publication of JP2000260961A publication Critical patent/JP2000260961A/en
Application granted granted Critical
Publication of JP3754221B2 publication Critical patent/JP3754221B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a field programmable gate array which can reduce the number of outside connecting terminals. SOLUTION: A chip-on-chip semiconductor device is constituted by laying and joining a slave chip 2 upon and to the surface of a master chip 1. On the master chip 1, a field programmable gate array(FPGA) circuit 50 and a switching circuit 51 are formed. On the slave chip 2, a nonvolatile configuration memory circuit 60 is formed for storing the circuit setting information of the FPGA circuit 50. The FPGA circuit 50 or configuration memory circuit 60 is selectively connected to outside connecting pads 12 via the switching circuit 51. The memory circuit 60 can be programmed via the pads 12 and switching circuit 51. In addition, input and output can be made to and from the FPGA circuit 50 via the pads 12 and the switching circuit 51.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は、フィールドプロ
グラマブルゲートアレイを有するマルチチップ型半導体
装置に関する。The present invention relates to a multi-chip type semiconductor device having a field programmable gate array.

【０００２】[0002]

【従来の技術】ユーザが所望の回路をプログラムするこ
とができるＦＰＧＡ（フィールドプログラマブルゲート
アレイ）は、とくに、多品種少量生産品に利用されるこ
とが多い。従来から用いられているＦＰＧＡは、図５に
示すように、プログラマブルゲートアレイ１０１と、こ
のプログラマブルゲートアレイ１０１のスイッチの状態
を設定するためのＳＲＡＭ（スタティックＲＡＭ）１０
２とをＣＭＯＳプロセスで集積したＦＰＧＡチップ１０
０からなる。そして、このＦＰＧＡチップ１００を内蔵
したＩＣパッケージに、ＥＰＲＯＭ１１０が外付けされ
る。このＥＰＲＯＭ１１０に、プログラマブルゲートア
レイ１０１のスイッチの状態を設定するためのスイッチ
設定情報を書き込むことにより、所望の回路が得られ
る。2. Description of the Related Art An FPGA (Field Programmable Gate Array) that allows a user to program a desired circuit is often used particularly for a wide variety of small-quantity products. As shown in FIG. 5, a conventionally used FPGA includes a programmable gate array 101 and an SRAM (static RAM) 10 for setting a state of a switch of the programmable gate array 101.
FPGA chip 10 integrated with CMOS process 2
Consists of zero. The EPROM 110 is externally attached to an IC package containing the FPGA chip 100. By writing switch setting information for setting the state of the switches of the programmable gate array 101 into the EPROM 110, a desired circuit can be obtained.

【０００３】ＦＰＧＡチップ１００およびＥＰＲＯＭ１
１０は、それぞれ、別のＩＣパッケージに収容され、こ
れらの間の接続は、プリント配線基板を介して達成され
るようになっているのが一般的である。[0003] FPGA chip 100 and EPROM1
Generally, each is accommodated in a separate IC package, and the connection between them is generally achieved via a printed wiring board.

【０００４】[0004]

【発明が解決しようとする課題】しかし、上述の構成で
は、ＦＰＧＡチップ１００には、ＥＰＲＯＭ１１０との
接続のための接続パッドを設けなければならないから、
その分、チップ面積が大きくなったり、プログラマブル
ゲートアレイ１０１への信号の入出力数が制限されたり
するという問題がある。However, in the above configuration, the FPGA chip 100 must be provided with connection pads for connection to the EPROM 110.
Accordingly, there is a problem that the chip area becomes large and the number of input / output of signals to / from the programmable gate array 101 is limited.

【０００５】この問題は、ＦＰＧＡとＥＰＲＯＭとを１
チップに集積することによって解決されるであろうが、
ゲートアレイとＥＰＲＯＭとを共通のチップ上に形成す
るプロセスは極めて複雑であり、コストの大幅な増加に
つながるため、好ましい解決方法とは言えない。また、
ＦＰＧＡがＥＰＲＯＭとともに組み込まれた電子機器が
市場に出回ると、ＥＰＲＯＭの内容が、第三者によって
容易に読み出されるおそれがあり、このＥＰＲＯＭの記
憶データの秘密性が保持できないことも、問題となって
いた。[0005] The problem is that the FPGA and the EPROM are one
It will be solved by integrating on a chip,
The process of forming the gate array and the EPROM on a common chip is extremely complex and leads to a significant increase in cost, which is not a preferred solution. Also,
When an electronic device in which an FPGA is incorporated together with an EPROM is on the market, the contents of the EPROM may be easily read by a third party, and it is also a problem that the confidentiality of the data stored in the EPROM cannot be maintained. Was.

【０００６】そこで、この発明の目的は、上述の技術的
課題を解決し、外部接続端子数を少なくすることができ
る、フィールドプログラマブルゲートアレイを有するマ
ルチチップ型半導体装置を提供することである。また、
この発明の他の目的は、設定情報の秘密性を良好に保持
することができる、フィールドプログラマブルゲートア
レイを有するマルチチップ型半導体装置を提供すること
である。An object of the present invention is to provide a multi-chip type semiconductor device having a field programmable gate array which solves the above-mentioned technical problems and can reduce the number of external connection terminals. Also,
It is another object of the present invention to provide a multi-chip type semiconductor device having a field programmable gate array, which can maintain the confidentiality of setting information in a good manner.

【０００７】[0007]

【課題を解決するための手段および発明の効果】上記の
目的を達成するための請求項１記載の発明は、フィール
ドプログラマブルゲートアレイを有する第１の半導体チ
ップと、上記フィールドプログラマブルゲートアレイの
回路設定のための設定情報を記憶するための書き込み可
能な不揮発性メモリを有する第２の半導体チップと、上
記第１の半導体チップと上記第２の半導体チップとを接
続するチップ間接続部材とを含むことを特徴とするマル
チチップ型半導体装置である。According to the first aspect of the present invention, there is provided a first semiconductor chip having a field programmable gate array, and a circuit setting of the field programmable gate array. Semiconductor chip having a writable non-volatile memory for storing setting information for the semiconductor device, and an inter-chip connecting member for connecting the first semiconductor chip and the second semiconductor chip Is a multi-chip type semiconductor device.

【０００８】上記の構成によれば、第１の半導体チップ
に形成されたフィールドプログラマブルゲートアレイの
設定情報は、第２の半導体チップに形成された不揮発性
メモリに記憶されるようになっていて、これらの第１お
よび第２の半導体チップは、チップ間接続部材によっ
て、互いに接続されるようになっている。そして、第１
および第２の半導体チップは、たとえば、共通のパッケ
ージ内に封止されるなどして、マルチチップ型半導体装
置を構成している。According to the above configuration, the setting information of the field programmable gate array formed on the first semiconductor chip is stored in the nonvolatile memory formed on the second semiconductor chip. These first and second semiconductor chips are connected to each other by an inter-chip connecting member. And the first
The second semiconductor chip and the second semiconductor chip are sealed in, for example, a common package to constitute a multi-chip semiconductor device.

【０００９】これにより、フィールドプログラマブルゲ
ートアレイの回路を設定するための外部接続端子を省く
ことができるから、外部接続端子数を少なくすることが
でき、フィールドプログラマブルゲートアレイの入出力
数についての制限が少なくなる。また、フィールドプロ
グラマブルゲートアレイと不揮発性メモリとは、別のチ
ップ上に形成されるので、製造プロセスが複雑になるこ
ともない。Thus, the number of external connection terminals for setting the circuit of the field programmable gate array can be omitted, so that the number of external connection terminals can be reduced, and the number of inputs and outputs of the field programmable gate array is limited. Less. Further, since the field programmable gate array and the nonvolatile memory are formed on different chips, the manufacturing process does not become complicated.

【００１０】なお、上記チップ間接続部材は、ボンディ
ングワイヤであってもよい。また、請求項４に記載され
ているようなチップ・オン・チップ構造が採用される場
合には、第１および／または第２の半導体チップの表面
に形成された金属隆起電極であってもよい。この金属隆
起電極は、厚膜状のバンプであってもよく、バンプほど
は高さの高くない金属薄膜（たとえば、金属蒸着膜）で
あってもい。[0010] The inter-chip connecting member may be a bonding wire. In the case where the chip-on-chip structure as described in claim 4 is adopted, a metal raised electrode formed on the surface of the first and / or second semiconductor chip may be used. . The metal bump electrode may be a thick-film bump or a metal thin film (for example, a metal vapor-deposited film) not as high as the bump.

【００１１】請求項２記載の発明は、上記第１の半導体
チップは、上記不揮発性メモリのプログラム端子と、上
記フィールドプログラマブルゲートアレイの入出力端子
とに共通に用いられる外部接続端子と、この外部接続端
子を上記不揮発性メモリまたは上記フィールドプログラ
マブルゲートアレイに選択的に接続する切り換え回路と
を含むものであることを特徴とする請求項１記載のマル
チチップ型半導体装置である。According to a second aspect of the present invention, the first semiconductor chip includes an external connection terminal commonly used for a program terminal of the nonvolatile memory, an input / output terminal of the field programmable gate array, and an external connection terminal. 2. The multi-chip semiconductor device according to claim 1, further comprising a switching circuit for selectively connecting a connection terminal to said nonvolatile memory or said field programmable gate array.

【００１２】この構成によれば、第１の半導体チップ
は、不揮発性メモリのプログラムと、フィールドプログ
ラマブルゲートアレイに対する入出力とに共通に用いら
れる外部接続端子を有している。そして、切り換え回路
によってこの外部接続端子の接続を切り換える構成とな
っているので、外部接続端子を効果的に削減できる。こ
れにより、第１半導体チップのチップ面積の削減に寄与
することができ、また、フィールドプログラマブルゲー
トアレイの入出力数に対する制限も軽減できる。According to this configuration, the first semiconductor chip has the external connection terminals commonly used for the program of the nonvolatile memory and the input / output to / from the field programmable gate array. Since the connection of the external connection terminals is switched by the switching circuit, the number of external connection terminals can be effectively reduced. Thereby, it is possible to contribute to the reduction of the chip area of the first semiconductor chip, and it is also possible to reduce the limitation on the number of inputs and outputs of the field programmable gate array.

【００１３】請求項３記載の発明は、上記外部接続端子
と上記不揮発性メモリとの間の接続を永久的に遮断する
設定情報保護機構をさらに含むことを特徴とする請求項
２記載のマルチチップ型半導体装置である。この構成に
よれば、不揮発性メモリに設定情報を書き込んだ後に、
設定情報保護機構により、不揮発性メモリと外部接続端
子との間を永久的に遮断すれば、不揮発性メモリへの外
部からのアクセスが不可能な状態となる。これにより、
不揮発性メモリの設定情報の秘密性が保持される。According to a third aspect of the present invention, there is provided the multi-chip according to the second aspect, further comprising a setting information protection mechanism for permanently disconnecting the connection between the external connection terminal and the nonvolatile memory. Semiconductor device. According to this configuration, after writing the setting information to the nonvolatile memory,
If the setting information protection mechanism permanently cuts off the connection between the nonvolatile memory and the external connection terminal, external access to the nonvolatile memory becomes impossible. This allows
The confidentiality of the setting information in the nonvolatile memory is maintained.

【００１４】請求項４記載の発明は、上記第１の半導体
チップの表面に上記第２の半導体チップが重ねて接合さ
れ、これらの第１および第２の半導体チップがチップ・
オン・チップ構造で接合されていることを特徴とする請
求項１ないし３のいずれかに記載のマルチチップ型半導
体装置である。この構成によれば、第１および第２の半
導体チップが重ねて接合されているので、マルチチップ
型半導体装置は、実質的に１チップとして取り扱うこと
ができ、マスク方式のＡＳＩＣ（Application Specific
Integrated Circuit）とほぼ同一形状となる。したが
って、別パッケージのＥＰＲＯＭが必要であった従来技
術に比較して、格段に専有面積が減少するうえ、マスク
式のＡＳＩＣとの置き換えをも容易に行うことができ
る。According to a fourth aspect of the present invention, the second semiconductor chip is superimposed on and joined to the surface of the first semiconductor chip, and the first and second semiconductor chips are bonded to each other.
4. The multi-chip semiconductor device according to claim 1, wherein the semiconductor device is joined in an on-chip structure. According to this configuration, since the first and second semiconductor chips are overlapped and joined, the multi-chip type semiconductor device can be substantially handled as one chip, and a mask type ASIC (Application Specific
Integrated Circuit). Therefore, the occupied area is significantly reduced as compared with the related art in which an EPROM of a separate package is required, and replacement with a mask-type ASIC can be easily performed.

【００１５】しかも、チップ・オン・チップ構造では、
チップ間の配線長が極めて短くなるので、外部からのノ
イズの影響を受けにくく、また、高速な動作が可能であ
るという効果をも奏することができる。Moreover, in the chip-on-chip structure,
Since the wiring length between the chips is extremely short, it is hardly affected by external noise, and the effect that high-speed operation is possible can also be achieved.

【００１６】[0016]

【発明の実施の形態】以下では、この発明の実施の形態
を、添付図面を参照して詳細に説明する。図１は、この
発明の第１の実施形態に係るマルチチップ型半導体装置
の分解斜視図であり、図２は、当該半導体装置の断面図
である。この半導体装置は、第１の半導体チップとして
の親チップ１の表面１１に、第２の半導体チップとして
の子チップ２を重ね合わせて接合した、いわゆるチップ
・オン・チップ（Chip-On-Chip）構造を有している。こ
のチップ・オン・チップ構造のマルチチップ型半導体装
置は、外部との接続のためのリードフレーム１４が引き
出された状態で樹脂モールドされ、パッケージ４０に納
められている。Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is an exploded perspective view of a multi-chip type semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a sectional view of the semiconductor device. This semiconductor device is a so-called Chip-On-Chip in which a child chip 2 as a second semiconductor chip is superposed and joined to a surface 11 of a parent chip 1 as a first semiconductor chip. It has a structure. The multi-chip type semiconductor device having the chip-on-chip structure is resin-molded in a state where the lead frame 14 for connection to the outside is pulled out, and is housed in a package 40.

【００１７】親チップ１は、たとえばシリコンチップか
らなっており、フィールドプログラマブルゲートアレイ
（ＦＰＧＡ）回路を内部に有している。この親チップ１
の表面１１は、親チップ１の基体をなす半導体基板にお
いてトランジスタなどの機能素子が形成された活性表層
領域側の表面であり、最表面は、絶縁物の保護膜で覆わ
れている。この保護膜上には、所定の位置において、外
部接続用の複数のパッド１２が、ほぼ矩形の平面形状を
有する親チップ１の表面１１の周縁付近に露出して配置
されている。この外部接続パッド１２は、ボンディング
ワイヤ１３によってリードフレーム１４に接続されてい
る。The parent chip 1 is made of, for example, a silicon chip, and has a field programmable gate array (FPGA) circuit therein. This parent chip 1
The surface 11 is a surface on the active surface layer region side on which a functional element such as a transistor is formed on a semiconductor substrate serving as a base of the parent chip 1, and the outermost surface is covered with a protective film of an insulator. On the protective film, a plurality of pads 12 for external connection are arranged at predetermined positions so as to be exposed near the periphery of the surface 11 of the parent chip 1 having a substantially rectangular planar shape. This external connection pad 12 is connected to a lead frame 14 by a bonding wire 13.

【００１８】親チップ１の内方の領域には、子チップ２
の接合領域１５が設定されており、この接合領域１５に
は、子チップ２とのチップ間接続のためのチップ接続パ
ッドＰＭが、複数個（図１では８個のみ図示）形成され
ている。子チップ２は、たとえばシリコンチップからな
っており、ＥＰＲＯＭ（消去可能なプログラム可能読取
り専用記憶装置）などからなる、ＦＰＧＡのスイッチ状
態を設定するための不揮発性のメモリ回路（以下、「不
揮発性コンフィギュレーションメモリ回路」という。）
を内部に有している。この子チップ２の表面２１は、子
チップ２の基体をなす半導体基板においてトランジスタ
などの機能素子が形成された活性表層領域側の表面であ
り、最表面は、絶縁物の保護膜で覆われている。この保
護膜上には、親チップ１とのチップ間接続のためのチッ
プ接続パッドＰＤが、複数個（図１では８個のみ図示）
形成されている。In the area inside the parent chip 1, the child chip 2
A plurality of chip connection pads PM (only eight are shown in FIG. 1) for connecting the chips to the child chip 2 are formed in the bonding region 15. The slave chip 2 is formed of, for example, a silicon chip, and includes a nonvolatile memory circuit (hereinafter referred to as “nonvolatile configuration”) for setting a switch state of the FPGA, such as an EPROM (erasable programmable read-only storage device). Memory memory circuit.)
Inside. The surface 21 of the child chip 2 is a surface on the active surface layer region side on which a functional element such as a transistor is formed on a semiconductor substrate serving as a base of the child chip 2, and the outermost surface is covered with an insulating protective film. I have. On this protective film, a plurality of chip connection pads PD for chip-to-chip connection with the parent chip 1 (only eight are shown in FIG. 1)
Is formed.

【００１９】子チップ２のチップ接続パッドＰＤ上に
は、耐酸化性の金属、たとえば、金、鉛、プラチナ、銀
またはイリジウムからなるバンプＢがそれぞれ形成され
ていて、チップ間接続部材をなす金属隆起電極を構成し
ている。子チップ２は、表面２１を親チップ１の表面１
１に対向させた状態で親チップ１に接合されている。こ
の接合は、バンプＢを接合領域１５のチップ接続パッド
ＰＭにそれぞれ当接させた状態で、親チップ１と子チッ
プ２とを相互に圧着することにより達成される。この圧
着の際、必要に応じて親チップ１および／または子チッ
プ２に超音波振動を与えることにより、バンプＢとチッ
プ接続パッドＰＭとの確実な接合が達成される。On the chip connection pads PD of the child chip 2, bumps B made of an oxidation-resistant metal, for example, gold, lead, platinum, silver or iridium are formed, respectively, and the metal forming the inter-chip connection member is formed. It constitutes a raised electrode. The child chip 2 has the front surface 21 that is the front surface 1 of the parent chip 1.
1 and is joined to the parent chip 1. This bonding is achieved by pressing the parent chip 1 and the child chip 2 together with the bumps B in contact with the chip connection pads PM in the bonding area 15. At the time of this pressure bonding, by applying ultrasonic vibration to the parent chip 1 and / or the child chip 2 as necessary, reliable bonding between the bump B and the chip connection pad PM is achieved.

【００２０】図３は、上述のマルチチップ型半導体装置
の電気的構成を示すブロック図である。親チップ１は、
ＦＰＧＡ回路５０（プログラマブルゲートアレイ）と切
り換え回路５１とを内部回路として有しており、ＦＰＧ
Ａチップを構成している。子チップ２は、不揮発性コン
フィギュレーションメモリ回路６０（以下「コンフィギ
ュレーションメモリ回路６０」という。）を内部回路と
して有しており、コンフィギュレーションメモリチップ
を構成している。FIG. 3 is a block diagram showing an electrical configuration of the above-mentioned multi-chip type semiconductor device. Parent chip 1
It has an FPGA circuit 50 (programmable gate array) and a switching circuit 51 as internal circuits.
A chip is constituted. The child chip 2 has a nonvolatile configuration memory circuit 60 (hereinafter, referred to as “configuration memory circuit 60”) as an internal circuit, and forms a configuration memory chip.

【００２１】親チップ１と子チップ２とを接合した状態
では、コンフィギュレーションメモリ回路６０は、所定
のチップ接続パッドＰＭ，ＰＤおよびバンプＢが形成す
るチップ間接続部Ｃ１を介して、ＦＰＧＡ回路５０に接
続される。ＦＰＧＡ回路５０の内部のスイッチは、コン
フィギュレーションメモリ回路６０に記憶されている設
定情報に従って切り換えられる。したがって、コンフィ
ギュレーションメモリ回路６０に、所望の回路に対応し
た設定情報を書き込んでおけば、ＦＰＧＡ回路５０は、
所望の構成の回路を形成する。In a state where the parent chip 1 and the child chip 2 are joined, the configuration memory circuit 60 sends the FPGA circuit 50 via the chip connection portion C1 formed by the predetermined chip connection pads PM and PD and the bump B. Connected to. The switches inside the FPGA circuit 50 are switched according to the setting information stored in the configuration memory circuit 60. Therefore, if setting information corresponding to a desired circuit is written in the configuration memory circuit 60, the FPGA circuit 50
A circuit having a desired configuration is formed.

【００２２】ＦＰＧＡ回路５０の入出力ライン６５は、
外部接続パッド１２に接続されている。入出力ライン６
５の一部は、切り換え回路５１を介して外部接続パッド
１２に接続されている。切り換え回路５１は、入出力ラ
イン６５に接続されているとともに、所定のチップ接続
パッドＰＭ，ＰＤおよびバンプＢが形成するチップ間接
続部Ｃ２を介して、コンフィギュレーションメモリ回路
６０に接続されている。The input / output lines 65 of the FPGA circuit 50
It is connected to the external connection pad 12. Input / output line 6
A part of 5 is connected to the external connection pad 12 via the switching circuit 51. The switching circuit 51 is connected to the input / output line 65, and is also connected to the configuration memory circuit 60 via a chip connection portion C2 formed by predetermined chip connection pads PM and PD and the bump B.

【００２３】切り換え回路５１は、個々のチップ間接続
部Ｃ２に対応するスイッチＳＷ１，ＳＷ２，・・・・・・を有
している。各スイッチＳＷ１，ＳＷ２，・・・・・・は、外部
接続パッド１２と入出力ライン６５を接続する状態と、
外部接続パッド１２とチップ間接続部Ｃ２とを接続する
状態とに切り換えることができる。切り換えスイッチＳ
Ｗ１，ＳＷ２，・・・・・・に接続された外部接続パッド１２
およびそれらに接続されるリードフレーム１４は、コン
フィギュレーションメモリ回路６０のプログラムのため
のプログラム端子と、ＦＰＧＡ回路５０の入出力端子と
に共通に用いられる外部接続端子を成している。切り換
えスイッチＳＷ１，ＳＷ２，・・・・・・は、所定の外部接続
パッド１２から入力される切り換え制御信号によって、
上記２つの状態のいずれかをとる。The switching circuit 51 has switches SW1, SW2,... Corresponding to the respective inter-chip connecting portions C2. Each of the switches SW1, SW2,... Connects the external connection pad 12 to the input / output line 65,
The state can be switched to a state in which the external connection pad 12 and the inter-chip connection portion C2 are connected. Switch S
External connection pads 12 connected to W1, SW2,.
The lead frame 14 connected to them constitutes an external connection terminal commonly used for a program terminal for programming the configuration memory circuit 60 and an input / output terminal of the FPGA circuit 50. The changeover switches SW1, SW2,... Are controlled by a changeover control signal input from a predetermined external connection pad 12.
It takes one of the above two states.

【００２４】この半導体装置の使用に際しては、まず、
切り換え回路５１のスイッチＳＷ１，ＳＷ２，・・・・・・を
コンフィギュレーションメモリ回路６０側に接続するた
めの切り換え制御信号が入力される。この状態で、切り
換え回路５１に接続されている外部接続パッド１２か
ら、コンフィギュレーションメモリ回路６０に、ＦＰＧ
Ａ回路５０の回路設定のための設定情報が書き込まれ
る。この設定情報の書き込みの後には、切り換え制御信
号は、スイッチＳＷ１，ＳＷ２，・・・・・・をＦＰＧＡ回路
５０の入出力ライン６５側に接続する状態とされる（た
とえば、切り換え制御信号を入力するための外部接続パ
ッド１２を開放状態とする。）。これにより、切り換え
回路５１に接続されている外部接続パッド１２は、ＦＰ
ＧＡ回路５０の入出力のために使用可能な状態となる。When using this semiconductor device, first,
A switching control signal for connecting the switches SW1, SW2,... Of the switching circuit 51 to the configuration memory circuit 60 is input. In this state, the FPG is supplied from the external connection pad 12 connected to the switching circuit 51 to the configuration memory circuit 60.
Setting information for circuit setting of the A circuit 50 is written. After the writing of the setting information, the switching control signal is set to a state in which the switches SW1, SW2,... Are connected to the input / output line 65 side of the FPGA circuit 50 (for example, the switching control signal is input). The external connection pad 12 is opened.) Thereby, the external connection pad 12 connected to the switching circuit 51 is connected to the FP
The state becomes available for input / output of the GA circuit 50.

【００２５】コンフィギュレーションメモリ回路６０へ
の設定情報の書き込みが完了すれば、ＦＰＧＡ回路５０
は、その設定情報に従う回路を形成する。そして、コン
フィギュレーションメモリ回路６０は、当該設定情報を
不揮発に記憶するので、この半導体装置への電源の供給
が遮断されて、その後に、再びこの半導体装置を用いる
ときには、ＦＰＧＡ回路５０は、当初から所望の回路を
形成することになる。When the writing of the setting information to the configuration memory circuit 60 is completed, the FPGA circuit 50
Form a circuit according to the setting information. Then, since the configuration memory circuit 60 stores the setting information in a nonvolatile manner, the power supply to the semiconductor device is cut off, and when the semiconductor device is used again thereafter, the FPGA circuit 50 starts from the beginning. A desired circuit will be formed.

【００２６】このように、この実施形態によれば、ＦＰ
ＧＡ回路５０を内蔵した親チップ１と、コンフィギュレ
ーションメモリ回路６０を内蔵した子チップ２とをチッ
プ・オン・チップ接合することによって、実質的に１チ
ップとして取り扱うことが可能なマルチチップ型半導体
装置を構成している。これにより、設定情報を記憶する
ＥＰＲＯＭを外付けすることなく所望の回路を構成する
ことができるから、外部接続端子数を少なくすることが
できる。別の観点から見れば、外部接続端子のほぼすべ
てをＦＰＧＡ回路５０への入出力のために用いることが
できるので、入出力数の制限を少なくすることができ
る。Thus, according to this embodiment, the FP
A chip-on-chip joining of a parent chip 1 having a built-in GA circuit 50 and a child chip 2 having a built-in configuration memory circuit 60 results in a multi-chip type semiconductor device which can be handled substantially as one chip. Is composed. As a result, a desired circuit can be configured without externally attaching an EPROM for storing setting information, and the number of external connection terminals can be reduced. From another viewpoint, almost all of the external connection terminals can be used for input and output to and from the FPGA circuit 50, so that the limitation on the number of input and output can be reduced.

【００２７】しかも、外付けのＥＰＲＯＭが不要である
から、マスク方式のＡＳＩＣとほぼ同形状のＦＰＧＡが
実現できることになり、占有面積を格段に減少させるこ
とができるうえ、マスク方式のＡＳＩＣとの置き換えを
も容易に行うことができる。さらに、この実施形態の構
成では、外部接続パッド１２の一部が、コンフィギュレ
ーションメモリ回路６０へのプログラムと、ＦＰＧＡ回
路５０への入出力とに共用されているので、これによっ
ても、外部接続端子の削減が図られており、また、ＦＰ
ＧＡ回路５０への入出力数に対する制限の軽減が図られ
ている。Moreover, since an external EPROM is not required, an FPGA having substantially the same shape as the mask type ASIC can be realized, the occupied area can be remarkably reduced, and the mask type ASIC can be replaced. Can also be easily performed. Further, in the configuration of this embodiment, a part of the external connection pad 12 is shared for the program to the configuration memory circuit 60 and the input and output to and from the FPGA circuit 50. Has been reduced, and FP
The limitation on the number of inputs and outputs to the GA circuit 50 is reduced.

【００２８】図４は、この発明の第２の実施形態に係る
マルチチップ型半導体装置の電気的構成を示すブロック
図である。この半導体装置は、上述の第１の実施形態に
係る半導体装置と類似しているので、図４において、上
述の図３に示された各部に対応する部分には、図４の場
合と同一の参照符号を付すとともに、上述の図１および
図２を再び参照することとする。FIG. 4 is a block diagram showing an electrical configuration of a multi-chip type semiconductor device according to a second embodiment of the present invention. This semiconductor device is similar to the semiconductor device according to the above-described first embodiment, and therefore, in FIG. 4, portions corresponding to the respective portions shown in FIG. The reference numerals are used, and the above-mentioned FIGS. 1 and 2 are referred to again.

【００２９】この実施形態では、コンフィギュレーショ
ンメモリ回路６０に書き込まれた設定情報に対する外部
からのアクセスを禁止するための設定情報保護機構７０
が備えられている。この設定情報保護機構７０は、この
実施形態においては、排他的論理和ゲート７１と、この
排他的論理和ゲート７１の両端子間に接続されたアンチ
ヒューズ７２とで構成されている。排他的論理和ゲート
７１の一対の入力端子は、それぞれ外部接続パッド１２
のうちの所定の一対のパッド１２１，１２２に接続され
ている。そして、排他的論理和ゲート７１のパッド１２
１側の入力端子には、抵抗７３を介して電源電圧Ｖccが
与えられ、排他的論理和ゲート７１のパッド１２２側の
入力端子には、抵抗７４を介してグランド電位が与えら
れるようになっている。In this embodiment, a setting information protection mechanism 70 for inhibiting external access to the setting information written in the configuration memory circuit 60.
Is provided. In this embodiment, the setting information protection mechanism 70 includes an exclusive OR gate 71 and an antifuse 72 connected between both terminals of the exclusive OR gate 71. A pair of input terminals of the exclusive OR gate 71 are connected to the external connection pad 12 respectively.
Are connected to a predetermined pair of pads 121 and 122. The pad 12 of the exclusive OR gate 71
The power supply voltage Vcc is applied to the input terminal on the 1 side via the resistor 73, and the ground potential is applied to the input terminal on the pad 122 side of the exclusive OR gate 71 via the resistor 74. I have.

【００３０】切り換え回路５１を構成するスイッチＳＷ
１，ＳＷ２，・・・・・・は、それぞれ、正論理（ハイアクテ
ィブ）型ゲートＧＰ（たとえば、ＮチャンネルＭＯＳト
ランジスタのゲートにハイレベルが印加されることによ
り導通）と負論理（ローアクティブ）型ゲートＧＮ（た
とえば、正論理型ゲートＧＰのＮチャンネルＭＯＳトラ
ンジスタが非導通のときに導通）との対で構成されてい
る。そして、正論理型ゲートＧＰの一方の出力端子は、
チップ間接続部Ｃ２を介してコンフィギュレーションメ
モリ回路６０に接続されており、負論理型ゲートＧＮの
一方の出力端子は、入出力ライン６５を介してＦＰＧＡ
５０に接続されている。正論理型ゲートＧＰおよび負論
理型ゲートＧＮの各他方の出力端子は、外部接続パッド
１２に共通に接続されている。A switch SW constituting the switching circuit 51
1, SW2,... Are a positive logic (high active) type gate GP (for example, conducting when a high level is applied to the gate of an N-channel MOS transistor) and a negative logic (low active). And a type gate GN (for example, conducting when the N-channel MOS transistor of the positive logic type gate GP is non-conducting). One output terminal of the positive logic type gate GP is
One output terminal of the negative logic type gate GN is connected to the configuration memory circuit 60 via the inter-chip connection portion C2, and is connected to the FPGA via an input / output line 65.
50. The other output terminals of the positive logic gate GP and the negative logic gate GN are commonly connected to the external connection pad 12.

【００３１】正論理型ゲートＧＰおよび負論理型ゲート
ＧＮの各制御入力端子には、切り換え制御ライン７８を
介して、排他的論理和ゲート７１の出力信号が切り換え
制御信号として入力されるようになっている。コンフィ
ギュレーションメモリ回路６０にＦＰＧＡ回路５０の回
路設定のための設定情報をプログラムするときには、排
他的論理和ゲート７１の両端子に接続されたパッド１２
１，１２１は、いずれも開放状態とされる。また、初期
状態では、アンチヒューズ７２は、遮断状態となってい
る。したがって、排他的論理和ゲート７１には、一方の
入力端子からは電源電圧Ｖccが入力され、他方の端子か
らはグランド電位が与えられる。そのため、排他的論理
和ゲート７１の出力信号は、ハイレベルとなる。したが
って、正論理型ゲートＧＰは導通状態となり、負論理型
ゲートＧＮは遮断状態となる。よって、この状態では、
切り換え回路５１に接続されている外部接続パッド１２
を介して、コンフィギュレーションメモリ回路６０をプ
ログラムすることができる。The output signal of the exclusive OR gate 71 is input as a switching control signal to each control input terminal of the positive logic gate GP and the negative logic gate GN via a switching control line 78. ing. When setting information for circuit setting of the FPGA circuit 50 is programmed in the configuration memory circuit 60, the pad 12 connected to both terminals of the exclusive OR gate 71 is programmed.
Each of the reference numerals 1 and 121 is in an open state. In the initial state, the antifuse 72 is in a cutoff state. Therefore, the power supply voltage Vcc is input from one input terminal to the exclusive OR gate 71, and the ground potential is applied from the other terminal. Therefore, the output signal of the exclusive OR gate 71 becomes high level. Therefore, the positive logic gate GP is turned on, and the negative logic gate GN is turned off. Therefore, in this state,
External connection pad 12 connected to switching circuit 51
, The configuration memory circuit 60 can be programmed.

【００３２】一方、コンフィギュレーションメモリ回路
６０のプログラムが終了した後には、パッド１２１，１
２２間に適当な電圧が印加される。これにより、アンチ
ヒューズ７２は、排他的論理和ゲート７１の両端子間を
短絡した状態となり、この状態は、パッド１２１，１２
２間への電圧の印加を停止した後も、永久的に保持され
る。したがって、以後は、排他的論理和ゲート７１の出
力信号は、パッド１２１，１２２への電圧印加状態に関
わりなく、ローレベルとなる。これにより、負論理型ゲ
ートＧＮは導通状態となり、正論理型ゲートＧＰは遮断
状態となって、以後は、正論理型ゲートＧＰが導通する
ことはない。On the other hand, after the programming of the configuration memory circuit 60 is completed, the pads 121, 1
An appropriate voltage is applied between 22. As a result, the antifuse 72 is in a state where both terminals of the exclusive OR gate 71 are short-circuited.
Even after the application of the voltage between the two is stopped, it is kept permanently. Therefore, thereafter, the output signal of the exclusive OR gate 71 becomes low level irrespective of the voltage application state to the pads 121 and 122. As a result, the negative logic gate GN is turned on, the positive logic gate GP is turned off, and thereafter, the positive logic gate GP is not turned on.

【００３３】したがって、切り換え回路５１に接続され
た外部接続パッド１２からは、専ら、ＦＰＧＡ回路５０
へのアクセスのみが可能であって、コンフィギュレーシ
ョンメモリ回路６０へのアクセスは不可能になる。これ
により、コンフィギュレーションメモリ回路６０の内容
が読み出されたりすることがなくなるから、コンフィギ
ュレーションメモリ回路６０の設定情報の秘密性を保持
することができる。Therefore, from the external connection pad 12 connected to the switching circuit 51, only the FPGA circuit 50
Access to the configuration memory circuit 60 is not possible. This prevents the contents of the configuration memory circuit 60 from being read out, so that the confidentiality of the setting information of the configuration memory circuit 60 can be maintained.

【００３４】以上、この発明の２つの実施形態について
説明したが、この発明は他の形態でも実施することが可
能である。たとえば、上述の実施形態では、コンフィギ
ュレーションメモリ回路６０に対するプログラムは、切
り換え回路５１に接続された外部接続パッド１２のみを
用いて行われるようになっているが、コンフィギュレー
ションメモリ回路６０に対するプログラムのための配線
の一部は、切り換え回路５１を介さずに専用の外部接続
パッド１２に接続されていてもよい。Although the two embodiments of the present invention have been described above, the present invention can be implemented in other embodiments. For example, in the above embodiment, the programming for the configuration memory circuit 60 is performed using only the external connection pads 12 connected to the switching circuit 51. May be connected to the dedicated external connection pad 12 without passing through the switching circuit 51.

【００３５】また、上述の実施形態では、子チップ２に
バンプＢを設けているが、親チップ１側に同様のバンプ
を設けてもよく、親チップ１および子チップ２の両方に
バンプを設けて、バンプ同士を接合することによって親
チップ１および子チップ２のチップ・オン・チップ接合
を達成してもよい。また、親チップ１と子チップ２と接
合する金属隆起電極は、さほどの高さを要しないので、
一般に電解めっきまたは無電解めっきによって形成され
るバンプのほかにも、金属蒸着膜のような金属薄膜で構
成することもできる。In the above-described embodiment, the bump B is provided on the child chip 2. However, a similar bump may be provided on the parent chip 1 side, and the bump is provided on both the parent chip 1 and the child chip 2. Thus, chip-on-chip joining of the parent chip 1 and the child chip 2 may be achieved by joining the bumps. In addition, since the metal bump electrode that is joined to the parent chip 1 and the child chip 2 does not require much height,
In general, besides the bumps formed by electrolytic plating or electroless plating, they can be formed of a metal thin film such as a metal deposition film.

【００３６】さらに、上記の実施形態では、親チップ１
および子チップ２がバンプＢを介して接合されたチップ
・オン・チップ構造のマルチチップ型半導体装置を例に
挙げたが、親チップの表面に子チップ２の裏面（活性表
層領域とは反対側の面）を対向させて接合し、チップ接
続パッド間の接続をワイヤボンディングにより行う構成
のチップ・オン・チップ構造の装置にも、この発明を適
用することが可能である。また、ワイヤボンディングに
より半導体チップ間が接続される場合には、必ずしもチ
ップ・オン・チップ構造をとる必要はない。さらに、配
線基板上に複数の半導体チップが接合され、この配線基
板を介して半導体チップ間の接続が達成される構成の半
導体装置に対しても、この発明を適用することが可能で
ある。Further, in the above embodiment, the parent chip 1
And a multi-chip type semiconductor device having a chip-on-chip structure in which the child chip 2 is bonded via bumps B, the back surface of the child chip 2 (the side opposite to the active surface layer region) The present invention can also be applied to a device having a chip-on-chip structure in which the semiconductor device is bonded such that the surfaces thereof face each other and the connection between the chip connection pads is performed by wire bonding. When the semiconductor chips are connected by wire bonding, it is not always necessary to adopt a chip-on-chip structure. Further, the present invention can be applied to a semiconductor device having a configuration in which a plurality of semiconductor chips are bonded on a wiring board and connection between the semiconductor chips is achieved via the wiring board.

【００３７】さらに、上記の実施形態では、親チップ１
および子チップ２は、いずれもシリコンからなるチップ
であることとしたが、シリコンの他にも、化合物半導体
（ガリウム砒素半導体等）やゲルマニウム半導体などの
他の任意の半導体材料を用いた半導体チップをこの発明
の半導体装置に適用することができる。この場合に、第
１の半導体チップと第２の半導体チップとの半導体材料
は、同じでもよいし異なっていてもよい。Further, in the above embodiment, the parent chip 1
Each of the sub-chips 2 is a chip made of silicon. However, in addition to silicon, a semiconductor chip using any other semiconductor material such as a compound semiconductor (such as a gallium arsenide semiconductor) or a germanium semiconductor may be used. The present invention can be applied to the semiconductor device of the present invention. In this case, the semiconductor materials of the first semiconductor chip and the second semiconductor chip may be the same or different.

【００３８】その他、特許請求の範囲に記載された事項
の範囲で種々の設計変更を施すことが可能である。In addition, various design changes can be made within the scope of the matters described in the claims.

【図面の簡単な説明】[Brief description of the drawings]

【図１】この発明の第１の実施形態に係るマルチチップ
型半導体装置の分解斜視図である。FIG. 1 is an exploded perspective view of a multi-chip semiconductor device according to a first embodiment of the present invention.

【図２】上記マルチチップ型半導体装置の断面図であ
る。FIG. 2 is a sectional view of the multi-chip type semiconductor device.

【図３】上記マルチチップ型半導体装置の電気的構成を
示すブロック図である。FIG. 3 is a block diagram illustrating an electrical configuration of the multi-chip type semiconductor device.

【図４】この発明の第２の実施形態に係るマルチチップ
型半導体装置の電気的構成を示すブロック図である。FIG. 4 is a block diagram showing an electrical configuration of a multichip semiconductor device according to a second embodiment of the present invention.

【図５】従来のＦＰＧＡの構成を説明するためのブロッ
ク図である。FIG. 5 is a block diagram for explaining a configuration of a conventional FPGA.

【符号の説明】[Explanation of symbols]

１ 親チップ（第１の半導体チップ） ２ 子チップ（第２の半導体チップ） １２，１２１，１２２ 外部接続パッド ５０ ＦＰＧＡ回路 ５１ 切り換え回路 ６０ 不揮発性コンフィギュレーションメモリ回路 ６５ 入出力ライン Ｃ１，Ｃ２ チップ間接続部 ＰＭ，ＰＤ チップ接続パッド Ｂ バンプ ７０ 設定情報保護機構 ７１ 排他的論理和ゲート ７２ アンチヒューズ Reference Signs List 1 parent chip (first semiconductor chip) 2 child chip (second semiconductor chip) 12, 121, 122 external connection pad 50 FPGA circuit 51 switching circuit 60 nonvolatile configuration memory circuit 65 input / output line C1, C2 Connection PM, PD Chip connection pad B Bump 70 Setting information protection mechanism 71 Exclusive OR gate 72 Antifuse

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】フィールドプログラマブルゲートアレイを
有する第１の半導体チップと、 上記フィールドプログラマブルゲートアレイの回路設定
のための設定情報を記憶するための書き込み可能な不揮
発性メモリを有する第２の半導体チップと、 上記第１の半導体チップと上記第２の半導体チップとを
接続するチップ間接続部材とを含むことを特徴とするマ
ルチチップ型半導体装置。A first semiconductor chip having a field programmable gate array; a second semiconductor chip having a writable nonvolatile memory for storing setting information for setting a circuit of the field programmable gate array; A multi-chip type semiconductor device, comprising: an inter-chip connecting member for connecting the first semiconductor chip and the second semiconductor chip. 【請求項２】上記第１の半導体チップは、上記不揮発性
メモリのプログラム端子と、上記フィールドプログラマ
ブルゲートアレイの入出力端子とに共通に用いられる外
部接続端子と、この外部接続端子を上記不揮発性メモリ
または上記フィールドプログラマブルゲートアレイに選
択的に接続する切り換え回路とを含むものであることを
特徴とする請求項１記載のマルチチップ型半導体装置。2. The semiconductor device according to claim 1, wherein the first semiconductor chip includes an external connection terminal commonly used for a program terminal of the nonvolatile memory, an input / output terminal of the field programmable gate array, and the external connection terminal. 2. The multi-chip type semiconductor device according to claim 1, further comprising a switching circuit selectively connected to the memory or the field programmable gate array. 【請求項３】上記外部接続端子と上記不揮発性メモリと
の間の接続を永久的に遮断する設定情報保護機構をさら
に含むことを特徴とする請求項２記載のマルチチップ型
半導体装置。3. The multi-chip semiconductor device according to claim 2, further comprising a setting information protection mechanism for permanently interrupting a connection between said external connection terminal and said nonvolatile memory. 【請求項４】上記第１の半導体チップの表面に上記第２
の半導体チップが重ねて接合され、これらの第１および
第２の半導体チップがチップ・オン・チップ構造で接合
されていることを特徴とする請求項１ないし３のいずれ
かに記載のマルチチップ型半導体装置。4. The method according to claim 1, wherein the second semiconductor chip is provided on a surface of the first semiconductor chip.
4. The multi-chip type according to claim 1, wherein said first and second semiconductor chips are joined together in a chip-on-chip structure. Semiconductor device.
JP05807899A 1999-03-05 1999-03-05 Multi-chip type semiconductor device Expired - Fee Related JP3754221B2 (en)

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