JP2012029211A - Timing adjustment circuit - Google Patents

Timing adjustment circuit Download PDF

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JP2012029211A
JP2012029211A JP2010168256A JP2010168256A JP2012029211A JP 2012029211 A JP2012029211 A JP 2012029211A JP 2010168256 A JP2010168256 A JP 2010168256A JP 2010168256 A JP2010168256 A JP 2010168256A JP 2012029211 A JP2012029211 A JP 2012029211A
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circuit
delay
unit
signal
timing adjustment
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JP2010168256A
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Japanese (ja)
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隆行 ▲浜▼田
Takayuki Hamada
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Fujitsu Ltd
富士通株式会社
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Abstract

A timing adjustment circuit capable of generating a signal that is continuously and smoothly interpolated with a delay time is provided.
A coarse adjustment delay circuit that delays an input signal in units of a predetermined delay time, and a unit delay that receives a coarse adjustment signal output from the coarse adjustment delay circuit and is delayed by the predetermined delay time. A unit delay circuit 2 that outputs a signal, and a phase interpolation circuit 3 that receives the coarse adjustment signal and the unit delay signal and interpolates a phase between the coarse adjustment signal and the unit delay signal, and the phase The interpolation circuit 3 has a trimming unit 33 provided on the input side of the unit delay circuit.
[Selection] Figure 8

Description

  The embodiments referred to in this application relate to timing adjustment circuits.

  In recent years, the performance improvement of a semiconductor storage device (for example, DRAM: Dynamic Random Access Memory) and a processor used for a computer or other information processing equipment has been remarkable. Accordingly, signal transmission between chips mounted on a board or between a plurality of elements and circuit blocks in one chip must be performed accurately and at high speed.

  Therefore, for example, a timing adjustment circuit for controlling the delay time of each data signal is provided on the transmission side so that a plurality of data signals can be sampled at an optimum timing by the clock signal on the reception side.

  Specifically, for example, there is known one that controls a delay line in which a plurality of unit delay units are connected by using a delay locked loop (DLL) circuit.

  In addition, the timing adjustment circuit using the delay line and the DLL circuit is limited in the delay time that can be controlled by the delay time by the unit delay unit, so the delay time by the unit delay unit is interpolated to control a finer delay time. What to do is also known.

  By the way, conventionally, various timing adjustment circuits have been proposed.

Japanese Patent Laid-Open No. 06-204792 JP 2004-110490 A JP 2001-297585 A Japanese Patent Laid-Open No. 11-088153 JP 2001-119272 A JP 2000-298532 A JP 2001-111394 A

Takefumi Enomoto et al., "A 667-Mb / s Operating Digital DLL Architecture for 512-Mb DDR SDRAM", IEEE J Solid- State Circuits, Vol. 39, pp.194-206, published in January 2004

  As described above, for example, a timing adjustment circuit using a delay line and a DLL circuit is known which controls a finer delay time by interpolating a delay time by a unit delay unit.

  However, the interpolation of the delay time, for example, has a step difference for each delay time of the unit delay unit, and it has been difficult to perform it continuously and smoothly.

  According to an embodiment, a timing adjustment circuit is provided that includes a coarse adjustment delay circuit that delays an input signal in units of a predetermined delay time, a unit delay circuit, and a phase interpolation circuit.

  The unit delay circuit receives the coarse adjustment signal output from the coarse adjustment delay circuit and outputs a unit delay signal delayed by the predetermined delay time. The phase interpolation circuit receives the coarse adjustment signal and the unit delay signal, and interpolates a phase between the coarse adjustment signal and the unit delay signal.

  The phase interpolation circuit includes a trimming unit provided on the input side of the unit delay circuit.

  The disclosed timing adjustment circuit can produce a signal that is continuously and smoothly interpolated with a delay time.

It is a figure which shows the example of application of a timing adjustment circuit. FIG. 2 is a block diagram illustrating an example of a DLL circuit in the timing adjustment circuit of FIG. 1. FIG. 3 is a circuit diagram illustrating an example of a unit delay unit in the DLL circuit of FIG. 2. It is a block diagram which shows an example of the phase interpolation circuit in a timing adjustment circuit. FIG. 5 is a circuit diagram illustrating an example of an inverter unit in the phase interpolation circuit of FIG. 4. FIG. 5 is a diagram showing a change in delay time in a timing adjustment circuit to which the phase interpolation circuit of FIG. 4 is applied. It is a block diagram which shows the timing adjustment circuit of one Example. FIG. 8 is a block diagram showing a phase interpolation circuit in the timing adjustment circuit of FIG. 7. It is a circuit diagram which shows the trimming unit in the phase interpolation circuit of FIG. It is a figure for demonstrating adjustment of the time at the time of a delay by the trimming unit of FIG. It is a figure which shows the change of the time at the time of a delay in the timing adjustment circuit of FIG.

  First, before describing embodiments of the timing adjustment circuit in detail, the timing adjustment circuit and its problems will be described with reference to FIGS.

  FIG. 1 is a diagram illustrating an application example of a timing adjustment circuit. 1, reference numeral 100 is a timing adjustment circuit, 101 is a DLL circuit, 110, 111,... Are data signal delay lines, and 201 and 210, 211,.

  The skew elements 201 and 210, 211,... Are, for example, capacitances parasitic on the wiring (printed wiring) on the board when the transmitting side and the receiving side are integrated circuits (LSIs) provided on the board (printed circuit board). is there.

  In addition, the skew elements 201 and 210, 211,... Are, for example, wiring capacities on a chip when the transmission side and the reception side are circuit blocks in one chip.

  Here, for example, the skew elements 201 and 210, 211,... Have different wiring lengths and parasitic capacitances, so that the timing of the clock signal and each of the data signals DATA0, DATA1,. Become.

  The clock signal CLK from the transmission side is delayed by a skew element 201 on the board and transmitted to the reception side, for example. Further, the data signals DATA0, DATA1,... From the transmission side are delayed by the skew elements 201 and 210, 211,.

  .. Are not all the same, so that the timing adjustment circuit 100 on the transmission side can sample the data signals DATA0, DATA1,... Is provided.

  That is, by controlling the delay time by the delay lines 110, 111,... Of the timing adjustment circuit 100 provided on the transmission side, individual delays are given to the plurality of data signals DATA0, DATA1,. ing.

  As a result, on the receiving side, the transition timing of the clock signal CLK comes to an intermediate position between the transition timings of the data signals DATA0, DATA1,... (Approximately the center of the data signal eye), and the data signal is correctly sampled. It becomes possible.

  Note that the control (setting) of the delay time of the data signals DATA0, DATA1,... By the timing adjustment circuit 100 provided on the transmission side is executed as, for example, a training sequence performed when the system is turned on. Further, the number of data signal lines from the transmission side to the reception side may be a plurality of data signals DATA0, DATA1,... That can be transmitted in parallel, but may be one.

  Thus, for example, when there is a single clock signal and a single or multiple data signals, the timing adjustment circuit 100 gives an appropriate delay to the single or multiple data signals and samples them with the clock signal. Used to adjust to possible phase difference. Needless to say, the timing adjustment circuit referred to in this specification is not limited to the one for adjusting the phase of such a data signal.

  By the way, in a digital control timing adjustment circuit, an inverter (unit delay unit) of cascaded CMOS circuits is used as a delay circuit for giving a delay to a signal, and the delay amount is determined by the number of stages passing through the inverter. Yes.

  In the delay circuit, for example, the delay fluctuates due to dynamic variations in temperature and power supply voltage. Therefore, in order to keep the delay time constant, for example, the number of passing stages of the unit delay unit is dynamically controlled.

  FIG. 2 is a block diagram showing an example of the DLL circuit in the timing adjustment circuit of FIG. 1, and FIG. 3 is a circuit diagram showing an example of the unit delay unit in the DLL circuit of FIG. Here, FIG. 2 shows the DLL circuit 101 focusing on one data signal (DATA0).

  As shown in FIG. 2, the DLL circuit 101 includes a plurality of unit delay units DU0, DU1,..., DUn connected in cascade, a phase comparison circuit 131, and a control circuit 132. One of the plurality of unit delay units DU0, DU1,..., DUn connected in cascade is selected by the enable signals EN0, EN1,.

  As shown in FIG. 3, the unit delay unit DU (DU0, DU1,..., DUn) includes an inverter INV1 and three NAND gates NAND1 to NAND3. The unit delay unit DU defines the unit delay unit DU to be turned back by setting the enable signal EN to a high level “H”. Here, a unit in which a plurality of unit delay units (delay circuits) are connected is referred to as a delay line.

  The phase comparison circuit 131 receives the original clock signal CLK and a delayed clock signal CLKd having a delay amount determined by the number of stages of delay units that pass through. Then, the phase comparison circuit 131 controls via the control circuit 132 so that the phase difference between the signals CLK and CLKd corresponds to exactly one cycle of the clock signal.

  That is, the control circuit 132 outputs the enable signals EN0, EN1,..., ENn for the respective unit delay units DU0, DU1,..., DUn according to the phase comparison result of the signals CLK and CLKd from the phase comparison circuit 131 and performs control. The signal CS is output.

  The control signal CS is a control signal for the delay line of the data signal, and the delay to be given to the data signal can be calculated as a ratio to the period of the clock signal.

  Thus, in the digital control timing adjustment circuit, the minimum delay adjustment accuracy is limited by the delay time of the unit delay unit DU.

  However, for example, when the number of passing stages in the DLL circuit is 99 and the phase difference to be given to the data signal is π / 2 radians with respect to the clock cycle, the number of delay stages to be passed is 99/4 = 24.75. It becomes impossible to take the delay amount of the calculated value.

  FIG. 4 is a block diagram showing an example of a phase interpolation circuit in the timing adjustment circuit, in which a phase interpolation circuit (fine adjustment delay circuit) is connected in cascade to a delay line to perform phase interpolation.

  The phase interpolation circuit 300 is connected to the input and output of the unit delay circuit DUC, and controls the first inverter unit 301 provided on the input side, the second inverter unit 302 provided on the output side, and those inverter units. And a controller 303 for

  Here, the other ends of the first inverter unit 301 and the second inverter unit 302 having one end provided on the input side and the output side of the unit delay circuit DUC are grounded via a capacitor C.

  FIG. 5 is a circuit diagram showing an example of an inverter unit in the phase interpolation circuit of FIG. The first inverter unit 301 and the second inverter unit 302 are basically the same.

  As shown in FIG. 5, the inverter unit 301 (302) has a plurality of inverters connected in parallel, and each inverter has a high impedance (Hi-Z) by a control signal IS11 (IS12) from the controller 303. The state can be taken.

  The input of the unit delay circuit DUC is grounded through the number of inverters defined by the control signal IS11 in the first inverter unit 301 and the capacitor C. The output of the unit delay circuit DUC is grounded through the number of inverters defined by the control signal IS12 in the second inverter unit 302 and the capacitor C.

  That is, the data signal before passing through the unit delay circuit DUC is connected to the first inverter unit 301, and the data signal after passing through the unit delay circuit DUC is connected to the second inverter unit 302, and the Hi-Z state inverter in each inverter unit Change the number of.

  Thus, the delay amount is adjusted by using a coarse adjustment delay line based on the number of passing stages of the unit delay circuit DUC and a fine adjustment circuit that adjusts the delay amount below the unit delay circuit DUC using the phase interpolation circuit 300 described above. Control can be performed.

  FIG. 6 is a diagram showing a change in delay time in the timing adjustment circuit to which the phase interpolation circuit of FIG. 4 is applied. Here, the vertical axis represents a delay amount (delay time), and the horizontal axis represents a control code for controlling the number of Hi-Z inverters in the inverter unit.

  In a delay circuit in which a coarse adjustment delay line and a fine adjustment phase interpolation circuit (fine adjustment delay circuit) are connected in cascade, when control is performed to increase the amount of delay, the delay is first made by changing the control code of the fine adjustment delay circuit. Increase.

  When the delay that can be taken by the fine adjustment delay circuit is maximized (in FIG. 6, x points), the number of passing stages of the coarse adjustment delay line is increased by one, and the control code of the fine adjustment delay circuit is minimized. Control is performed so that the delay amount is reached (in FIG. 6, ● points).

  In order to increase or decrease the delay continuously (monotonically) by controlling the number of stages of the coarse adjustment delay line and the control code of the fine adjustment delay circuit, the range of possible values of the delay of the fine adjustment delay circuit is a unit. It is assumed that it is the same as or smaller than the delay unit (unit delay circuit).

  However, in practice, for example, the delay increases or decreases due to variations in capacitance components parasitic on the input / output sides of the unit delay circuit DUC, and therefore the delay is not the same as the unit delay unit in the coarse adjustment delay line.

  That is, as shown in FIG. 6, when the fine adjustment delay circuit transitions from the maximum delay state (× location in FIG. 6) to the minimum state (● location in FIG. 6), the delay increases continuously. There is a possibility that a level difference may occur without being realized.

  Hereinafter, embodiments of the timing adjustment circuit will be described in detail with reference to the accompanying drawings. FIG. 7 is a block diagram illustrating a timing adjustment circuit according to an embodiment. In FIG. 7, reference numeral 1 is a coarse adjustment delay line, 2 is a unit delay circuit, 3 is a phase interpolation circuit, 4 is a control circuit, and 5 is a delay comparison circuit.

  Reference numeral 10 denotes a replica circuit unit, 11 denotes a replica coarse adjustment delay line, 12 denotes a replica unit delay circuit, and 13 denotes a replica phase interpolation circuit. The coarse adjustment delay lines 1 and 11, the unit delay circuits 2 and 12, and the phase interpolation circuits (fine adjustment delay circuits) 3 and 13 are the same.

  As shown in FIG. 7, the timing adjustment circuit includes a coarse adjustment delay line 1, a unit delay circuit 2 and a phase interpolation circuit 3, a replica circuit unit 10, a control circuit 4, and a delay comparison circuit 5. Here, the replica circuit unit 10 includes a replica coarse adjustment delay line 11, a replica unit delay circuit 12, and a replica phase interpolation circuit 13.

  An input signal (input clock signal) is input to the coarse adjustment delay line 1. For example, a signal (coarse adjustment signal) to which a delay amount by an n-stage delay unit is given is a unit delay circuit 2 and a phase interpolation circuit. 3 is supplied.

  Similarly, also in the replica circuit unit 10. The input signal is input to the replica coarse adjustment delay line 11 and, for example, a signal given a delay amount by an n-stage delay unit is supplied to the replica unit delay circuit 12 and the replica phase interpolation circuit 13.

  The output of the phase interpolation circuit 3 is output as an output signal (output clock signal), supplied to one input of the delay comparison circuit 5, and supplied to the other input of the delay comparison circuit 5. Is compared with the output of.

  Here, the unit delay circuit 2 delays the input signal by a predetermined delay time as a unit in the coarse adjustment delay line 1, and outputs the delayed unit delay signal. Further, the control circuit 4 outputs control signals IS1 and IS2 and a trimming signal TS according to the output (delay comparison result) of the delay comparison circuit 5 to the phase interpolation circuit 3.

  FIG. 8 is a block diagram showing a phase interpolation circuit in the timing adjustment circuit of FIG. 7, in which the phase interpolation circuit 3 is drawn together with the unit delay circuit 2 and the control circuit 4.

  As shown in FIG. 8, the phase interpolation circuit 3 includes a first inverter unit 31 provided on the input side of the unit delay circuit 2, a second inverter unit 32 provided on the output side of the unit delay circuit 2, and a capacitor C. And a trimming unit 33.

  Here, the first inverter unit 31 and the second inverter unit 32 are grounded via a capacitor C.

  The first and second inverter units 31 and 32 are the same as the inverter unit 301 (302) described with reference to FIG. 5, and are in the Hi-Z state by the control signal IS1 (IS2) from the control circuit 4, respectively. Control the number of inverters.

  The input of the unit delay circuit 2 is grounded via the number of inverters defined by the control signal IS1 in the first inverter unit 31 and the capacitor C, and is connected to the trimming unit 33.

  The output of the unit delay circuit 2 is grounded through the number of inverters defined by the control signal IS2 in the second inverter unit 32 and the capacitor C.

  Here, assuming that M and N are natural numbers and N> M ≧ 1, each of the first inverter unit 31 and the second inverter unit 32 has N inverters that can take a high impedance state.

  The first inverter unit 31 turns on the M number of inverters to define the rising slope, and the second inverter unit 32 turns on the NM number of inverters, and the first and second inverter units. As a whole, N inverters are turned on.

  FIG. 9 is a circuit diagram showing a trimming unit in the phase interpolation circuit of FIG. As shown in FIG. 9, the trimming unit 33 has a plurality of capacitors 332a to 332d connected in series with a plurality of switches 331a to 331d.

  Here, the switches 331a to 331d are, for example, transfer gates, and the capacitors 332a to 332d are, for example, MOS capacitors formed on a semiconductor substrate.

  Here, the trimming unit 33 adjusts the capacitance between the input side of the unit delay circuit 2 and the ground by the switches 331a to 331d that are ON / OFF controlled according to the trimming signal TS from the control circuit 4. Yes.

  Next, the operation of the timing adjustment circuit of one embodiment will be described. First, in the timing adjustment circuit of FIG. 7, in addition to the delay amount for n unit delay units in the coarse adjustment delay line 1 of the main body, the delay amount for one stage by the unit delay circuit 2 (delay for n + 1 stages). Thus, the delay in the phase interpolation circuit 3 is set to the minimum state.

  On the other hand, the replica circuit unit 10 is set so that the delays of the unit delay units n stages in the replica coarse adjustment delay line 11 and the replica phase interpolation circuit 13 are maximized. Thereby, for example, the phase interpolation circuit 3 can be set to the maximum delay state.

  Then, when the possible range of the delay amount by the phase interpolation circuit 3 becomes larger than one unit delay unit of the coarse adjustment delay line 1 due to, for example, element variation, the control circuit 4 The capacity of the trimming unit 33 is controlled (increased) according to the output.

  The control circuit 5 controls the trimming signal TS for the trimming unit 33 to increase the number of on-state switches in the trimming unit 33. This process is repeated, and the process is terminated when the range of delay amount that can be taken by the phase interpolation circuit 3 becomes the same as the delay amount of one unit delay unit.

  That is, in the timing adjustment circuit of this embodiment, the trimming unit 33 is provided on the input side of the unit delay circuit 2, and the slope of the input signal before passing through the unit delay circuit 2 is changed to thereby change the output side of the phase interpolation circuit 3. It is designed to control the tilt.

  FIG. 10 is a diagram for explaining the adjustment of the delay time by the trimming unit of FIG. 8, and FIG. 11 is a diagram showing the change of the delay time in the timing adjustment circuit of FIG.

  Here, FIG. 10A shows an ideal output waveform, and FIG. 10B shows an output waveform when the output load of the unit delay circuit 2 is heavy, and FIG. ) Shows an output waveform when the trimming unit 33 adjusts the delay amount.

  As shown in FIG. 10B, when the output load of the unit delay circuit 2 is heavy, for example, the rising characteristic on the output side becomes gentle. At this time, as shown in FIG. 10C, the control circuit 4 controls the trimming unit 33 to adjust the rising characteristic on the input side to be the same as (parallel to) the output side.

  Thus, as is apparent from the comparison between FIG. 11 and FIG. 6, the fine adjustment delay circuit (phase interpolation circuit) in FIG. 6 eliminates the difference in level when the delay is changed from the maximum delay state to the minimum delay state. Can be increased.

  That is, according to the timing adjustment circuit of this embodiment, it is possible to generate a signal in which delay time is continuously and smoothly interpolated. The trimming unit 33 is not limited to the one shown in FIG. 9, and various types can be applied.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
A coarse adjustment delay circuit that delays an input signal in units of a predetermined delay time;
A unit delay circuit for receiving a coarse adjustment signal output from the coarse adjustment delay circuit and outputting a unit delay signal delayed by the predetermined delay time;
A phase interpolation circuit that receives the coarse adjustment signal and the unit delay signal and interpolates a phase between the coarse adjustment signal and the unit delay signal;
The phase interpolation circuit includes:
A timing adjustment circuit comprising a trimming unit provided on an input side of the unit delay circuit.

(Appendix 2)
In the timing adjustment circuit according to attachment 1,
The timing adjustment circuit, wherein the trimming unit adjusts a capacitance between an input side of the unit delay circuit and a ground.

(Appendix 3)
In the timing adjustment circuit according to attachment 2,
The trimming unit is
Multiple switches,
And a plurality of capacitors connected in series with each of the switches.

(Appendix 4)
In the timing adjustment circuit according to any one of appendices 1 to 3,
The phase interpolation circuit further includes:
A first inverter unit provided on the input side of the unit delay circuit;
A second inverter unit provided on the output side of the unit delay circuit;
And a capacitor provided between the first and second inverter units and the ground.

(Appendix 5)
In the timing adjustment circuit according to attachment 4,
A replica circuit unit having circuits corresponding to the coarse adjustment delay circuit, the unit delay circuit, and the phase interpolation circuit;
A delay comparison circuit that performs a delay comparison between the output of the phase interpolation circuit and the output of the phase interpolation circuit of the replica circuit unit;
The trimming unit and a control circuit for controlling the first and second inverter units according to the output of the delay comparison circuit, and the trimming unit is controlled by the control circuit. Timing adjustment circuit.

(Appendix 6)
In the timing adjustment circuit according to appendix 4 or 5,
M and N are natural numbers, and N> M ≧ 1,
The first and second inverter units each have N inverters that can take a high impedance state;
The first inverter unit turns on M inverters and defines a rising slope;
The second inverter unit turns on NM inverters, and turns on N inverters as a whole by the first and second inverter units.

DESCRIPTION OF SYMBOLS 1 Coarse adjustment delay line 2 Unit delay circuit 3,300 Phase interpolation circuit 4 Control circuit 5 Delay comparison circuit 10 Replica circuit part 11 Replica coarse adjustment delay line 12 Replica unit delay circuit 13 Replica phase interpolation circuit 31,301 1st inverter Unit 32, 302 Second inverter unit 33 Trimming unit 101 DLL circuit 110, 111, ... Data signal delay line 201, 210, 211, ... Skew element 303 Controller

Claims (5)

  1. A coarse adjustment delay circuit that delays an input signal in units of a predetermined delay time;
    A unit delay circuit for receiving a coarse adjustment signal output from the coarse adjustment delay circuit and outputting a unit delay signal delayed by the predetermined delay time;
    A phase interpolation circuit that receives the coarse adjustment signal and the unit delay signal and interpolates a phase between the coarse adjustment signal and the unit delay signal;
    The phase interpolation circuit includes:
    A timing adjustment circuit comprising a trimming unit provided on an input side of the unit delay circuit.
  2. The timing adjustment circuit according to claim 1,
    The timing adjustment circuit, wherein the trimming unit adjusts a capacitance between an input side of the unit delay circuit and a ground.
  3. The timing adjustment circuit according to claim 2,
    The trimming unit is
    Multiple switches,
    And a plurality of capacitors connected in series with each of the switches.
  4. The timing adjustment circuit according to any one of claims 1 to 3,
    The phase interpolation circuit further includes:
    A first inverter unit provided on the input side of the unit delay circuit;
    A second inverter unit provided on the output side of the unit delay circuit;
    And a capacitor provided between the first and second inverter units and the ground.
  5. The timing adjustment circuit according to claim 4, further comprising:
    A replica circuit unit having circuits corresponding to the coarse adjustment delay circuit, the unit delay circuit, and the phase interpolation circuit;
    A delay comparison circuit that performs a delay comparison between the output of the phase interpolation circuit and the output of the phase interpolation circuit of the replica circuit unit;
    The trimming unit and a control circuit for controlling the first and second inverter units according to the output of the delay comparison circuit, and the trimming unit is controlled by the control circuit. Timing adjustment circuit.
JP2010168256A 2010-07-27 2010-07-27 Timing adjustment circuit Pending JP2012029211A (en)

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Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6472641A (en) * 1987-09-08 1989-03-17 Tektronix Inc Skew correction apparatus
JPH05199088A (en) * 1991-02-25 1993-08-06 Toshiba Corp Delay circuit
JPH06204792A (en) * 1992-12-31 1994-07-22 Sony Corp Delay circuit
JPH0854957A (en) * 1994-08-12 1996-02-27 Hitachi Ltd Clock distribution system
JPH0918305A (en) * 1995-06-26 1997-01-17 Ando Electric Co Ltd Delay circuit
JPH09172356A (en) * 1995-12-19 1997-06-30 Fujitsu Ltd Delay circuit and digital phase lock circuit
JPH1055668A (en) * 1996-08-13 1998-02-24 Fujitsu Ltd Semiconductor integrated circuit, semiconductor integrated circuit module, and semiconductor integrated circuit system
JPH1188153A (en) * 1997-09-03 1999-03-30 Nec Corp Digital dll circuit
JP2000122750A (en) * 1998-10-15 2000-04-28 Fujitsu Ltd Timing clock generating circuit using hierarchical dll circuit
JP2001297585A (en) * 2000-04-18 2001-10-26 Mitsubishi Electric Corp Clock generating circuit, and semiconductor memory provided with it
JP2002508120A (en) * 1997-06-18 2002-03-12 クリーダンス システムズ コーポレイション A programmable delay circuit with a calibration delay
JP2003091331A (en) * 2001-09-19 2003-03-28 Elpida Memory Inc Interpolating circuit, dll circuit and semiconductor integrated circuit
JP2004129110A (en) * 2002-10-07 2004-04-22 Fujitsu Ltd Phase interpolation circuit

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6472641A (en) * 1987-09-08 1989-03-17 Tektronix Inc Skew correction apparatus
JPH05199088A (en) * 1991-02-25 1993-08-06 Toshiba Corp Delay circuit
JPH06204792A (en) * 1992-12-31 1994-07-22 Sony Corp Delay circuit
JPH0854957A (en) * 1994-08-12 1996-02-27 Hitachi Ltd Clock distribution system
JPH0918305A (en) * 1995-06-26 1997-01-17 Ando Electric Co Ltd Delay circuit
JPH09172356A (en) * 1995-12-19 1997-06-30 Fujitsu Ltd Delay circuit and digital phase lock circuit
JPH1055668A (en) * 1996-08-13 1998-02-24 Fujitsu Ltd Semiconductor integrated circuit, semiconductor integrated circuit module, and semiconductor integrated circuit system
JP2002508120A (en) * 1997-06-18 2002-03-12 クリーダンス システムズ コーポレイション A programmable delay circuit with a calibration delay
JPH1188153A (en) * 1997-09-03 1999-03-30 Nec Corp Digital dll circuit
JP2000122750A (en) * 1998-10-15 2000-04-28 Fujitsu Ltd Timing clock generating circuit using hierarchical dll circuit
JP2001297585A (en) * 2000-04-18 2001-10-26 Mitsubishi Electric Corp Clock generating circuit, and semiconductor memory provided with it
JP2003091331A (en) * 2001-09-19 2003-03-28 Elpida Memory Inc Interpolating circuit, dll circuit and semiconductor integrated circuit
JP2004129110A (en) * 2002-10-07 2004-04-22 Fujitsu Ltd Phase interpolation circuit

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