JP3378667B2 - Variable delay circuit for periodic clock - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit for varying the output timing of a periodic clock. 2. Description of the Related Art As a conventional example, there is a delay circuit for generating a ramp wave and making an output timing variable by using a comparator. This will be described with reference to FIGS. In the configuration of the present apparatus, as shown in FIG. 3, the periodic clock signal 70, which is an input signal of the ramp generator 52, is a clock signal generated at a constant period Tconst. The ramp generator 52 is a generator that generates a triangular waveform for each trigger signal, and generates a rising voltage having a slope proportional to time. That is, the rising edge of the periodic clock signal 70, which is an input, is detected as a trigger signal, and as shown in FIG. The output signal 53 of the ramp wave 80 is supplied to one input terminal of a comparator 58. The DA converter 56 is a DA converter that outputs an analog comparison voltage 57 in response to the setting of digital data. Upon receiving the delay amount setting data 55 from outside, an analog comparison voltage 57 corresponding to the data is supplied to the other input terminal of the comparator 58 as a reference comparison voltage. Comparator 5
Numeral 8 compares the two analog voltages. When the rising voltage of the ramp wave 80 detects the comparison voltage 57 or more, the output signal 59 becomes high level. With this configuration, by changing the value set in the DA converter 56, an arbitrary delay time can be given to the input periodic clock signal 70 and output. Here, the resolution of the delay time is the resolution of the DA converter 56,
Since it is determined by the slope of the ramp wave 80, a desired delay resolution can be easily obtained by using the DA converter 56 having a desired resolution. As described above, the ramp generator 52, the D / A converter 56, and the comparator 58 are composed of analog circuits, so that they can be integrated. In some cases, a jitter may occur in the output signal 59 due to the influence of noise of an adjacent signal. In addition, it is often the case that the cost of making the analog mixed circuit LSI is high. [0004] Therefore, an object to be solved by the present invention is to provide a variable delay circuit consisting of only a digital circuit to provide a stable circuit without generation of jitter due to integration.
It is an object of the present invention to realize a variable delay circuit that can be easily converted to an I type. FIG. 1 shows a solution according to the present invention. In order to solve the above problem, in the configuration of the present invention, the periodic clock signal 70 as an input is supplied to the input terminal of the first-stage gate 12a, and the constant period Tconst
Gates 12a-1a that provide a propagation delay exceeding several times
2n are connected in series, each output terminal of the plurality of gates 12a to 12n is connected to an input terminal of the selector 16, and a selector 16 for selecting and outputting one of the output signals of the plurality of gates 12a to 12n is provided. Make it a configuration means. Thereby, with a resolution less than the propagation delay time Td of the gate,
This is a means for realizing a variable delay circuit. There is also a configuration means for realizing the configuration of the plurality of gates and the selector by providing a plurality of stages in series. The overall propagation delay T due to gates 12a-12n
The total is provided several times or more of the period Tconst, and this is selected by the selector 16 to be the output signal 18, whereby the resolution of less than the gate propagation delay time Td is obtained. An embodiment of the present invention is a circuit that uses a propagation delay caused by the gates of a plurality of ICs as a delay element and uses this and a selector to vary the output timing. This will be described with reference to FIG. The configuration of this device is
As shown in FIG. 1, a periodic clock signal 70, which is an input signal of a plurality of gates 12a to 12n, has a constant period Tconst
Signal. The plurality of gates 12a to 12n are N gates, and each gate has substantially the same propagation delay T.
It is used as a delay element having d. These gates are connected in series, and are supplied from the output point of each gate 12n to the input terminal of the selector 16. Also multiple gates 1
The total propagation delay Ttotal due to 2a-12n is equal to the period Tc
Provide several times or more of onst. The selector 16 is a selector circuit having N inputs and one output. Any of the delayed signals from the N gates is selected by a selection signal 17 to become an output signal 18. Thus, the output signal 18 can be output as a signal delayed with a resolution of the gate propagation delay Td unit. As a result, the resolution obtained is determined by the propagation delay of the gate. However, in the present invention in which the total propagation delay Ttotal is set to several times or more of the period Tconst,
Focusing on the periodic clock signal 70 that is repeatedly generated, a resolution of less than one gate time can be obtained. This will be described below with reference to numerical examples. The propagation delay of the gate is, for example, Td = 90p
s, the number of gates used N = 900, and the period Tco
It is assumed that nst = 10 ns, and the value of the gate selection stage of the selector 16 is Sel. Here, description will be made assuming that the propagation delay of the selector 16 is 0 ns for ease of explanation.
The delay time at the output point 18 can be expressed by Tx = Td × Sel.
Here, since Td = 90 ps, the resolution is 90 ps.
Step. Next, the delay time from the position exceeding Tx> 10 ns is Tx = Td × at the position of Sel = 112.
Sel = 90 × 112 = 1,080 ps. If the period Tconst = 10 ns is subtracted here, 80 ps is the difference from the immediately preceding input period clock signal 70, and this can be regarded as the obtained delay time. That is, if one cycle Tconst time (10 ns) is delayed, the time obtained by adding the offset time of 80 ps becomes the delay time. Similarly, two cycles Tconst
If the time is delayed (20 ns), the offset time becomes 70 ps. Similarly, if three periods Tconst time (30 ns) delay, the offset time becomes 60 ps. Thus M
If the period Tconst time (M × 10 ns) is delayed, 90- (M
× 10) The offset time is ps. As shown in the above numerical example, the periodic clock signal 70
It can be seen from the fact that the output timing can be finely changed by setting the desired selection signal 17 even for a minute delay time shorter than the propagation delay of the gate. In addition, this realization circuit can be realized only by a digital circuit, and is suitable for LSI. In the above, actually, since the propagation delay of each gate has a variation, the selection signal 17 for determining the delay set value is set by using a value calibrated in advance, so that a normal A very small delay time can be obtained. (Application Example) In the description of the above embodiment, the case where one selector 16 is used has been described. However, as shown in FIG. 2, the configuration of a plurality of gates and selectors is changed to a configuration in which a plurality of stages are provided. Can be implemented in the same manner. Also,
In the description of the above embodiment, the power supply voltage supplied to the gates 12a to 12n is not described. Is obtained. By utilizing this change, a means for reducing the number N of the gates 12a to 12n may be used in combination or may be carried out in the same manner. Since the present invention is configured as described above, it has the following effects. The total propagation delay Ttotal by the gates 12a to 12n is
By providing the output signal 18 by selecting it by several times or more of the period Tconst and obtaining the output signal 18 by the selector 16, there is an effect that a resolution less than the gate propagation delay time Td can be obtained. As a result, a delay circuit capable of finely varying the output timing can be realized. Further, since this circuit is realized only by a digital circuit, there is an advantage that it can be easily formed into an LSI. Of course, since there is no analog circuit, it is possible to realize a stable variable delay circuit without generation of jitter due to integration. [0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a delay circuit of the present invention which uses a propagation delay caused by a plurality of gates as a delay element and uses this and a selector to vary output timing. FIG. 2 is a delay circuit according to the present invention, in which the configuration of a plurality of gates and selectors is provided in a plurality of stages to make output timing variable. FIG. 3 is an example of a conventional delay circuit that varies the output timing using the generation of a ramp wave and a comparator. FIG. 4 is a timing chart for explaining a conventional delay in output timing due to a slope of a triangular waveform of a ramp generator. [Description of Signs] 12a, 12n Gate 16 Selector 17 Selection signal 18, 59 Output signal 52 Ramp wave generator 55 Delay setting data 56 DA converter 57 Analog comparison voltage 58 Comparator 70 Period clock signal 80 Ramp wave

Claims (1)

(57) Claims 1. A delay circuit that receives a periodic clock signal (70) generated at a constant period (Tconst), applies a delay thereto, and outputs the delayed clock signal. A plurality of gates (12a to 12n) that provide a propagation delay exceeding several times are provided in series connection, and an output terminal of each of the plurality of gates (12a to 12n) is connected to an input terminal of the selector (16). A variable delay circuit for a periodic clock, comprising: a selector (16) for selecting and outputting one of output signals of a plurality of gates (12a to 12n).