CN110518884A - Be delayed amplifier - Google Patents
Be delayed amplifier Download PDFInfo
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- CN110518884A CN110518884A CN201910769767.3A CN201910769767A CN110518884A CN 110518884 A CN110518884 A CN 110518884A CN 201910769767 A CN201910769767 A CN 201910769767A CN 110518884 A CN110518884 A CN 110518884A
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- 230000003111 delayed effect Effects 0.000 title claims abstract description 21
- 230000010355 oscillation Effects 0.000 claims abstract description 132
- 230000003321 amplification Effects 0.000 claims abstract description 84
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 84
- 238000000034 method Methods 0.000 claims description 11
- 230000008859 change Effects 0.000 claims description 7
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- 235000003140 Panax quinquefolius Nutrition 0.000 claims description 4
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- 238000013016 damping Methods 0.000 claims 1
- 238000013461 design Methods 0.000 description 6
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- 230000000630 rising effect Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/14—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
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- Amplifiers (AREA)
Abstract
The present invention provides a kind of delay amplifiers, which is characterized in that the delay amplifier includes one or more levels amplifying circuit；Delay amplification circuit of the level-one based on self-timing oscillation rings is included at least in one or more levels described amplifying circuit；The delay amplifier further includes input stage delay amplification circuit；If input time delay is matched with the setup parameter of amplifying circuit, amplifying circuit itself is used as input stage delay amplification circuit；If input time delay does not match the setup parameter of amplifying circuit, which can be converted to the time delayed signal for being matched with amplifying circuit setup parameter by independent input stage delay amplification circuit.Delay amplification circuit provided by the invention realizes and controls mode, and the flexibility and stability of delay amplifier can be improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, and in particular, to a kind of delay amplifier more particularly to one kind are prolonged
When amplifier circuit design method.
Background technique
With the development of CMOS technology, the supply voltage of chip is being reduced, and the speed of service of transistor is improving.Due to crystalline substance
The body pipe speed of service improves, and the reduction of transmission delay, the minimum interval of digital signal in time is smaller and smaller, therefore when utilization
Between interval transmission data information relative to it is traditional will be more advantageous using voltage amplitude transmitting data information.Time figure turns
Parallel operation (TDC) can be used to handle the delayed data between digital signal, and can replace for handling digital signal amplitude information
Analog-digital converter (ADC).
Typical TDC a kind of time-to-digit converter and time measurement side as disclosed in patent document CN106773613A
Method.Time-to-digit converter includes: no sequential signal generation unit, for generating multiple unordered clock signals: sampling unit, is used
In receiving multiple unordered clock signals and hold survey input signal, using hold survey input signal to multiple unordered clock signals into
Row sampling, and corresponding actual samples result: decoding unit is exported, for receiving actual samples as a result, and according to actual samples
As a result and timing information relevant to the timing of multiple unordered clock signals determine hold survey input signal certain edges thereof along with it is more
Time difference of the certain edges thereof of selected clock signal in a unordered clock signal between surveys the thin of input signal to obtain to hold
Time result；And thick time counting unit, for receiving selected clock signal and holding survey input signal, and with selected clock letter
Number input signal to be measured is counted as counting clock, holds the thick time result for surveying input signal to obtain.
In order to improve the temporal resolution of TDC, need to amplify the delay of previous stage using delay amplifier.Prolong
When amplifier circuit the delay between two signal rising edges or failing edge is amplified, facilitate subsequent conditioning circuit such as TDC root
Data information is extracted according to delayed data, to realize information processing.
Current delay amplifier specifically includes that (1) uses the metastable state effect of S/R latch；(2) it is based on controlled discharge
Principle；(3) it is based on pulse train circuit (pulse train)；(4) it is based on annular oscillation circuit；(5) it is based on Variable delay chain
Deng.The above major design can be divided into two classes, wherein (1) and (2) is the charge and discharge time output and input by change, thus
Realize the amplification output of input time delay, similar Simulation scale-up circuit.Its advantage is that small time delayed signal can be amplified,
The disadvantage is that the poor linearity of amplification, the delay variable range of input are small；Delay amplification circuit based on pulse train, may be implemented
Multiple delays are overlapped, but are difficult to work independently, subsequent TDC circuit is needed to carry out collaboration completion；Based on Variable delay chain
Or the delay amplification circuit of the ring oscillator of changeable frequency, using switching front and back, the delay of delay unit is different or shakes
The amplification that period difference realizes delay is swung, the range for the amplification that is delayed is big, and controllability is good, and anti-PVT changes the features such as performance is good.But
Tradition based on phase inverter its frequency limited of ring oscillator that perhaps NAND gate is constituted in the limitation of phase inverter or NAND gate,
Speed is restricted.It changes simultaneously in the dimension process of phase inverter, adjustable range depends on the adjustable of phase inverter size
Whole range needs to integrate more inverter circuits when requiring multiple amplification factors, to increase adjustable ability, therefore
The alternative that can amplify that is delayed is weaker.
Summary of the invention
For the defects in the prior art, the object of the present invention is to provide a kind of delay amplifiers.
A kind of delay amplifier provided according to the present invention, the delay amplifier includes one or more levels amplifying circuit；
Delay amplification circuit of the level-one based on self-timing oscillation rings is included at least in one or more levels described amplifying circuit；
The delay amplifier further includes input stage delay amplification circuit；If input time delay is matched with the setting of amplifying circuit
Parameter, then amplifying circuit itself is used as input stage delay amplification circuit；If input time delay does not match the setting ginseng of amplifying circuit
Number, then independent input stage delay amplification circuit, which can be converted to the unmatched input time delay, is matched with amplifying circuit setting
The time delayed signal of parameter.
Preferably, the independent input stage delay amplification circuit include delay amplification circuit based on controlled discharge or
S/R latch based on metastable state effect.
Preferably, the delay amplification circuit based on self-timing oscillation rings includes n grades of self-timing oscillation rings, input circuits
And output circuit；
The n grades of self-timing oscillation rings can generate the time delayed signal of n phase, and wherein n is the positive integer of setting；
The input circuit includes control circuit, can receive amplification factor and input as data, each by being decoded as
Self-timing oscillation rings generate two different configurations, and two different configurations make self-timing oscillation ring oscillation in different frequencies
On；
The output circuit can according to the output of self-timing oscillation rings generate output time delayed signal, and control output when
It carves.
Preferably, the control circuit includes that a switching generates control circuit and two selection circuits；The switching produces
Raw control circuit controls oscillation rings and is switched to new working frequency according to the change of input signal in self-timing oscillation rings；The choosing
The control new working frequency can be exported by selecting circuit.
Preferably, the switching generates control circuit, including delays time to control and switching sequence adjustment circuit, can reduce or
Person avoids the delay time error introduced in handoff procedure.
Preferably, 2 n grades of self-timing oscillation rings are connected with control circuit respectively；2 n grades of self-timing vibrations
Swing ring, control circuit is connected with output circuit respectively；The input circuit respectively with 2 n grades of self-timing oscillation rings phases
Connection.
Preferably, the n grades of self-timing oscillation rings, including multistage Miller unit Muller C_element, have oscillation
Frequency Adjustment Function can produce the oscillator signal of different frequency by configuring.
Preferably, the Miller unit Muller C_element can be to initialize under conditions set.
Preferably, in the n grades of self-timing oscillation rings, the connection type of every level-one timing oscillation rings is as follows:
The output Ri of phase inverter is connected to an input of Miller unit in i-stage, another input of Miller unit is
Fi is exported and is connected to the output Ci+1 of next stage for Ci, the input Ri of every level-one phase inverter.
Compared with prior art, the present invention have it is following the utility model has the advantages that
1, delay amplifier provided by the invention has the advantages that simple structure, using flexible, stability are strong；
2, delay amplifier provided by the invention is based on Variable delay ring oscillation principle, for based on phase inverter or
The ring oscillator of NAND gate composition improves, and using the ring oscillator based on self-timing, realizes the promotion of frequency of oscillation,
The adjustment of its frequency of oscillation is more easier, higher for the adjustment capability of delay amplification；
3, delay amplifier provided by the invention, since the stability of self-timing oscillator is more preferable, relative to other annulars
The performance of the anti-PVT fluctuation of oscillator is more preferable.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention,
Objects and advantages will become more apparent upon:
Fig. 1 delay amplifier principle figure
Fig. 2 the application delay amplifier architecture figure
Fig. 3 first order delay amplification circuit schematic diagram
Delay amplification circuit structure chart of the second level Fig. 4 based on self-timing oscillation rings
N grades of self-timing oscillation rings of Fig. 5
Fig. 6 Miller unit Muller C_element
Fig. 7 self-timing oscillation rings realize delay amplification principle
Fig. 8 input circuit
Fig. 9 control circuit
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, several changes and improvements can also be made.These belong to the present invention
Protection scope.
A kind of delay amplifier provided according to the present invention, the delay amplifier includes one or more levels amplifying circuit；
Delay amplification circuit of the level-one based on self-timing oscillation rings is included at least in one or more levels described amplifying circuit；
The delay amplifier further includes input stage delay amplification circuit；If input time delay is matched with the setting of amplifying circuit
Parameter, then amplifying circuit itself is used as input stage delay amplification circuit；If input time delay does not match the setting ginseng of amplifying circuit
Number, then independent input stage delay amplification circuit, which can be converted to the unmatched input time delay, is matched with amplifying circuit setting
The time delayed signal of parameter.
The independent input stage delay amplification circuit includes delay amplification circuit based on controlled discharge or based on Asia
The S/R latch of stable state effect.
The delay amplification circuit based on self-timing oscillation rings includes n grades of self-timing oscillation rings, input circuit and defeated
Circuit out；
The n grades of self-timing oscillation rings can generate the time delayed signal of n phase, and wherein n is the positive integer of setting；
The input circuit includes control circuit, can receive amplification factor and input as data, each by being decoded as
Self-timing oscillation rings generate two different configurations, and two different configurations make self-timing oscillation ring oscillation in different frequencies
On；
The output circuit can according to the output of self-timing oscillation rings generate output time delayed signal, and control output when
It carves.
The control circuit includes that a switching generates control circuit and two selection circuits；The switching generates control electricity
Road controls oscillation rings and is switched to new working frequency according to the change of input signal in self-timing oscillation rings；The selection circuit energy
Enough output controls the new working frequency.
The switching generates control circuit, including delays time to control and switching sequence adjustment circuit, can reduce or avoid
The delay time error introduced in handoff procedure.
2 n grades of self-timing oscillation rings are connected with control circuit respectively；2 n grades of self-timing oscillation rings, control
Circuit processed is connected with output circuit respectively；The input circuit is connected with 2 n grades of self-timing oscillation rings respectively.
The n grades of self-timing oscillation rings, including multistage Miller unit Muller C_element, have frequency of oscillation adjustment
Function can produce the oscillator signal of different frequency by configuring.
The Miller unit Muller C_element can be to initialize under conditions set.
In the n grades of self-timing oscillation rings, the connection type of every level-one timing oscillation rings is as follows:
The output Ri of phase inverter is connected to an input of Miller unit in i-stage, another input of Miller unit is
Fi is exported and is connected to the output Ci+1 of next stage for Ci, the input Ri of every level-one phase inverter.
Further, the present invention relates to the designs of delay amplification circuit, provide a kind of prolonging based on self-timing oscillation rings
When amplifier design philosophy.In an embodiment of the present invention delay amplification circuit include: input circuit, control circuit, from
Timing oscillation loop circuit, output circuit composition.Delay amplification circuit provided by the invention realizes and controls mode, can be improved
The flexibility and stability of delay amplifier.
The present invention is based on Variable delay ring oscillation principles, for the ring oscillation based on phase inverter or NAND gate composition
Device improves, and using the ring oscillator based on self-timing, realizes the promotion of frequency of oscillation, the adjustment of frequency of oscillation is more
It is easy, it is higher for the adjustment capability of delay amplification, since the stability of self-timing oscillator is more preferable, relative to other annular vibrations
The performance for swinging the anti-PVT fluctuation of device is more preferable.The present invention provides a kind of high speed, and delay amplifying power is flexible, and the good delay of stability is put
Big device circuit design method.
The delay amplifier includes level-one or multistage enlarged structure, wherein at least includes that level-one is vibrated based on self-timing
The delay amplification circuit of ring.
Optionally, delay amplifier includes input stage delay amplification circuit, and realization amplifies small delay, with full
The input requirements of the subsequent delay amplification circuit based on self-timing oscillation rings of foot.It is vibrated if input time delay meets based on self-timing
The delay amplification circuit requirement of ring, input stage can be cancelled.
Input stage delay amplification circuit, using the metastable state effect based on S/R latch (when metastable state occurs for S/R latch
When, the time of circuit stability has been postponed, has been input to the delay of output to increase) or delay amplification electricity based on controlled discharge
Road or other delay amplification circuits.Small delay is amplified to subsequent based on self-timing oscillation rings by input stage delay amplification circuit
The acceptable range of delay amplification circuit.
Delay amplification circuit based on self-timing oscillation rings amplifies as the second level or subsequent delay.Work as input time delay
When meeting the delay amplification circuit requirement based on self-timing oscillation rings, the delay amplification circuit based on self-timing oscillation rings can be straight
It connects as input stage.
The multistage delay amplification circuit based on self-timing oscillation rings can be used to be cascaded, to improve times of amplification
Number.
The delay amplification circuit circuit based on self-timing oscillation rings includes two n grades of self-timing oscillation rings, input electricity
Road, control circuit and output circuit composition.
The n grades of self-timing oscillation rings generate the time delayed signal of n phase.
The n grades of self-timing oscillation rings are formed using multistage Muller C_element, have frequency of oscillation adjustment function
Can, it can produce the oscillator signal of different frequency by configuring；
The Muller C_element has function of initializing, and there are many implementations.
Optionally, the n grades of self-timing oscillation rings use array coupled structure, to improve the stability of frequency of oscillation, from
And further increase the stability of delay amplifier.
The input circuit includes control circuit, is inputted wherein can receive amplification factor as data, by being decoded as
Each self-timing oscillation rings generate two different configurations, and two different configurations make self-timing oscillation ring oscillation different
In frequency.Both different configurations make self-timing oscillation ring oscillation over different frequencies, the first configuration can make to make by oneself
When oscillation rings work in cycle T 1, second configuration can with thing self-timing oscillation rings work in cycle T 2, Typical Disposition T2 > T1
The control circuit includes that a switching generates control circuit and two selection circuits.Switching generates control circuit root
According to the change of input signal in self-timing oscillation rings, determine that oscillation rings are switched to new working frequency, new working frequency is selected
Select the output control of circuit.
The switching generates control circuit, including delays time to control and switching sequence adjustment circuit, can reduce or avoid to cut
The delay time error introduced during changing.
The output circuit generates output time delayed signal according to the output of self-timing oscillation rings, and at the time of control output.
Further, with reference to the accompanying drawing, the preferred embodiment of the present invention is illustrated.
If Fig. 2 is a kind of embodiment of delay amplifier, including first order delay amplification circuit U1, second level delay is put
Big circuit U 2 and third level delay amplification circuit U3 composition.
Delay amplifier may include level-one or multistage enlarged structure, such as only include second level delay amplification circuit U2.
Delay amplification circuit proposed by the present invention based on self-timing oscillation rings can be used separately as delay amplifier, can also be with
As the level-one in multistage amplifier circuit.Delay amplification circuit proposed by the present invention based on self-timing oscillation rings, for input
Delay has certain requirement.In the case that input time delay is too small, delay amplifier may include input stage, and realization will be small
Delay amplifies, to meet the input requirements of subsequent delay amplification circuit.It is vibrated if input time delay meets based on self-timing
The delay amplification circuit requirement of ring, input stage can be cancelled.
Fig. 3 is a kind of embodiment of input stage delay amplification circuit, and input stage delay amplification circuit is locked using based on SR
The metastable state effect of storage or based on the delay amplification circuit of controlled discharge or other delay amplification circuits.Fig. 3 delay is put
The advantages of big circuit is can to amplify to small delay, and small delay is amplified to subsequent by input stage delay amplification circuit
The acceptable range of delay amplification circuit.In some cases, the delay amplification circuit based on self-timing oscillation rings is as
Second level or subsequent delay amplification.When amplification factor increases, the multistage delay based on self-timing oscillation rings can be used
Amplifying circuit.
Fig. 4 is a kind of embodiment of the delay amplification circuit based on self-timing oscillation rings in the present invention.Based on self-timing
The delay amplification circuit of oscillation rings includes two n grades of self-timing oscillation rings (U5 and U7), input circuit (U4), control circuit and defeated
Circuit forms out.The structure of third level delay amplification circuit U3 and second level delay amplification circuit U2 can be identical in Fig. 2.
Fig. 5 is a kind of embodiment of timing oscillation rings, and the output of phase inverter is connected to the one of Miller unit in every level-one
A input, the output of phase inverter are Ri, another input of Miller unit is Fi, is exported as Ci.The input of every level-one phase inverter
Ri is connected to the output Ci+1 of next stage.In order to which the original state of self-timing oscillation rings is arranged, in every level-one be added set and
Reset signal, when it is 0 that set signal, which is 1, reset signal, the output of Miller unit is 1.When reset signal is 1, set letter
When number being 0, the output of Miller unit is 0.In self-timing oscillation rings, there are bubble and token.If in i grades of oscillation rings
Output Ci be not equal to upper level output Ci-1, then illustrate that there are a token in i grades.If the output in i grades of oscillation rings
Ci is equal to the output Ci-1 of upper level, then illustrates that there are a bubble in i grades.Self-timing oscillation rings can produce from main oscillations
Need to meet three conditions: (1) oscillation rings series n is more than or equal to 3；(2) quantity of bubble should be more than or equal in oscillation rings
1；(3) quantity of token is a positive even numbers in oscillation rings.
In timing oscillation rings embodiment shown in Fig. 5, carrying out different configurations for every level-one Miller unit can be with
The different frequency of oscillation of parameter.Frequency of oscillation is related with the ratio of bubble in oscillation rings and token, meets relationship.
Wherein T indicates the period of oscillation rings, and the quantity of token is NT, the quantity of bubble is NB, NB+NT=L, DFIt is close
Strangle delay of the unit F to C, DRIt is the delay of Miller unit R to C.The characteristics of self-timing oscillation rings is can be matched by initial
It sets, the number of adjustment bubble and token can adjust the frequency of oscillation of oscillation rings.
Fig. 6 is a kind of embodiment of Miller unit in the present invention, the Muller C_ of multi input in the embodiment of the present invention
Its truth table of element is
Table one, Muller C_element truth table
Its logical expression is:
Muller C_element has function of initializing in the present invention, for adjusting the quantity of bubble and token, vibration
Swing the working frequency of ring.Muller C_element has a different circuit structures, present embodiment only wherein an example, this
Invention is not limited to the implementation method of Fig. 6.
Fig. 7 is to realize delay amplification principle based on self-timing oscillation rings in the present invention, and delay is passed through in two oscillation rings
Different delay series, realizes the enlarging function of delay.
Assuming that the series of self-timing oscillation rings is L grades
Assuming that the front and back cycle of oscillation of self-timing oscillation rings is 1 and A respectively
Assuming that the rising time t0 of A_in
Assuming that the rising time t0+ Δ x of B_in
Assuming that A_in signal has transmitted m grades, it is n grades remaining (m+n=L)
Assuming that B_in has transmitted x grades of m- Δ, x grades of remaining n+ Δ；
At this time carry out cycle of oscillation switching
A_out is (t0)+(m)+(nA) from the time for being input to output
B_out is (t0+ Δ x)+(m- Δ x)+((n+ Δ x) A) from the time for being input to output
B_out-Aout=Δ x A
To realize that output delay is exaggerated A times
Fig. 8 is a kind of embodiment of input circuit in the present invention, and in embodiment, the amplifier that is delayed inputs amplification
Multiple is as data, by generating two different configurations, two different configurations after decoding for each self-timing oscillation rings
Make self-timing oscillation ring oscillation over different frequencies.
In embodiments of the present invention, have four group 4 select 1 mux unit, the number and self-timing oscillation rings of every group of mux unit
Series it is identical.Wherein first group of mux unit is used to control the set signal of first self-timing oscillation rings, second group of mux unit
For controlling the reset signal of first self-timing oscillation rings, third group mux unit is used to control Article 2 self-timing oscillation rings
Set signal, second group of mux unit be used to control the reset signal of Article 2 self-timing oscillation rings.The selection of Mux unit is believed
Number control circuit from delay amplification circuit.
Fig. 9 is a kind of embodiment of control circuit in the present invention, and control circuit includes that a switching generates control circuit
With two selection circuits.Switching generates control circuit according to the change of input signal in self-timing oscillation rings, determines oscillation ring cutting
New working frequency is changed to, new working frequency is controlled by the output of selection circuit.The switching generates control circuit, including prolongs
When control and switching sequence adjustment circuit, can reduce or avoid the delay time error introduced in handoff procedure.
As shown in Fig. 7 arrow, in embodiments of the present invention, the selection of switching is carried out in rising edge or failing edge, to protect
Signal is demonstrate,proved by entire Miller unit, to generate the delay of unit.In embodiment, first that B_in signal is passed through is selected
The output of a Miller unit drives counting unit as clock signal.Counting unit counts to setting value when, generate switching letter
Number.In actual design, the characteristics of according to input time delay, the clock of actuation techniques unit, the self-timing that can pass through from A_in
Some Miller unit in self-timing oscillation rings that some Miller unit or B_in in oscillation rings pass through.
Output circuit in Fig. 4 generates output time delayed signal according to the output of self-timing oscillation rings.In embodiment,
Output selects the afterbody of self-timing oscillation rings as the delay amplified signal of output.In practical applications, prolong to change
The output time of Shi Fang great.It can choose and exported earlier than afterbody, in this case include meter in output control circuit
Number device, the counter can be adjusted by outside, so that it is determined that the output time of delay amplification.
In the description of the present application, it is to be understood that term " on ", "front", "rear", "left", "right", " is erected at "lower"
Directly ", the orientation or positional relationship of the instructions such as "horizontal", "top", "bottom", "inner", "outside" is orientation based on the figure or position
Relationship is set, description the application is merely for convenience of and simplifies description, rather than the device or element of indication or suggestion meaning are necessary
It with specific orientation, is constructed and operated in a specific orientation, therefore should not be understood as the limitation to the application.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make a variety of changes or modify within the scope of the claims, this not shadow
Ring substantive content of the invention.In the absence of conflict, the feature in embodiments herein and embodiment can any phase
Mutually combination.
Claims (9)
1. a kind of delay amplifier, which is characterized in that the delay amplifier includes one or more levels amplifying circuit；The level-one
Or delay amplification circuit of the level-one based on self-timing oscillation rings is included at least in multistage amplifier circuit；
The delay amplifier further includes input stage delay amplification circuit；If input time delay is matched with the setting ginseng of amplifying circuit
Number, then amplifying circuit itself is used as input stage delay amplification circuit；If input time delay does not match the setup parameter of amplifying circuit,
Then independent input stage delay amplification circuit, which can be converted to the unmatched input time delay, is matched with amplifying circuit setting ginseng
Several time delayed signals.
2. delay amplifier according to claim 1, which is characterized in that the independent input stage delay amplification circuit packet
Include the delay amplification circuit based on controlled discharge or the S/R latch based on metastable state effect.
3. delay amplifier according to claim 1, which is characterized in that the delay amplification based on self-timing oscillation rings
Circuit includes n grades of self-timing oscillation rings, input circuit and output circuit；
The n grades of self-timing oscillation rings can generate the time delayed signal of n phase, and wherein n is the positive integer of setting；
The input circuit includes control circuit, can receive amplification factor and input as data, by being decoded as each certainly
Timing oscillation rings generate two different configurations, and two different configurations make self-timing oscillation ring oscillation over different frequencies；
The output circuit can generate output time delayed signal according to the output of self-timing oscillation rings, and at the time of control output.
4. delay amplifier according to claim 3, which is characterized in that the control circuit includes that a switching generates control
Circuit processed and two selection circuits；The switching generates control circuit according to the change of input signal in self-timing oscillation rings, control
Damping swings ring cutting and changes to new working frequency；The selection circuit can export the control new working frequency.
5. delay amplifier according to claim 4, which is characterized in that the switching generates control circuit, including delay
Control and switching sequence adjustment circuit, can reduce or avoid the delay time error introduced in handoff procedure.
6. delay amplifier according to claim 3, which is characterized in that 2 n grades of self-timing oscillation rings respectively with control
Circuit processed is connected；2 n grades of self-timing oscillation rings, the control circuits are connected with output circuit respectively；The input circuit
It is connected respectively with 2 n grades of self-timing oscillation rings.
7. delay amplifier according to claim 3, which is characterized in that the n grades of self-timing oscillation rings, including multistage dense
Unit Muller C_element is strangled, has frequency of oscillation adjustment function, can produce the oscillation letter of different frequency by configuring
Number.
8. delay amplifier according to claim 7, which is characterized in that the Miller unit Muller C_element energy
Enough to initialize under conditions set.
9. delay amplifier according to claim 3, which is characterized in that in the n grades of self-timing oscillation rings, every level-one is fixed
When oscillation rings connection type it is as follows:
The output Ri of phase inverter is connected to an input of Miller unit in i-stage, another input of Miller unit is Fi, defeated
It is out Ci, the input Ri of every level-one phase inverter is connected to the output Ci+1 of next stage.
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