CN110518884B - Time-delay amplifier - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/14—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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Abstract
The invention provides a delay amplifier, which is characterized by comprising a one-stage or multi-stage amplifying circuit; the one-stage or multi-stage amplifying circuit at least comprises a one-stage delay amplifying circuit based on a self-timing oscillation ring; the delay amplifier also comprises an input stage delay amplifying circuit; if the input delay is matched with the set parameters of the amplifying circuit, the amplifying circuit is used as an input stage delay amplifying circuit; if the input delay does not match the set parameters of the amplifying circuit, the independent input stage delay amplifying circuit can convert the unmatched input delay into a delay signal matched with the set parameters of the amplifying circuit. The realization and control mode of the delay amplifying circuit provided by the invention can improve the flexibility and stability of the delay amplifier.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and in particular, to a delay amplifier, and more particularly, to a method for designing a delay amplifier circuit.
Background
With the development of CMOS processes, the power supply voltage of the chip is decreasing and the operating speed of the transistor is increasing. Because the transistor operation speed is increased, the transmission delay is reduced, and the minimum interval of the digital signal in time is smaller and smaller, the data information transmission by using the time interval has more advantages compared with the traditional data information transmission by using the voltage amplitude. A time-to-digital converter (TDC) may be used to process delay information between digital signals and may replace an analog-to-digital converter (ADC) used to process amplitude information of digital signals.
A typical TDC is a time-to-digital converter and a time measurement method as disclosed in patent document CN 106773613A. The time-to-digital converter includes: a chaotic signal generating unit for generating a plurality of chaotic clock signals: the sampling unit is used for receiving a plurality of unordered clock signals and a holding input signal, sampling the plurality of unordered clock signals by using the holding input signal, and outputting a corresponding actual sampling result: a decoding unit for receiving the actual sampling result and determining a time difference between a specific edge of the input signal under test and a specific edge of a selected clock signal among the plurality of unordered clock signals according to the actual sampling result and timing information related to the timings of the plurality of unordered clock signals to obtain a fine time result of the input signal under test; and the coarse time counting unit is used for receiving the selected clock signal and the input signal to be tested, and counting the input signal to be tested by taking the selected clock signal as a counting clock so as to obtain a coarse time result of the input signal to be tested.
In order to improve the time resolution of the TDC, the delay of the previous stage needs to be amplified by using a delay amplifier. The delay amplifier circuit amplifies the delay between the rising edge and the falling edge of the two signals, so that a subsequent circuit such as a TDC can conveniently extract data information according to delay information, and information processing is realized.
Current delay amplifiers mainly comprise: (1) using the metastable effect of the SR latch; (2) based on a controlled discharge principle; (3) pulse train circuit based (pulse train); (4) based on a ring oscillator circuit; (5) based on a variable delay chain, etc. The above main designs can be divided into two types, wherein (1) and (2) realize the amplified output of input delay by changing the charging and discharging time of input and output, and are similar to analog amplifying circuits. The method has the advantages that the method can amplify tiny delay signals, and has the defects of poor linearity of amplification and small variable range of input delay; the delay amplifying circuit based on the pulse sequence can realize superposition of a plurality of delays, but is difficult to work independently and needs a subsequent TDC circuit to complete the cooperation; the delay amplifying circuit based on the variable delay chain or the ring oscillator with variable frequency realizes the amplification of delay by using different delay of the delay unit or different oscillation period before and after switching, and has the characteristics of large delay amplification range, good controllability, good PVT change resistance performance and the like. However, the frequency and speed of the conventional ring oscillator based on inverters or nand gates are limited by the limitations of the inverters or nand gates. Meanwhile, in the process of changing the size of the inverter, the adjustable range depends on the adjustable range of the size of the inverter, when multiple amplification factors are required, more inverter circuits need to be integrated to increase the adjustable capacity, and therefore the selectivity of time delay capable of being amplified is weaker.
Disclosure of Invention
In view of the shortcomings of the prior art, it is an object of the present invention to provide a delay amplifier.
According to the delay amplifier provided by the invention, the delay amplifier comprises a one-stage or multi-stage amplifying circuit; the one-stage or multi-stage amplifying circuit at least comprises a one-stage delay amplifying circuit based on a self-timing oscillation ring;
the delay amplifier also comprises an input stage delay amplifying circuit; if the input delay is matched with the set parameters of the amplifying circuit, the amplifying circuit is used as an input stage delay amplifying circuit; if the input delay does not match the set parameters of the amplifying circuit, the independent input stage delay amplifying circuit can convert the unmatched input delay into a delay signal matched with the set parameters of the amplifying circuit.
Preferably, the independent input stage delay amplifying circuit comprises a controlled discharge based delay amplifying circuit or a metastable effect based SR latch.
Preferably, the self-timing oscillation ring based delay amplifying circuit comprises an n-stage self-timing oscillation ring, an input circuit and an output circuit;
the n-stage self-timing oscillation ring can generate n phase delay signals, wherein n is a set positive integer;
the input circuit comprises a control circuit, can receive amplification factors as data input, and generates two different configurations for each self-timing oscillation ring through decoding, wherein the two different configurations enable the self-timing oscillation ring to oscillate at different frequencies;
the output circuit can generate an output delay signal according to the output of the self-timing oscillation ring and control the output time.
Preferably, the control circuit includes a switching generation control circuit and two selection circuits; the switching generation control circuit controls the oscillation ring to be switched to a new working frequency according to the change of the input signal in the self-timing oscillation ring; the selection circuit is capable of controlling the new operating frequency.
Preferably, the switching generation control circuit comprises a delay control and switching timing adjustment circuit, which can reduce or avoid delay errors introduced in the switching process.
Preferably, 2 n-stage self-timing oscillation rings are respectively connected with the control circuit; the 2 n-stage self-timing oscillation rings and the control circuit are respectively connected with an output circuit; the input circuit is respectively connected with the 2 n-stage self-timing oscillation rings.
Preferably, the n-stage self-timing oscillation ring comprises a multi-stage miller C _ element, and has an oscillation frequency adjusting function, and oscillation signals with different frequencies can be generated through configuration.
Preferably, the miller unit Muller C _ element can be initialized under set conditions.
Preferably, in the n-stage self-timed oscillation ring, each stage of the timed oscillation ring is connected as follows:
the output Ri of the inverter in the ith stage is connected to one input of the miller cell, the other input of the miller cell is Fi, the output is Ci, and the input Ri of the inverter in each stage is connected to the output Ci +1 of the next stage.
Compared with the prior art, the invention has the following beneficial effects:
1. the delay amplifier provided by the invention has the advantages of simple structure, flexible use and strong stability;
2. the delay amplifier provided by the invention is based on a variable delay ring oscillation principle, improves a ring oscillator formed by an inverter or a NAND gate, and realizes the promotion of oscillation frequency by adopting the ring oscillator based on self-timing, the adjustment of the oscillation frequency is easier, and the adjustment capability of delay amplification is higher;
3. the delay amplifier provided by the invention has better stability and better PVT fluctuation resistance compared with other ring oscillators.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a schematic diagram of a delay amplifier
FIG. 2 is a block diagram of a delay amplifier according to the present application
FIG. 3 is a schematic diagram of a first stage delay amplifier circuit
FIG. 4 is a diagram of a second stage of self-timed oscillation ring-based delay amplifier circuit
FIG. 5 n-stage self-timed oscillation ring
FIG. 6 Miller Unit Muller C _ element
FIG. 7 is a schematic diagram of realizing time-delay amplification of self-timing oscillation ring
FIG. 8 input circuit
FIG. 9 control circuit
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
According to the delay amplifier provided by the invention, the delay amplifier comprises a one-stage or multi-stage amplifying circuit; the one-stage or multi-stage amplifying circuit at least comprises a one-stage delay amplifying circuit based on a self-timing oscillation ring;
the delay amplifier also comprises an input stage delay amplifying circuit; if the input delay is matched with the set parameters of the amplifying circuit, the amplifying circuit is used as an input stage delay amplifying circuit; if the input delay does not match the set parameters of the amplifying circuit, the independent input stage delay amplifying circuit can convert the unmatched input delay into a delay signal matched with the set parameters of the amplifying circuit.
The independent input stage delay amplifying circuit comprises a delay amplifying circuit based on controlled discharge or an SR latch based on metastable state effect.
The delay amplifying circuit based on the self-timing oscillation ring comprises an n-stage self-timing oscillation ring, an input circuit and an output circuit;
the n-stage self-timing oscillation ring can generate n phase delay signals, wherein n is a set positive integer;
the input circuit comprises a control circuit, can receive amplification factors as data input, and generates two different configurations for each self-timing oscillation ring through decoding, wherein the two different configurations enable the self-timing oscillation ring to oscillate at different frequencies;
the output circuit can generate an output delay signal according to the output of the self-timing oscillation ring and control the output time.
The control circuit comprises a switching generation control circuit and two selection circuits; the switching generation control circuit controls the oscillation ring to be switched to a new working frequency according to the change of the input signal in the self-timing oscillation ring; the selection circuit is capable of controlling the new operating frequency.
The switching generation control circuit comprises a delay control circuit and a switching time sequence adjusting circuit, and can reduce or avoid delay errors introduced in the switching process.
The 2 n-stage self-timing oscillation rings are respectively connected with a control circuit; the 2 n-stage self-timing oscillation rings and the control circuit are respectively connected with an output circuit; the input circuit is respectively connected with the 2 n-stage self-timing oscillation rings.
The n-stage self-timing oscillation ring comprises a multi-stage Miller unit Muller C _ element, has an oscillation frequency adjusting function, and can generate oscillation signals with different frequencies through configuration.
The miller cell Muller C _ element can be initialized under set conditions.
In the n-stage self-timing oscillation ring, each stage of timing oscillation ring is connected in the following mode:
the output Ri of the inverter in the ith stage is connected to one input of the miller cell, the other input of the miller cell is Fi, the output is Ci, and the input Ri of the inverter in each stage is connected to the output Ci +1 of the next stage.
Further, the invention relates to the design of a delay amplifying circuit, and provides a design method of a delay amplifier based on a self-timing oscillation ring. In one embodiment of the present invention, a delay amplifying circuit includes: the self-timing oscillation circuit comprises an input circuit, a control circuit, a self-timing oscillation ring circuit and an output circuit. The realization and control mode of the delay amplifying circuit provided by the invention can improve the flexibility and stability of the delay amplifier.
The invention is based on the variable time-delay ring oscillation principle, improves the ring oscillator based on the phase inverter or the NAND gate, adopts the ring oscillator based on self-timing to realize the promotion of the oscillation frequency, has easier adjustment of the oscillation frequency and higher adjustment capability of time-delay amplification, and has better PVT fluctuation resistance compared with other ring oscillators due to better stability of the self-timing oscillator. The invention provides a design method of a delay amplifier circuit with high speed, flexible delay amplification capacity and good stability.
The delay amplifier comprises a one-stage or multi-stage amplification structure, wherein at least one stage of delay amplification circuit based on a self-timing oscillation ring is included.
Optionally, the delay amplifier includes an input stage delay amplifying circuit, and the amplification of the slight delay is realized to meet the input requirement of the subsequent delay amplifying circuit based on the self-timing oscillation ring. The input stage can be eliminated if the input delay meets the requirements of the self-timed oscillation ring-based delay amplification circuit.
The input stage delay amplifying circuit uses a metastable state effect based on an SR latch (when the SR latch generates the metastable state, the circuit is delayed from stabilizing, so that the delay of input to output is increased) or a delay amplifying circuit based on controlled discharge or other delay amplifying circuits. The input stage delay amplifying circuit amplifies the small delay to a range which can be accepted by a subsequent delay amplifying circuit based on a self-timing oscillation ring.
And the time delay amplifying circuit based on the self-timing oscillation ring is used as a second stage or subsequent time delay amplification. When the input delay meets the requirement of the self-timing oscillation ring-based delay amplifying circuit, the self-timing oscillation ring-based delay amplifying circuit can be directly used as an input stage.
Multistage delay amplifying circuits based on self-timing oscillation rings can be used for cascading so as to improve the amplification factor.
The delay amplifying circuit based on the self-timing oscillation ring comprises two n-stage self-timing oscillation rings, an input circuit, a control circuit and an output circuit.
And the n-stage self-timing oscillation ring generates delay signals of n phases.
The n-stage self-timing oscillation ring is composed of multiple stages of Muller C _ elements, has an oscillation frequency adjusting function, and can generate oscillation signals with different frequencies through configuration;
the Muller C _ element has an initialization function and has a plurality of implementation modes.
Optionally, the n-stage self-timing oscillation ring adopts an array coupling structure to improve stability of oscillation frequency, so as to further improve stability of the delay amplifier.
The input circuit includes a control circuit which can accept the amplification as a data input and produce two different configurations for each self-timed oscillation loop by decoding, the two different configurations causing the self-timed oscillation loop to oscillate at different frequencies. The two different configurations oscillate the self-timed oscillator loop at different frequencies, the first configuration operating the self-timed oscillator loop at a period T1, the second configuration operating the self-timed oscillator loop at a period T2, with T2> T1 being typical
The control circuit comprises a switching generation control circuit and two selection circuits. The switching generation control circuit determines that the oscillation ring is switched to a new working frequency according to the change of the input signal in the self-timing oscillation ring, and the new working frequency is controlled by the output of the selection circuit.
The switching generation control circuit comprises a delay control circuit and a switching time sequence adjusting circuit, and delay errors introduced in the switching process can be reduced or avoided.
And the output circuit generates an output delay signal according to the output of the self-timing oscillation ring and controls the output time.
Further, preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
Fig. 2 shows an embodiment of the delay amplifier, which includes a first stage delay amplifying circuit U1, a second stage delay amplifying circuit U2, and a third stage delay amplifying circuit U3.
The delay amplifier may comprise one or more stages of amplification structures, such as only the second stage delay amplifying circuit U2. The delay amplifying circuit based on the self-timing oscillation ring can be independently used as a delay amplifier and can also be used as one stage of a multi-stage amplifying circuit. The delay amplifying circuit based on the self-timing oscillation ring has certain requirements on input delay. When the input delay is too small, the delay amplifier may include an input stage to amplify the small delay to meet the input requirement of the subsequent delay amplifying circuit. The input stage can be eliminated if the input delay meets the requirements of the self-timed oscillation ring-based delay amplification circuit.
Fig. 3 is an embodiment of an input stage delay amplifying circuit using a metastable effect based on SR latches or a controlled discharge based delay amplifying circuit or other delay amplifying circuits. The delay amplifying circuit of fig. 3 has the advantage that a small delay can be amplified, and the input stage delay amplifying circuit amplifies the small delay to a range acceptable by a subsequent delay amplifying circuit. In some cases, a self-timed oscillation loop based delay amplification circuit is used as a second stage or subsequent delay amplification. When the amplification factor is increased, a multi-stage delay amplification circuit based on a self-timing oscillation ring can be used.
Fig. 4 is an embodiment of the delay amplifying circuit based on the self-timing oscillation loop in the invention. The delay amplifying circuit based on the self-timing oscillation ring comprises two n-stage self-timing oscillation rings (U5 and U7), an input circuit (U4), a control circuit and an output circuit. The third stage delay amplifying circuit U3 and the second stage delay amplifying circuit U2 in fig. 2 may have the same structure.
Fig. 5 is an embodiment of a timed oscillation ring, where the output of the inverter in each stage is connected to one input of the miller cell, the output of the inverter is Ri, the other input of the miller cell is Fi, and the output is Ci. The input Ri of the inverter of each stage is connected to the output Ci +1 of the next stage. In order to set the initial state of the self-timed oscillation loop, set and reset signals are added to each stage, and when the set signal is 1 and the reset signal is 0, the output of the miller cell is 1. When the reset signal is 1 and the set signal is 0, the output of the miller cell is 0. In the self-timed oscillation ring, there are bubbles and tokens. If the output Ci in the i-stage of the ring is not equal to the output Ci-1 of the previous stage, it indicates that there is a token in the i-stage. If the output Ci of the i stage of the oscillation ring is equal to the output Ci-1 of the previous stage, it indicates that there is a bubble in the i stage. The self-timing oscillation ring can generate autonomous oscillation and meets three conditions: (1) the number n of the oscillating ring stages is more than or equal to 3; (2) the number of bubbles in the oscillation ring should be more than or equal to 1; (3) the number of tokens in the oscillation ring is a positive even number.
In the timed oscillation ring embodiment shown in fig. 5, different configurations for each stage of miller cells may be parameterized by different oscillation frequencies. The oscillation frequency is related to the ratio of bubble to token in the oscillation ring, and the following relation is satisfied.
Where T denotes the period of the oscillation ring and the number of tokens is NTThe number of bubbles is NB，NB+NT＝L，DFIs the delay of the Miller units F to C, DRIs the delay of the miller cells R to C. The self-timing oscillation ring is characterized in that the oscillation frequency of the oscillation ring can be adjusted by adjusting the number of bubbles and tokens through initial configuration.
FIG. 6 is a diagram of an embodiment of a Miller unit according to the present invention, in which a truth table of a multi-input Muller C _ element is shown as
TABLE I Muller C _ element truth table
The logic expression is as follows:
the Muller C _ element has an initialization function and is used for adjusting the number of bubbles and tokens and the working frequency of an oscillation ring. The Muller C _ element has different circuit structures, and this embodiment is only an example, and the present invention is not limited to the implementation method of fig. 6.
Fig. 7 shows that the delay amplification principle is realized based on the self-timing oscillation ring, and the delay is realized in two oscillation rings through different delay stages.
Assuming that the number of stages of the self-timed oscillation ring is L-stage
Suppose the front and back oscillation periods of the self-timed oscillation ring are 1 and A respectively
Assume rising edge time t0 of A _ in
Suppose the rising edge time t0+ Δ x of B _ in
Suppose the a _ in signal has passed m stages, the remaining n stages (m + n ═ L)
Suppose B _ in has delivered m- Δ x stages, leaving n + Δ x stages;
at this time, the oscillation period is switched
The time from input to output of A _ out is (t0) + (m) + (nA)
The time from input to output of B _ out is (t0+ Δ x) + (m- Δ x) + ((n + Δ x) A)
B_out-Aout＝Δx A
Thereby realizing output delay amplification by A times
Fig. 8 is an embodiment of the input circuit of the present invention, in which the input amplification of the delay amplifier is used as data, and two different configurations are generated for each self-timed oscillation ring after decoding, and the two different configurations cause the self-timed oscillation ring to oscillate at different frequencies.
In an embodiment of the present invention, there are four sets of 1 out of 4 mux units, each set having the same number of mux units as the number of stages of the self-timed oscillation ring. Wherein the first set of mux units is used to control the set signal of the first self-timed oscillation ring, the second set of mux units is used to control the reset signal of the first self-timed oscillation ring, the third set of mux units is used to control the set signal of the second self-timed oscillation ring, and the second set of mux units is used to control the reset signal of the second self-timed oscillation ring. The selection signal of the Mux unit comes from a control circuit of the time delay amplifying circuit.
Fig. 9 is an embodiment of a control circuit according to the present invention, the control circuit including a switch generation control circuit and two selection circuits. The switching generation control circuit determines that the oscillation ring is switched to a new working frequency according to the change of the input signal in the self-timing oscillation ring, and the new working frequency is controlled by the output of the selection circuit. The switching generation control circuit comprises a delay control circuit and a switching time sequence adjusting circuit, and delay errors introduced in the switching process can be reduced or avoided.
In an embodiment of the present invention, the selection of switching is done on either the rising or falling edge to ensure that the signal passes through the entire miller cell, thereby creating a unit delay, as indicated by the arrows in fig. 7. In an embodiment, the output of the first miller cell through which the B _ in signal passes is selected as the clock signal to drive the counting unit. The counting unit generates a switching signal when counting to a set value. In practical design, according to the characteristics of input delay, the clock driving the technical unit can pass through a certain miller unit in the self-timing oscillation ring through A _ in or pass through B _ in.
The output circuit of fig. 4 generates an output delay signal based on the output of the self-timed oscillator loop. In an embodiment, its output selects the last stage of the self-timed oscillation loop as the delayed amplified signal of the output. In practical applications, the amplified output timing is delayed for changing. Optionally, the output is performed earlier than the last stage, in which case the output control circuit includes a counter that can be externally adjusted to determine the output time of the delay amplification.
In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (8)
1. A delay amplifier, characterized in that the delay amplifier comprises one or more stages of amplifying circuits; the one-stage or multi-stage amplifying circuit at least comprises a one-stage delay amplifying circuit based on a self-timing oscillation ring;
the delay amplifier also comprises an input stage delay amplifying circuit; if the input delay is matched with the set parameters of the amplifying circuit, the amplifying circuit is used as an input stage delay amplifying circuit; if the input delay is not matched with the set parameters of the amplifying circuit, the independent input stage delay amplifying circuit can convert the unmatched input delay into a delay signal matched with the set parameters of the amplifying circuit;
the delay amplifying circuit based on the self-timing oscillation ring comprises an n-stage self-timing oscillation ring, an input circuit and an output circuit;
the n-stage self-timing oscillation ring can generate n phase delay signals, wherein n is a set positive integer;
the input circuit comprises a control circuit, can receive amplification factors as data input, and generates two different configurations for each self-timing oscillation ring through decoding, wherein the two different configurations enable the self-timing oscillation ring to oscillate at different frequencies;
the output circuit can generate an output delay signal according to the output of the self-timing oscillation ring and control the output time.
2. The delay amplifier of claim 1, wherein the independent input stage delay amplifying circuit comprises a controlled discharge based delay amplifying circuit or a metastable effect based SR latch.
3. The delay amplifier of claim 1, wherein the control circuit comprises a switching generation control circuit and two selection circuits; the switching generation control circuit controls the oscillation ring to be switched to a new working frequency according to the change of the input signal in the self-timing oscillation ring; the selection circuit is capable of controlling the new operating frequency.
4. The delay amplifier of claim 3, wherein the switch generation control circuit comprises a delay control and switch timing adjustment circuit.
5. The delay amplifier of claim 1, wherein 2 of said n-stage self-timed oscillator loops are each connected to a control circuit; the 2 n-stage self-timing oscillation rings and the control circuit are respectively connected with an output circuit; the input circuit is respectively connected with the 2 n-stage self-timing oscillation rings.
6. The delay amplifier of claim 1, wherein the n-stage self-timed oscillation loop comprises a multi-stage Miller unit Muller C _ element, and has an oscillation frequency adjusting function, and the n-stage self-timed oscillation loop can generate oscillation signals with different frequencies by configuration.
7. Delay amplifier according to claim 6, characterized in that the Miller unit Muller C _ element can be initialized under set conditions.
8. The delay amplifier of claim 6, wherein the n-stage self-timed oscillation ring, each stage of the timed oscillation ring is connected as follows:
output R of inverter in i-th stageiConnected to one input of the Miller cell, the other input of the Miller cell being FiThe output is CiInput R of each stage of inverteriOutput C connected to the next stagei+1。
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| CN201910769767.3A CN110518884B (en) | 2019-08-20 | 2019-08-20 | Time-delay amplifier |
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| CN112486008B (en) * | 2020-12-11 | 2021-12-07 | 上海交通大学 | Resolution-adjustable time measurement statistical system and method based on TDC |
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| CN105827237A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Time delay circuit and voltage-controlled oscillator |
| CN106656116A (en) * | 2016-12-27 | 2017-05-10 | 上海交通大学 | High-linearity phase interpolator |
| CN109787619A (en) * | 2019-02-26 | 2019-05-21 | 上海交通大学 | Multiphase clock generation circuit |
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| US8436670B2 (en) * | 2011-01-13 | 2013-05-07 | Micron Technology, Inc. | Power supply induced signal jitter compensation |
| CN103902930B (en) * | 2014-03-10 | 2016-09-07 | 杭州晟元数据安全技术股份有限公司 | The unclonable functional circuit structure of physics based on ring oscillator |
| CN104101827B (en) * | 2014-06-25 | 2016-08-31 | 东南大学 | A kind of process corner detection circuit based on self-timing oscillation rings |
| JP6699073B2 (en) * | 2016-03-25 | 2020-05-27 | ヤマハ株式会社 | Self-excited class D amplifier |
| CN109933127A (en) * | 2019-03-07 | 2019-06-25 | 中科亿海微电子科技（苏州）有限公司 | Programmable delay cellular construction |
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| CN105827237A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Time delay circuit and voltage-controlled oscillator |
| CN106656116A (en) * | 2016-12-27 | 2017-05-10 | 上海交通大学 | High-linearity phase interpolator |
| CN109787619A (en) * | 2019-02-26 | 2019-05-21 | 上海交通大学 | Multiphase clock generation circuit |
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