CN109787619A - Multiphase clock generation circuit - Google Patents
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Abstract
The present invention provides a kind of multiphase clock generation circuits, comprising: m n grades of self-timing oscillation rings；Loop coupling is vibrated in the m n grades of self-timings.The advantages of the present invention is based on digital designs, good with the migration between technique, the comprehensive performance of area, power consumption and anti-PVT characteristic, and have high resolution, the anti-noise sound intensity.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, and in particular, to multiphase clock generation circuit.
Background technique
A high-resolution multi-phase clock signal generation circuit is needed in many communications or signal processing system, such as high speed
Composite score clock module, high precision measurement and the measuring circuit etc. in string simultaneously/parallel-to-serial converter, phaselocked loop in interconnection.
Generating multiphase clock at present, there are mainly three types of methods: (1) based on the multiphase clock generation circuit of chain of inverters, mainly asking
Topic is that power consumption is big, resolution ratio is low；(2) voltage controlled oscillator based on phase interpolator can multiphase higher with output resolution ratio when
Clock, but it is more sensitive for the variation of technique, voltage and temperature (PVT)；(3) based on the voltage controlled oscillator VCO of feedback, Ke Yiti
High phase resolution ratio, and there is better anti-PVT variation characteristic, but the voltage controlled oscillator based on feedback, belong to analog circuit,
The portability of technology room is poor, and circuit area and power consumption are big.
Patent document CN1897583A (application number: 200610043016.6) is disclosed a kind of for high-speed transceiver reception
The multiphase orthogonal clock generation circuit of the completion clock and data recovery at end, including eight phase-interpolations and selection circuit, a phase
Position selection circuit.The reference clock of 16 phase phase intervals Π/8 exported PLL/VCO is divided into 8 groups by phase-interpolation and selection circuit
Phase-interpolation is carried out, the clock of 32 phase phase intervals Π/16 is generated and phase is carried out by control signal SLC1_I, I=1,2,3,4
Position selection, generates two groups of 8 phase, phase intervals are the clock of Π/2 in group, wherein CLK1,3,5,7, CLK2,4,6,8 according to
Successively effective sequence phase is incremented by respectively, successively decreases by SLC1_1, SLC1_2, SLC1_3, SLC1_4, and step-length is Π/16.Phase choosing
It selects circuit and selects appropriate phase: SLC2_ from multiphase orthogonal clock under the action of controlling signal SLC2_J, J=1,2, L, 6
5 it is effective when, export clock signal clk I phase between the Π of Π~2, successively according to SLC2_1, SLC2_2, SLC2_3, SLC2_4
Effective sequence phase taper, step-length are Π/4；When SLC2_6 is effective, the phase of CLKI between 0~Π, according to SLC2_1,
Successively effective sequence phase is incremented by by SLC2_2, SLC2_3, SLC2_4, and step-length is Π/4.
Summary of the invention
For the defects in the prior art, the object of the present invention is to provide a kind of multiphase clock generation circuits.
A kind of multiphase clock generation circuit provided according to the present invention, comprising:
M n grades of self-timing oscillation rings；
Loop coupling is vibrated in the m n grades of self-timings.
Preferably, the n grades of self-timing oscillation rings include:
The Miller unit Muller C_element of n multi input；
The Miller unit Muller C_element of the multi input includes: the input of multiple groups identical function, wherein at least
One group is used to generate oscillator signal, and at least one set is used for and loop coupling is vibrated in other n grades of self-timing.
Preferably, the Miller unit Muller C_element of the multi input:
The Miller unit Muller C_element logical expression of multi input is as follows:
F is the input of n group identical function: F1=F2=....=Fn
R is the input of n group identical function: R1=R2=....=Rn
Wherein,
SET indicates the SET signal of the Miller unit Muller C_element of multi input；
RESET indicates the RESET signal of the Miller unit Muller C_element of multi input；
C indicates the output of the Miller unit Muller C_element of multi input.
Preferably, the input of at least one set of identical function:
With other one or more Millers in addition to the Miller unit of this multi input in the n grades of self-timing oscillation rings
The output of unit Muller C_element is connected, and makes the Miller unit Muller of n multi input in n grades of self-timing oscillation rings
C_element connection.
Preferably, the input of at least one set of identical function:
It shakes with other n grades of self-timing in addition to this n grades of self-timing oscillation rings in the m n grades of self-timing oscillation rings
The output for swinging the Miller unit Muller C_element of one or more multi inputs in ring is connected, and makes m n grades of self-timing vibration
Swing loop coupling.
Preferably, at least one set of input vibrates loop coupling with other n grades of self-timing:
At least one set input is connected from the output of different Miller unit Muller C_element.
Preferably, the Miller unit Muller C_element of the multi input provides an initialization and configuration circuit；
The initialization and configuration circuit carry out initial configuration to n grades of self-timing oscillation rings, configure self-timing oscillation rings
Generate different frequency of oscillation and waveform.
Preferably, the n grades of self-timing oscillation rings generate n clock phase；
The m n grades of self-timings oscillation loop coupling generates m × n clock phase.
Preferably, further includes:
By adjusting the series n of the self-timing oscillation rings and quantity m of self-timing oscillation rings, different clock phases is generated
Position.
Preferably, the series n of the self-timing oscillation rings is the positive integer more than or equal to 3；
The quantity m of self-timing oscillation rings is the positive integer more than or equal to 2.
Compared with prior art, the present invention have it is following the utility model has the advantages that
It is good with the migration between technique the present invention is based on digital design, area, power consumption and anti-PVT characteristic it is comprehensive
Performance is closed, and there is high resolution, the advantages of the anti-noise sound intensity
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention,
Objects and advantages will become more apparent upon:
Fig. 1 is the structural schematic diagram of high-resolution multiphase clock generation circuit provided by the invention.
Fig. 2 is self-timing oscillation rings schematic diagram provided by the invention.
Fig. 3 is the Miller cellular construction schematic diagram of multi input provided by the invention.
Fig. 4 is a kind of embodiment schematic diagram of the Miller unit of multi input provided by the invention.
Fig. 5 is the coupling schematic diagram of high-resolution multiphase clock generation circuit provided by the invention.
Fig. 6 is the emulation schematic diagram of the coupling of high-resolution multiphase clock generation circuit provided by the invention.
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, several changes and improvements can also be made.These belong to the present invention
Protection scope.
A kind of multiphase clock generation circuit provided according to the present invention, comprising:
M n grades of self-timing oscillation rings；
Loop coupling is vibrated in the m n grades of self-timings.
Specifically, the n grades of self-timing oscillation rings include:
The Miller unit Muller C_element of n multi input；
The Miller unit Muller C_element of the multi input includes: the input of multiple groups identical function, wherein at least
One group is used to generate oscillator signal, and at least one set is used for and loop coupling is vibrated in other n grades of self-timing.
Specifically, the Miller unit Muller C_element of the multi input:
The Miller unit Muller C_element logical expression of multi input is as follows:
F is the input of n group identical function: F1=F2=....=Fn
R is the input of n group identical function: R1=R2=....=Rn
Wherein,
SET indicates the SET signal of the Miller unit Muller C_element of multi input；
RESET indicates the RESET signal of the Miller unit Muller C_element of multi input；
C indicates the output of the Miller unit Muller C_element of multi input.
Specifically, the input of at least one set of identical function:
With other one or more Millers in addition to the Miller unit of this multi input in the n grades of self-timing oscillation rings
The output of unit Muller C_element is connected, and makes the Miller unit Muller of n multi input in n grades of self-timing oscillation rings
C_element connection.
Specifically, the input of at least one set of identical function:
It shakes with other n grades of self-timing in addition to this n grades of self-timing oscillation rings in the m n grades of self-timing oscillation rings
The output for swinging the Miller unit Muller C_element of one or more multi inputs in ring is connected, and makes m n grades of self-timing vibration
Swing loop coupling.
Specifically, at least one set of input vibrates loop coupling with other n grades of self-timing:
At least one set input is connected from the output of different Miller unit Muller C_element.
Specifically, the Miller unit Muller C_element of the multi input provides an initialization and configuration circuit；
The initialization and configuration circuit carry out initial configuration to n grades of self-timing oscillation rings, configure self-timing oscillation rings
Generate different frequency of oscillation and waveform.
Specifically, the n grades of self-timing oscillation rings generate n clock phase；
The m n grades of self-timings oscillation loop coupling generates m × n clock phase.
Specifically, further includes:
By adjusting the series n of the self-timing oscillation rings and quantity m of self-timing oscillation rings, different clock phases is generated
Position.
Specifically, the series n of the self-timing oscillation rings is the positive integer more than or equal to 3；
The quantity m of self-timing oscillation rings is the positive integer more than or equal to 2.
Below by preference, the present invention is more specifically illustrated.
Preference 1:
For the resolution ratio of Current high resolution multiphase clock generation circuit, power consumption, circuit area and anti-PVT characteristic etc.
Problems, by the present invention in that generating high-resolution clock with a kind of digital coupling self-timing oscillation rings, this is set
Meter is based on digital design, good with the migration between technique, the good combination property of area, power consumption and anti-PVT characteristic, and
With high resolution, the features such as the anti-noise sound intensity.
The present invention provides a kind of design method of high-resolution multiphase clock generation circuit.Multiphase clock generation circuit
It is coupled and is generated by m n grades of self-timing oscillation rings (Self-timed Ring Oscillator, STRO).Wherein m indicate n grade oneself
The number of timing oscillation rings, n indicate the series of self-timing oscillation rings.The number of self-timing oscillation rings and the grade of self-timing oscillation rings
Number is adjustable, to generate different phases.Different using the coupled modes of RLC from other, multiphase clock of the invention is logical
Different n grade self-timing oscillation loop coupling is crossed to generate.N grades of self-timing oscillation rings can produce n clock phase, will by coupling
M independent self-timing oscillation rings are synchronous, and coupling generates m × n clock phase, to realize high-resolution clock.
The n grades of self-timing oscillation rings generate multi-phase clock signal.N grades of self-timing oscillation rings provided by the invention,
Series is adjustable, to generate the clock signal of different frequency of oscillation and out of phase.Self-timing vibration provided by the invention
The working condition of oscillation rings can be controlled by the way that the original state of oscillation rings is arranged by swinging ring.Preferably, oscillation rings should be set as
Uniform communication mode obtains higher clock frequency, and generates the clock signal of even phase.
The n grades of self-timing oscillation rings are made of the Miller unit Muller C_element of n multi input.
The Miller unit Muller C_element of the multi input, is made of the input of multiple groups identical function, wherein extremely
Few one group for generating oscillator signal, at least one set of coupling for other self-timing oscillation rings.
Coupling between the self-timing oscillation rings is realized by multi input Miller unit Muller C_element.It is more
The input signal in Miller unit Muller C_element including multiple identical functions is inputted, by the difference of these identical functions
Input is connected to the output of different Miller unit Muller C_element, thus realize the delay coupling of circuit with it is synchronous.
Such as in m multi input Miller unit Muller C_element (F0 ... Fn, R0 ... Rn, SET, RESET), wherein
F0, the R0 of each Miller unit Muller C_element is interengageable for generating one m grades of self-timing oscillation rings,
But F1 and R1 is used for and the F1 and R1 of another self-oscillation ring are attached, to generate coupling effect.As shown in Figure 5, C1/
The corresponding Miller unit Muller C_element of C2/C3 forms a self-oscillation ring, the corresponding Miller unit of C4/C5/C6
Muller C_element forms a self-oscillation ring, and the F1/R1 of these units of C4/C5/C6 is connected respectively to C4/C5/C6 (vibration
Swing inside ring), and F2/R2 is then coupled to the self-oscillation ring (another oscillation rings) of C1/C2/C3 composition.
Traditional Miller unit includes the signals such as F, R, RESET, SET and C, and truth table is as shown in Table 1, wherein F, R,
SET, RESET are inputs, and C is output.Present invention firstly provides a kind of multi input Miller unit concepts.Its main feature is that input includes
F0 ... Fn, R0 ... Rn, SET, RESET and C signal.Wherein F0 ... Fn realizes identity logic function, but has n different inputs.
R0 ... Rn realizes identity logic function, but has n different inputs.
Muller C_element is unit relatively common in an asynchronous circuit, and most basic unit includes two defeated
Enter and exported with one, as shown in the table
| F | R | C |
| 0 | 0 | Previous C |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | Previous C |
Its logical expression is: C=！(F^R)&C-1+(F^R)&F
Or another way, as shown in the table
| F | R | C |
| 0 | 0 | 0 |
| 0 | 1 | Previous C |
| 1 | 0 | Previous C |
| 1 | 1 | 1 |
Its logical expression is: C=(F^R) &C-1+！(F^R)&F
Muller C_element in use can have the port Reset and Set, in the first manner for, increase
After Reset and Set signal, truth table is as follows:
Its logical expression is:
The characteristics of multi input Muller C_element in the present invention, is that it has multiple F and multiple R input, true value
Table is
Its logical expression is:
Wherein require F0=F1=....=Fn, R0=R1=....=Rn
The Miller unit Muller C_element of the multi input provides an initialization and configuration circuit, be used to for
N grades of self-timing oscillation rings carry out initial configuration, generate different frequency of oscillation and oscillation wave for configuring self-timing oscillation rings
Shape.
Preference 2:
Fig. 1 is the structural schematic diagram of high-resolution multiphase clock generation circuit of the invention, and multiphase clock generates electricity
Road includes m n grades of self-timing oscillation loop circuit.To form high-resolution more by intercoupling for M n grades of self-timing oscillation loop circuit
Phase clock generation circuit.Wherein the number of m and n is adjusted according to the number of required clock phase and the frequency of clock.
Fig. 2 is the self-timing oscillation rings in the present invention, by the Miller unit Muller C_element group of n grades of multi inputs
At composition, wherein n is greater than the positive integer equal to 3.In the self-timing of multi input Miller unit Muller C_element composition
In oscillation rings, according to the principle of self-timing circuit, there are bubble and token two states.Wherein, token is defined as vibrating
Output C in i grades of ringiNot equal to the output C of upper leveli-1State.Bubble is defined as the output C in i grades of oscillation ringsiIt is equal to
The output C of upper leveli-1State.When meeting three conditions, self-timing oscillation rings be can produce from main oscillations.These three
Part is respectively: (1) oscillation rings series n is more than or equal to 3；(2) quantity of bubble should be more than or equal to 1 in oscillation rings；(3) it vibrates
The quantity of token is a positive even numbers in ring.
The Miller unit Muller C_element of multi input is as shown in figure 3, Miller unit Muller C_ in the present invention
Element has the input of the identical function of multiple groups.Wherein F11 to F1n is the input of the identical function of n group.R11 to R1n
It is the n group input of identical function.Miller unit Muller C_element difference and the Miller unit of multi input of the invention
The main feature of Muller C_element first is that using multi input Miller unit Muller C_element.
As shown in figure 3, multi input Miller unit Muller C_element includes set and reset signal, can be used to adjust
The original state of whole oscillation rings, and the mode of oscillation of oscillation rings is set.There are two types of communication modes for oscillation rings: uniform intervals propagating mode
Formula and burst communication mode.If the quantity of bubble and the quantity of token difference are smaller in the original state of oscillation rings,
At this moment Charlie's effect in Miller unit Muller C_element is bigger, and output clock frequency is higher, and oscillation rings are at this time
Uniform intervals communication mode.If the quantity of bubble and the quantity of token difference are bigger in the original state of oscillation rings, close
The Charlie's effect strangled in unit Muller C_element is smaller, and the frequency of the clock of output is lower, and oscillation rings are at this time
Happen suddenly communication mode.In the case where identical series, the frequency of uniform intervals communication mode is higher.In the above manner, first
Begin that mode of oscillation and the frequency adjustment of input clock in self-timing oscillation rings may be implemented in configuration.
Fig. 4 is a kind of specific embodiment of multi input Miller unit Muller C_element of the present invention, including two groups
Identical input F1 and F2, R1 and R2.The truth table of Miller unit Muller C_element is as shown in table 1
Table one, multi input Miller unit truth table
Miller unit Muller C_element has a more circuit structure, present embodiment only wherein an example,
The present invention is not limited to the implementation methods of Fig. 4.
Fig. 5 is one embodiment of the present of invention.It include 33 grades of self-timing oscillation rings in embodiment.It mentions through the invention
The coupling process of confession, coupling generates 3 × 3 clock phases, to realize multiphase clock.The design is based on digital design,
It is good with the migration between technique, the features such as the good combination property and high resolution of area, power consumption and anti-PVT characteristic.Figure
6 be the analogous diagram of high-resolution multiphase clock generation circuit of the present invention, for the circuit structure of Fig. 5, can produce 9 phases
Clock.
One skilled in the art will appreciate that in addition to realizing system provided by the invention in a manner of pure computer readable program code
It, completely can be by the way that method and step be carried out programming in logic come so that provided by the invention other than system, device and its modules
System, device and its modules are declined with logic gate, switch, specific integrated circuit, programmable logic controller (PLC) and insertion
The form of controller etc. realizes identical program.So system provided by the invention, device and its modules may be considered that
It is a kind of hardware component, and the knot that the module for realizing various programs for including in it can also be considered as in hardware component
Structure；It can also will be considered as realizing the module of various functions either the software program of implementation method can be Hardware Subdivision again
Structure in part.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make a variety of changes or modify within the scope of the claims, this not shadow
Ring substantive content of the invention.In the absence of conflict, the feature in embodiments herein and embodiment can any phase
Mutually combination.
Claims (10)
1. a kind of multiphase clock generation circuit characterized by comprising
M n grades of self-timing oscillation rings；
Loop coupling is vibrated in the m n grades of self-timings.
2. multiphase clock generation circuit according to claim 1, which is characterized in that the n grades of self-timing oscillation rings packet
It includes:
The Miller unit Muller C_element of n multi input；
The Miller unit Muller C_element of the multi input includes: the input of multiple groups identical function, and wherein at least one group
For generating oscillator signal, at least one set is for vibrating loop coupling with other n grades of self-timing.
3. multiphase clock generation circuit according to claim 2, which is characterized in that the Miller unit of the multi input
Muller C_element:
The Miller unit Muller C_element logical expression of multi input is as follows:
F is the input of n group identical function: F1=F2=....=Fn
R is the input of n group identical function: R1=R2=....=Rn
Wherein,
SET indicates the SET signal of the Miller unit Muller C_element of multi input；
RESET indicates the RESET signal of the Miller unit Muller C_element of multi input；
C indicates the output of the Miller unit Muller C_element of multi input.
4. multiphase clock generation circuit according to claim 3, which is characterized in that at least one set identical function
Input:
With other one or more Miller units in addition to the Miller unit of this multi input in the n grades of self-timing oscillation rings
The output of Muller C_element is connected, and makes the Miller unit Muller C_ of n multi input in n grades of self-timing oscillation rings
Element connection.
5. multiphase clock generation circuit according to claim 4, which is characterized in that at least one set identical function
Input:
With other n grades of self-timing oscillation rings in addition to this n grades of self-timing oscillation rings in the m n grades of self-timing oscillation rings
In one or more multi inputs Miller unit Muller C_element output be connected, make m n grades of self-timing oscillation rings
Coupling.
6. multiphase clock generation circuit according to claim 5, which is characterized in that at least one set inputs and other
Loop coupling is vibrated in n grades of self-timings:
At least one set input is connected from the output of different Miller unit Muller C_element.
7. multiphase clock generation circuit according to claim 6, which is characterized in that the Miller unit of the multi input
Muller C_element provides an initialization and configuration circuit；
The initialization and configuration circuit carry out initial configuration to n grades of self-timing oscillation rings, and configuration self-timing oscillation rings generate
Different frequencies of oscillation and waveform.
8. multiphase clock generation circuit according to claim 7, which is characterized in that the n grades of self-timing oscillation rings produce
Raw n clock phase；
The m n grades of self-timings oscillation loop coupling generates m × n clock phase.
9. multiphase clock generation circuit according to claim 8, which is characterized in that further include:
By adjusting the series n of the self-timing oscillation rings and quantity m of self-timing oscillation rings, different clock phases is generated.
10. multiphase clock generation circuit according to claim 9, which is characterized in that the grade of the self-timing oscillation rings
Number n is the positive integer more than or equal to 3；
The quantity m of self-timing oscillation rings is the positive integer more than or equal to 2.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110518884A (en) * | 2019-08-20 | 2019-11-29 | 上海交通大学 | Be delayed amplifier |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005130302A (en) * | 2003-10-24 | 2005-05-19 | Internatl Business Mach Corp <Ibm> | Oscillator |
| US20050146361A1 (en) * | 2003-12-31 | 2005-07-07 | Burton Edward A. | Apparatus and method to control self-timed and synchronous systems |
| CN101242169A (en) * | 2007-02-09 | 2008-08-13 | 奇岩电子股份有限公司 | Device and method for generating multi-phase clock pulse signal based on ring oscillator |
| US20100156543A1 (en) * | 2008-12-22 | 2010-06-24 | Stmicroelectronics Pvt. Ltd. | Matrix structure oscillator |
| US8067989B1 (en) * | 2008-04-11 | 2011-11-29 | Quintic Holdings | Alternate clock apparatus and methods for improving radio performance |
| CN103297046A (en) * | 2013-05-09 | 2013-09-11 | 英特格灵芯片(天津)有限公司 | Phase-locked loop and method and circuit for producing clock thereof |
| CN104101827A (en) * | 2014-06-25 | 2014-10-15 | 东南大学 | Process corner detection circuit based on self-timing oscillation ring |
| CN104579319A (en) * | 2014-04-22 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Multi-phase clock generator |
| US9954540B1 (en) * | 2017-03-17 | 2018-04-24 | Oracle International Corporation | Asymmetric locking technique for asymmetric frequency locked loop |
| CN109271136A (en) * | 2018-08-06 | 2019-01-25 | 上海交通大学 | Real random number generator and method for generation based on FPGA |
-
2019
- 2019-02-26 CN CN201910142588.7A patent/CN109787619B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005130302A (en) * | 2003-10-24 | 2005-05-19 | Internatl Business Mach Corp <Ibm> | Oscillator |
| US20050146361A1 (en) * | 2003-12-31 | 2005-07-07 | Burton Edward A. | Apparatus and method to control self-timed and synchronous systems |
| CN101242169A (en) * | 2007-02-09 | 2008-08-13 | 奇岩电子股份有限公司 | Device and method for generating multi-phase clock pulse signal based on ring oscillator |
| US8067989B1 (en) * | 2008-04-11 | 2011-11-29 | Quintic Holdings | Alternate clock apparatus and methods for improving radio performance |
| US20100156543A1 (en) * | 2008-12-22 | 2010-06-24 | Stmicroelectronics Pvt. Ltd. | Matrix structure oscillator |
| CN103297046A (en) * | 2013-05-09 | 2013-09-11 | 英特格灵芯片(天津)有限公司 | Phase-locked loop and method and circuit for producing clock thereof |
| CN104579319A (en) * | 2014-04-22 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Multi-phase clock generator |
| CN104101827A (en) * | 2014-06-25 | 2014-10-15 | 东南大学 | Process corner detection circuit based on self-timing oscillation ring |
| US9954540B1 (en) * | 2017-03-17 | 2018-04-24 | Oracle International Corporation | Asymmetric locking technique for asymmetric frequency locked loop |
| CN109271136A (en) * | 2018-08-06 | 2019-01-25 | 上海交通大学 | Real random number generator and method for generation based on FPGA |
Non-Patent Citations (3)
| Title |
|---|
| MINMIN ZHANG等: "A Self-Timed Ring Based Time-to-Digital Converter on FPGA", 《2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)》 * |
| OUSSAMA ELISSATI等: "A novel High-Speed Multi-phase Oscillator Using Self-Timed Rings", 《2010 INTERNATIONAL CONFERENCE ON MICROELECTRONICS》 * |
| OUSSAMA ELISSATI等: "Multi-phase low-noise digital ring oscillators with sub-gate-delay resolution", 《AEU - INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110518884A (en) * | 2019-08-20 | 2019-11-29 | 上海交通大学 | Be delayed amplifier |
| CN110518884B (en) * | 2019-08-20 | 2021-03-09 | 上海交通大学 | Time-delay amplifier |
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| Publication number | Publication date |
|---|---|
| CN109787619B (en) | 2020-09-15 |
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