JPH11110067A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely suppress the entire EMI intensity by dividing an internal logic circuit into plural blocks and also changing the clock duty ratio that is supplied to each of these divided logic circuit blocks. SOLUTION: An internal logic circuit 3 included in an ASIC 2 is divided into internal logic blocks 37, 38, 39 and 40. An external clock 1 is received by a PLL included in a duty ratio control circuit 3.32, and the output is taken out of every stage of a VCO. Thus, the pulses 33, 34, 35 and 36 of different duty ratios are generated and then supplied to those divided logic blocks 27 to 40 respectively as blocks. As a result, the frequency components of EMI intensity are equalized and accordingly the entire EMI intensity can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for averaging an operating frequency generated by concentrating an odd number of times of EMI by an internal clock by using a duty ratio control circuit capable of changing a duty ratio, thereby obtaining an overall electromagnetic wave. Disturbance: relates to a semiconductor integrated circuit capable of reducing EMI (Electro-Magnetic Interference) intensity.

[0002]

2. Description of the Related Art In recent years, the speed of information communication devices such as personal computers has been increasing. However, noise has become a major problem due to the increase in speed, and EMI generated from within the ASIC has been increasing.
For example, the influence of the peripheral device caused by the problem is a problem.

A conventional semiconductor integrated circuit is supplied by an external clock from a crystal oscillator or a microcomputer or the like.
Is working. Normally, an external clock uses a waveform having a duty of 50%, so that EMI generated by an internal clock is generated at an odd multiple of the operating frequency.

FIG. 25 shows a conventional semiconductor integrated circuit. FIG. 25 (a) is a configuration diagram thereof, and FIG.
Indicates its frequency component and intensity. FIG.
In FIG. 5A, reference numeral 2 denotes an ASIC, and reference numeral 3 denotes an internal logic circuit including internal logic in the ASIC 2. In this semiconductor integrated circuit, as shown in FIG.
The intensity concentrates on a specific frequency component and shows a large value. For this reason, the EMI intensity of each frequency component is dispersed,
A circuit for averaging is required.

As a prior art for suppressing such EMI intensity, there is Japanese Patent Application Laid-Open No. Hei 4-310699. This is to generate a clock signal having two or more duty ratios by a counter to reduce EMI intensity.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit capable of accurately reducing such EMI intensity.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit which operates in response to a voltage adjustment signal and can derive a plurality of outputs having different delay values, and an applied clock input signal. A phase comparison circuit that can compare the phase with an arbitrary output of the oscillator and adjust the frequency of the oscillator so that the phases match, and a clock generator that can output a plurality of clock signals having different duty ratios from each output of the oscillator A circuit and a plurality of internal logic circuit blocks divided into a plurality of blocks, wherein a plurality of clocks from the clock generation circuit are applied to the plurality of internal logic circuit blocks, respectively.

[0008] In the semiconductor integrated circuit of the second invention,
The voltage adjustment signal is used to compare the phase of an oscillator in which an inverter capable of varying the delay value is connected in an odd-numbered stage ring shape with the applied clock input signal and the output of any inverter constituting the oscillator, so that the phases match. A phase comparison circuit that can adjust the frequency of the oscillator, a clock generation circuit that can output a plurality of clock signals having different duty ratios from the output of each inverter of the oscillator, and a plurality of internal logic circuit blocks divided into a plurality of blocks And applying a plurality of clocks from the clock generation circuit to a plurality of the internal logic circuit blocks, respectively.

In a semiconductor integrated circuit according to a third aspect of the present invention,
A clock generating circuit capable of switching a plurality of clocks having different duty ratios from each output of the oscillator for each cycle and outputting a plurality of clock signals; and switching a plurality of clocks from the clock generating circuit for each cycle to provide a plurality of clocks. This is applied to each of the internal logic circuit blocks.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 to 13 show a basic circuit on which the present invention is based. FIG. 1 is an overall configuration diagram showing an example of a basic circuit of a duty ratio control circuit as a premise of the present invention. In FIG. 1, 3 is AS
An internal logic circuit 4 in the IC is a duty ratio control circuit 1, and a duty ratio control circuit 1:
The operation is performed by the clock 5 output from the clock signal 4.

FIG. 2 is a circuit diagram of the duty ratio control circuit 1: 4 used in the basic circuit shown in FIG. Reference numeral 6 denotes a PLL (= Phase Lock Loop), and reference numeral 8 denotes a duty ratio selection circuit 1. Output 7 from PLL6
Is received by the duty ratio selection circuit 1: 8.

FIG. 3 is a circuit diagram of the PLL used in the circuit configuration of FIG. 2, and the portion surrounded by 9 is a VCO (= V
oltage Controlled Osillator), 15 is VCO
9 is the first stage output, 16 is the second stage output, 17 is the third stage output,
Reference numeral 18 denotes a fourth stage output, and 19 denotes a final stage output.

An external clock 1 is received by the PLL 6,
The output from each stage of the VCO 9 constituting the PLL 6 is extracted. Each block 10, 11, 1 in the VCO 9 of the PLL 6
2, 13, and 14 are constituted by the same circuit.
That is, the delay time of each block is the same.

In this description, the VCO 9 operates in five stages. Further, each of the blocks 10, 11, 12,.
13 and 14 each have a delay time of π / 5 [rad]. Each block 10 in the VCO 9
Each of 11, 12, 13, and 14 is constituted by an inverter, and is in the form of an oscillator in which inverters whose delay values can be varied as a whole are connected in an odd-numbered ring.

The output 15 of each stage extracted from the VCO 9
(Clk1), 16 (clk2), 17 (clk3), 18 (clk
4), 19 (clk5) are input to the duty ratio selection circuit 1: 8.

FIG. 4 shows a duty ratio selection circuit. 20
Is a selector, and its operation timing is as shown in the timing chart of FIG. In the duty ratio selection circuit 8, 16 (clk2), 17 (clk3), 18 (clk2)
4) and 19 (clk5) generate pulses corresponding to a delay time of 15 (clk1).

The output 16 of each stage extracted from the VCO 9
(Clk2), 17 (clk3), 18 (clk4), 19 (clk5)
Is input to the selector 20. In the selector 20, 2-bit control data 2 (such as a microcomputer)
1 (D0) and 22 (D1), outputs 16, 17, 1
Select any pulse from 8, 19 and 15 (cl
A clock 5 synchronized with k1) is output, and a clock is supplied to the internal logic 3. FIG. 5 shows a truth table relating to the input and output of the selector 20.

FIG. 6 shows a duty ratio control circuit 1
The timing of is shown. In addition, when the duty ratio is 50%, θ
The frequency component of the waveform whose duty is shifted by [rad] can be obtained from the equation shown in Table 1.

[0019]

[Table 1]

The EMI intensity distribution is as shown in Table 2.

[0021]

[Table 2]

Thus, a clock can be generated in which the odd multiples and the even multiples of the reference frequency are equal to each other, so that the overall EMI intensity can be reduced.

FIG. 7 shows that the odd number times and the even number times of the reference frequency become equal and the EMI intensity decreases. A case is shown in which a duty ratio control circuit 1 generates a waveform whose duty ratio deviates by θ [rad] from a duty of 50% (here, (D1, D0) = (1, 0) is selected).

FIG. 8 is an overall configuration diagram of a duty ratio control circuit 2 showing another example of the basic circuit on which the present invention is based. Reference numeral 2 denotes an ASIC, reference numeral 3 denotes an internal logic circuit in the ASIC 2, reference numeral 23 denotes a duty ratio control circuit 2, and the internal logic circuit 3 operates by a clock 24 output from the duty ratio control circuit 2:23.

FIG. 9 is a circuit diagram of the duty ratio control circuit 2 used in the circuit shown in FIG. Reference numeral 6 denotes a PLL, and reference numeral 25 denotes a duty ratio selection circuit 2.
The output 7 from the PLL 6 is received by the duty ratio selection circuit 25.

Reference numeral 31 denotes a signal for externally controlling the operation mode and the stop mode of the signal duty ratio selection circuit (by a microcomputer or the like). Similarly to the above, the external clock 1 is received by the PLL 6, and the V
The output from each stage of CO9 is taken out. Also, in this description, as in the above, the VCO has a five-stage configuration, and the blocks 10, 11, 12, 13, and 14 in the VCO are each π.
It has a delay time of / 5 [rad]. VCO9
Outputs 15 (clk1) and 16 (clk1)
2), 17 (clk3), 18 (clk4) and 19 (clk5)
It is input to the duty ratio selection circuit 2:25.

FIG. 10 shows the duty ratio selection circuit 2.
Reference numeral 26 denotes a selector, the operation of which is as shown in FIG. Also, 27 and 28 are flip-flops, and the operation is as shown in FIG. In the duty ratio selection circuit 2, 1
6 (clk2), 17 (clk3), 18 (clk4), 19 (clk2)
5) generates a pulse for a delay time of 15 (clk1).

Output 16 of each stage extracted from VCO 9
(Clk2), 17 (clk3), 18 (clk4), 19 (clk5)
Is input to the selector 26. The selector 26 selects 2bi of the select signals 24 and 25
By the up counter of t, (25 (S1), 24 (S0)) =
(0,0) → (0,1) → (1,0) → (1,1) →
The count is repeated in synchronization with (0,0) →... And 15 (clk1) (25 is the upper bit, and 24 is the lower bit). When the (Res) signal of the selector 26 is “L”, the clock 24 supplied to the internal logic is cut off,
"L" is output. Clock supply is performed at “H”.

Clock 24 supplied to internal logic 3
Are, as shown in FIG. 12, 15 (clk1) and 16 (clk2)
(Clk1−clk2) for a delay time of (clk1−clk2): 15 (clk1) and pulses (clk1−clk3) for a delay time of 17 (clk3): 15 (cl)
k1) and 18 (clk4) delay time pulses (clk1−clk)
4): expressed as follows) → 15 (clk1) and 19 (clk1)
5) Pulses for the delay time (clk1−clk5): These are represented as follows. → Synchronously with (clk1−clk2) and 15 (clk1), pulses are sequentially generated every cycle, and the internal logic 3
Supply clock to

As a result, the duty ratio of the clock changes when the signal propagates to the internal circuit. If a duty ratio control circuit that always changes the duty ratio is used, even if the desired effect cannot be obtained, the overall EMI intensity can be reduced. Is equalized to each frequency, so that
It is possible to lower the I intensity.

In FIG. 13, the duty ratio control circuit 2 changes the duty from 50% to 1 / 5π [ra].
d], 2 / 5π [rad], 3 / 5π [rad], 4 /
The frequency component and the intensity of the waveform whose duty ratio is shifted by 5π [rad] are shown.

FIG. 14 is an overall configuration diagram of the first embodiment of the duty ratio control circuit 3 according to the present invention.
Reference numeral 2 denotes an ASIC, reference numeral 3 denotes an internal logic circuit including internal logic in the ASIC 2, reference numerals 37, 38, 39, and 40 denote internal logic circuit blocks each including an internal logic block. The internal logic 3 is divided into four blocks. Reference numeral 32 denotes a duty ratio control circuit 3, and clocks 33, 3 output from the duty ratio control circuit 3:32.
Internal logic blocks divided into four by 4, 35, 36: 137, internal logic blocks 2: 38, internal logic blocks 3: 39, internal logic blocks 4: 40
Works.

FIG. 15 is a circuit diagram of the duty ratio control circuit 3 shown in FIG. Reference numeral 6 denotes a PLL, and reference numeral 41 denotes a duty ratio selection circuit 3. The output 7 from the PLL 6 is received by the duty ratio selection circuit 3:41.

In the same manner as shown in FIGS. 1 to 7, an external clock 1 is received by the PLL 6, and
6. The output from each stage of the VCO 9 constituting 6 is taken out. In this description, as in the case shown in FIGS. 1 to 7, the VCO has a five-stage configuration, and each of the blocks 10, 11, 12, 13, and 14 in the VCO includes π / 5 [rad]. ]
Has a delay time of The outputs 15 (clk1), 16 (clk2), 17 (clk1) of each stage taken out from the VCO 9
3), 18 (clk4) and 19 (clk5) are input to the duty ratio selection circuit 3:41.

FIG. 16 shows the duty ratio selection circuit 3.
Pulses 33, 34, 35, 3 for each generated delay time
6 is supplied as a clock to each of the internal logics 37, 38, 39, and 40 divided in synchronization with 15 (clk1). (In this description, the VCO is described as having five stages, so that it is divided into four. Described in the internal logic). Clocks 33, 34, 3 supplied to the internal logic divided into four
The timings of 5, 36 are as shown in FIG.

By dividing the internal logic and supplying clocks having different duty ratios to the respective internal logics as described above, the overall EMI intensity is equalized because the respective frequency components are equalized. It is possible to lower.

Embodiment 2 FIG. 18 is an overall configuration diagram of Embodiment 2 of the duty ratio control circuit according to the present invention. 3 is an internal logic circuit 47 in the ASIC,
Numerals 48, 49 and 50 are obtained by dividing the internal logic 3 into four blocks. Reference numeral 42 denotes a duty ratio control circuit 4. Internal clocks 47, 48, 49, and 50 divided into four by clocks 43, 44, 45, and 46 output from the duty ratio control circuit 4:42 operate.

FIG. 19 is a circuit diagram of the duty ratio control circuit 4 used in the second embodiment shown in FIG. Reference numeral 52 denotes a signal for externally controlling the operation mode and the stop mode of the signal duty ratio selection circuit 4 (such as a microcomputer).

As in the case shown in FIGS. 1 to 7, an external clock 1 is received by the PLL 6, and
6. The output from each stage of the VCO 9 constituting 6 is taken out. In this description, as in the case shown in FIGS. 1 to 7, the VCO has a five-stage configuration, and each of the blocks 10, 11, 12, 13, and 14 in the VCO includes π / 5.
It has a delay time of [rad].

The output 15 of each stage extracted from the VCO 9
(Clk1), 16 (clk2), 17 (clk3), 18 (clk
4) and 19 (clk5) are duty ratio selection circuits 2:51
Is input to

FIGS. 20 to 23 show the duty ratio selection circuit 4. FIG. 53, 54, 55, and 56 are selectors, and the operation is as shown in FIG. 57, 58, 5
9, 60, 61, 62, 63 and 64 are flip-flops, and the operation is as shown in FIG.

In the duty ratio selection circuit 2:51, 16
(Clk2), 17 (clk3), 18 (clk4), 19 (clk5)
Generates a pulse for a delay time of 15 (clk1).
Output 16 (clk2), 17 of each stage taken out from VCO 9
(Clk3), 18 (clk4), 19 (clk5) inversion and 15
The difference from (clk1) is input to the selectors 53, 54, 55, 56.

The selectors 53, 54, 55 and 56 are 2b
(0,0) → (0,1) by the up counter of it
→ (1,0) → (1,1) → (0,0) →... And 15
The count is repeated in synchronization with (clk1) (25 is the upper bit, and 24 is the lower bit). When the res signal 52 is “L”, the clock 43 supplied to the internal logic,
44, 45, and 46 are cut off and "L" is output. “H”
Sometimes supply of clocks 43, 44, 45, 46 is 47, 4
8, 49 and 50 are performed to the internal logic.

Clock 43 supplied to internal logic 47
As shown in FIG. 20, 15 (clk1) and 16 (clk2) at the timing shown in the timing chart of FIG.
(Clk1−clk2) for a delay time of (clk1−clk2): 15 (clk1) and pulses (clk1−clk3) for a delay time of 17 (clk3): 15 (cl)
k1) and 18 (clk4) delay time pulses (clk1−clk)
4): expressed as follows) → 15 (clk1) and 19 (clk1)
5) The pulse for the delay time (clk1−clk5): expressed as follows: → Synchronized with (clk1−clk2) and 15 (clk1),
A pulse is sequentially generated for each cycle, and a clock is supplied to the internal logic 47.

Clock 44 supplied to internal logic 48
Is (clk1-clk3) → (clk1-clk) as shown in FIG.
k4) → (clk1-clk5) → (clk1-clk2) → (clk1-clk
Synchronize with 3) and 15 (clk1), generate pulses sequentially for each period, and supply a clock to the internal logic 48.

Clock 45 supplied to internal logic 49
Is (clk1−clk4) → (clk1−clk) as shown in FIG.
k5) → (clk1-clk2) → (clk1-clk3) → (clk1-clk
Synchronizing with 4) and 15 (clk1), a pulse is sequentially generated for each cycle, and a clock is supplied to the internal logic 49.

Clock 46 supplied to internal logic 50
Is (clk1-clk5) → (clk1-clk) as shown in FIG.
k2) → (clk1-clk3) → (clk1-clk4) → (clk1-clk
Synchronizing with 5) and 15 (clk1), a pulse is sequentially generated every period, and a clock is supplied to the internal logic 50.

As described above, the internal logic circuit is divided into a plurality of blocks, the duty ratio of the clock supplied to each internal logic circuit block is changed, and the duty ratio of each clock is sequentially changed. Since the entire EMI intensity is dispersed into different frequency components, and the respective frequency components are equalized, the overall EMI intensity can be reduced.

As described above, according to the embodiment of the present invention, the configuration is such that the duty ratio of the internal logic of the ASIC is divided into any number, so that there is an effect of suppressing the overall EMI intensity.

[0050]

According to the first aspect of the present invention, by dividing the internal logic circuit into a plurality of blocks and changing the duty ratio of the clock supplied to each of the internal logic circuit blocks, the overall EMI intensity can be changed at different frequencies. Dispersed in the ingredients,
Since each frequency component is equalized, the entire EM
A semiconductor integrated circuit capable of appropriately suppressing the I intensity can be obtained.

According to the second aspect of the present invention, an oscillator in which an inverter capable of varying a delay value by a voltage adjustment signal is connected in an odd-numbered ring shape is used, and an internal logic circuit is divided into a plurality of blocks. By changing the duty ratio of the clock supplied to the internal logic circuit block, the entire EMI intensity is dispersed into different frequency components,
Since each frequency component is equalized, the entire EM
A semiconductor integrated circuit capable of suppressing I intensity more accurately can be obtained.

According to the third aspect, the internal logic circuit is divided into a plurality of blocks, the duty ratio of the clock supplied to each internal logic circuit block is changed,
By switching a plurality of clocks having different duty ratios in each cycle, the entire EMI intensity is dispersed into different frequency components, and the respective frequency components are equalized, so that the overall EMI intensity can be more accurately suppressed. A possible semiconductor integrated circuit can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit of the present invention.

FIG. 2 shows a duty ratio control circuit 1 according to the present invention.
FIG.

FIG. 3 is a duty ratio control circuit 1 of the present invention.
FIG. 3 is a circuit diagram of a PLL used in the embodiment.

FIG. 4 is a duty ratio control circuit 1 of the present invention.
3 is a circuit diagram of the duty ratio selection circuit 1 in FIG.

FIG. 5 is a diagram showing a truth table of a selector used in the duty ratio control circuits 1, 2, 3, and 4 of the present invention.

FIG. 6 is a duty ratio control circuit 1 according to the present invention.
3 is a timing chart of FIG.

FIG. 7 is a diagram showing an effect of the present invention when the duty is shifted by 2 / 5π from 50%.

FIG. 8 is a configuration diagram of a semiconductor integrated circuit of the present invention.

FIG. 9 is a duty ratio control circuit 2 of the present invention.
FIG.

FIG. 10 is a circuit diagram of a duty ratio selection circuit 2 in the duty ratio control circuit 2 of the present invention.

FIG. 11 is a truth table of a flip-flop used in the duty ratio control circuits 2 and 4 of the present invention.

FIG. 12 is a timing chart of the duty ratio control circuit 2 of the present invention.

FIG. 13 shows a duty of 50% to 1/5 of the present invention.
FIG. 9 is a diagram illustrating an effect when shifting by π, 2 / 5π, 3 / 5π, and 4 / 5π.

FIG. 14 is a configuration diagram of a semiconductor integrated circuit of the present invention.

FIG. 15 is a configuration diagram of a duty ratio control circuit 3 of the present invention.

FIG. 16 is a circuit diagram of the duty ratio selection circuit 3 in the duty ratio control circuit 3 of the present invention.

FIG. 17 is a timing chart of the duty ratio control circuit 3 of the present invention.

FIG. 18 is a configuration diagram of a semiconductor integrated circuit of the present invention.

FIG. 19 is a configuration diagram of the duty ratio control circuit 4 of the present invention.

FIG. 20 is a circuit diagram in a case where a clock is supplied to the internal logic 47 by the duty ratio selection circuit 4 in the duty ratio control circuit 4 of the present invention.

FIG. 21 is a circuit diagram in a case where a clock is supplied to the internal logic 48 by the duty ratio selection circuit 4 in the duty ratio control circuit 4 of the present invention.

FIG. 22 is a circuit diagram when a clock is supplied to the internal logic 49 by the duty ratio selection circuit 4 in the duty ratio control circuit 4 of the present invention.

FIG. 23 is a circuit diagram when a clock is supplied to the internal logic 50 by the duty ratio selection circuit 4 in the duty ratio control circuit 4 of the present invention.

FIG. 24 is a timing chart of the duty ratio control circuit 4 of the present invention.

FIG. 25 is a configuration diagram of a conventional semiconductor integrated circuit.

[Explanation of symbols]

3 internal logic, 4 duty ratio control circuit, 6 PLL, 8 duty ratio selection circuit, 9 VC
O, 32 duty ratio control circuit, 37 internal logic circuit block consisting of internal logic 1, 38 internal logic circuit block consisting of internal logic 2, 39 internal logic circuit block consisting of internal logic 3, 40 internal logic circuit consisting of internal logic 4 block.

Claims (3)

[Claims] An oscillator that operates in response to a voltage adjustment signal and can derive a plurality of outputs having different delay values, compares the phase of an applied clock input signal with an arbitrary output of the oscillator, and determines the phase. A phase comparison circuit that can adjust the frequency of the oscillator so that they match, a clock generation circuit that can output a plurality of clock signals having different duty ratios from each output of the oscillator, and a plurality of internal logic circuit blocks divided into a plurality of blocks Wherein a plurality of clocks from the clock generation circuit are applied to a plurality of the internal logic circuit blocks, respectively. 2. An oscillator in which inverters whose delay values can be varied by a voltage adjustment signal are connected in an odd-numbered stage ring shape.
A phase comparison circuit that compares the applied clock input signal with the phase of the output of any inverter that constitutes the oscillator, and adjusts the frequency of the oscillator so that the phases match;
A clock generation circuit capable of outputting a plurality of clock signals having different duty ratios from outputs of the respective inverters of the oscillator; and a plurality of internal logic circuit blocks divided into a plurality of blocks, and a plurality of clocks from the clock generation circuit. Is applied to each of the plurality of internal logic circuit blocks. 3. A clock generating circuit capable of outputting a plurality of clock signals by switching a plurality of clocks having different duty ratios from each output of the oscillator for each period,
3. The semiconductor integrated circuit according to claim 1, wherein a plurality of clocks from the clock generation circuit are switched for each cycle and applied to each of the plurality of internal logic circuit blocks.