201025829 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種振盪器，特別是有關於一種數位 控制振盪器。 【先前技術】 近年來，隨著深次微米（deep-submicron)技術的演進， 具有高效能以及易製作的積體電路(Integrated Circuit;以下 ❿ 簡稱1C)的發展係引人注目的。可擴充的微處理器（scalable microprocessor)系統以及繪圖處理器系統可經濟有效地 (cost-effectively)應用在先前的技術，用以增加時序率（ci〇ck rate)、降低功率損耗，並減少設計循環(design turn around) 的時間。在1C模組中，同步化是個重要的議題。因此，人 們將大量努力集中在高效能數位介面電路(digital interface circuit)，以和其它數位系統進行通信。鎖相迴路（Phase Locked Loop;以下簡稱PLL)被廣泛利用在許多高速微處 ❷理器及記憶體中。傳統的類比PLL通常具有較佳的顫動 (jitter)以及歪斜(skew)特性，但其製程需要較高的時間，而 且依賴於製程。相反的，數位PLL可被轉移至不同的製程。 此外’藉由比例CMOS技術(scaling CMOS technology)的好 處’數位PLL可操作在較低的工作電壓及位準，以具有較 佳的電源管理。為了使數位PLL應用在不同的時脈產生電 路或相位§周準電路中，操作頻率的範圍愈大愈好，方能符 合不同產品的規格。此外，具有較大範圍的PLL應該忍受 較大的時脈頻率、製程以及溫度的變化。 0758-A32056TWF;MTKI-06-050 3 201025829 , 第1圖係為習知數位控制振盪器之示意圖。如圖所 示’習知數位控制振盪器（Digital Controlled Oscillator， DCO)10具有延遲線12以及相位選擇器14。相位選擇器14 經過輸出信號Out控制延遲單元12ι〜i2n。 PLL的最大操作頻率係取決於數位控制振盪器的單一 延遲單元（121〜12η)的頻寬，而PLL的最小操作頻率係取決 於延遲線12的總延遲時間。習知的數位控制振蘯器的最大 操作頻率範圍如下示：201025829 VI. Description of the Invention: [Technical Field] The present invention relates to an oscillator, and more particularly to a digitally controlled oscillator. [Prior Art] In recent years, with the evolution of deep-submicron technology, the development of a high-performance and easy-to-manufacture integrated circuit (hereinafter referred to as 1C) has been attracting attention. Scalable microprocessor systems and graphics processor systems can be cost-effectively applied to previous technologies to increase ci〇ck rate, reduce power loss, and reduce design The time of the design turn around. Synchronization is an important issue in 1C modules. Therefore, a great deal of effort has been focused on high-performance digital interface circuits to communicate with other digital systems. The Phase Locked Loop (PLL) is widely used in many high-speed microprocessors and memories. Conventional analog PLLs typically have better jitter and skew characteristics, but the process requires a higher amount of time and is dependent on the process. Conversely, digital PLLs can be moved to different processes. In addition, 'the advantage of scaled CMOS technology' digital PLL can operate at lower operating voltages and levels for better power management. In order for the digital PLL to be applied in different clock generation circuits or phase § calibration circuits, the larger the operating frequency range, the better the specifications of different products. In addition, PLLs with a wide range should tolerate large clock frequency, process, and temperature variations. 0758-A32056TWF; MTKI-06-050 3 201025829, Fig. 1 is a schematic diagram of a conventional digitally controlled oscillator. As shown in the figure, a conventional Digital Controlled Oscillator (DCO) 10 has a delay line 12 and a phase selector 14. The phase selector 14 controls the delay units 12i to i2n via the output signal Out. The maximum operating frequency of the PLL is dependent on the bandwidth of the single delay unit (121~12n) of the digitally controlled oscillator, while the minimum operating frequency of the PLL is dependent on the total delay time of the delay line 12. The maximum operating frequency range of the conventional digitally controlled oscillator is as follows:
• F = J 其中，Τ為延遲線12的總延遲時間，Τι係為所有控制 位元均為低時的原始延遲時間，Cmax係為延遲線12的延 遲單元121~12n的最大數量。由上述方程式可知，操作頻 率的範圍可以均衡（trade off)硬體的複雜度和時間解析 度。可以藉由增加延遲單元的最大數量或者單個延遲單元 的延遲時間來擴展操作頻率的範圍。然而，前者增加了 = ❹體的複雜度，而後者降低了時間解析度。為了可同時符$ 所需的最大及最小速度’習知的數位PLL所需的數位控二 振盪器需由咼頻寬的延遲單元121-12n所構成。然而 了使具有高頻寬延遲單元的數位控制振盪器具有合理的^ 片面積，單一延遲單元的頻寬與延遲線12的長度間的取: 將實質上限制操作頻率範圍的最大與最小值的比率。捨 【發明内容】 有鑒於習知數位控制振盪器操作頻率範圍與硬體的 0758-A32056TWF;MTKI-06-050 4 201025829 複雜度以及時間解析度間的矛盾， 器 及用以產生周期信號的方法。 發月&供一種振盈 本發明提供—種振盈器，包括_冑 循環延遲線模組。循環控制器用以 2器以及一再 再循環延遲線模組用以提供一周期信號/ 。 組執行-再循環操作。在再循環操作的再循環 於循環控制信號。 17自艰人數係取決 纟發明另提供一種振^器，包括—再循環 以及一第二延遲線。再循環延遲線模組執行一再循^ 作。在再循環操作下，再循環的次數係取決：一 信號。再循環延遲線模組包括一第一延遲線。第：裏控制 輕接再循環延遲線模組。 〜^發明更提供一種方法，用以產生一周期信號，包括 =再=模式被致能時，對—第—閉迴路執行—再猶環 刼作’該第-閉迴路包括一第一延遲線；當該再 ❷被禁能時，將一第二延遲線連接該第一延遲線，並形成1 第二閉迴路；以及從該第二閉迴路輸出該周期信號。 、與習知數健制振盪H相比，本發明提供的振盈器及 用以產生周期信號的方法，藉由重覆使用延遲單元，可增 加操作頻率的範圍’而不需額外增加延遲單元的數量，具 有較小硬體開銷。 為讓本發明之上述和其他目的、特徵、和優點能更明 .顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳 細說明如下： 0758-A32056TWF;MTKI-06-050 5 201025829 【實施方式】 第2圖係為數位循環控制振盪器之方塊圖。如圖所 示’數位循環控制振盪器（Digital_Cycle_C〇ntr〇ller Oscillator ; DCCO)20包括，一循環控制器202、一再循環 延遲線模組204、一細微延遲線206以及一延遲調整單元 208。再循環延遲線模組204用以增加數位循環控制振盪器 20的操作頻率範圍的最大與最小值比率。細微延遲線2〇6 用以微調或是插入數位循環控制振盪器2〇的頻率。在其它 實施例中，若不需要精細的解析度，則可省略細微延遲線 206以及延遲調整單元2〇8。 第3圖為數位循環控制振盪器之一可能實施例。數位 循環控制振盪器30係為第2圖所示的數位循環控制振盪器 20的可旎實施例。在本實施例中，再循環延遲線模組 204(第2圖所示）係由再循環延遲線3〇2、第一選擇單元 及第二選擇單元所構成。細微延遲線206與細微延遲 參 線304一（第3圖所示）相同。延遲調整單元208 (第2圖所 不）由一角積分内插器(ΣΔ interp〇iator)3〇6所構成。藉由重 覆=用再循環延遲線3〇2的延遲單^，便可增加操作頻率 的範圍，並具有較小硬體開銷。延遲單元的重覆使用是一 j環操作。藉由再循環延遲線302及路徑316所構成的 閉迎路’便可執行再循環操作。因此，當藉由增加 循ί = Ϊ遲單元的次數’達到最小操作頻率需求時，再 : = = :頻率需求。延遲單元被重覆丄 疋再循環的次數。再循環的次數係取決於循環控制 〇758-A32056TWF;MTKI.〇6.〇5〇 201025829 器202。在再循環操作後，再循環延遲線3〇2連接細微延 遲線304。再循環延遲線3〇2、細微延遲線綱以及路徑 318構成一第二閉迴路。對比所需的操作周期 線304可補償剩餘的延遲。内插器3〇6更可婵加 度。數位循環控制振盪ϋ 30的輪出信號在節點〇2β處提 供。數巧循環控制振IH3G的操作頻率範圍如下式所示·· γ —— Τ T,<T^M *Cnax*At + Cl*At + C2*At + Tl 〇 < Cl < C 1• F = J where Τ is the total delay time of delay line 12, Τι is the original delay time when all control bits are low, and Cmax is the maximum number of delay units 121~12n of delay line 12. As can be seen from the above equation, the range of operating frequencies can be traded off the complexity and time resolution of the hardware. The range of operating frequencies can be extended by increasing the maximum number of delay units or the delay time of a single delay unit. However, the former increases the complexity of the ❹ body, while the latter reduces the time resolution. In order to simultaneously match the maximum and minimum speeds required for $, the digitally controlled two oscillators required for conventional digital PLLs are constructed of delay bandwidths 121-12n of the bandwidth. However, a digitally controlled oscillator having a high frequency wide delay unit has a reasonable chip area, and the ratio between the bandwidth of the single delay unit and the length of the delay line 12 will substantially limit the ratio of the maximum to the minimum of the operating frequency range.舍 [Summary] In view of the conventional digital control oscillator operating frequency range and hardware 0758-A32056TWF; MTKI-06-050 4 201025829 complexity and time resolution, the device and method for generating periodic signals . The present invention provides a vibrating device comprising a _胄 cyclic delay line module. The loop controller is used to provide a periodic signal / for the recirculating delay line module. Group execution - recycling operation. The recirculation operation is recycled to the cycle control signal. 17 The number of people in difficulty depends on the invention. Another invention provides a vibration device, including - recycling and a second delay line. The recirculating delay line module performs repeated cycles. In the recirculation operation, the number of recirculations depends on: a signal. The recirculating delay line module includes a first delay line. The first: the inner control lightly recirculates the delay line module. The invention also provides a method for generating a periodic signal, including = when the mode is enabled, the - first closed loop is performed - and the first closed delay line is included And when the re-enable is disabled, connecting a second delay line to the first delay line and forming a second closed loop; and outputting the periodic signal from the second closed loop. Compared with the conventional digital oscillation H, the vibrator provided by the present invention and the method for generating a periodic signal can increase the range of the operating frequency by repeatedly using the delay unit without adding an additional delay unit. The number has a smaller hardware overhead. The above and other objects, features, and advantages of the present invention will become more apparent and understood. -050 5 201025829 [Embodiment] FIG. 2 is a block diagram of a digital loop controlled oscillator. The digital loop control oscillator (Digital_Cycle_C〇ntr〇ller Oscillator; DCCO) 20 includes a loop controller 202, a recirculating delay line module 204, a fine delay line 206, and a delay adjusting unit 208. The recirculating delay line module 204 is used to increase the maximum to minimum ratio of the operating frequency range of the digital loop controlled oscillator 20. The fine delay line 2〇6 is used to fine tune or insert the digital loop to control the frequency of the oscillator 2〇. In other embodiments, the fine delay line 206 and the delay adjustment unit 2〇8 may be omitted if fine resolution is not required. Figure 3 is a possible embodiment of a digital loop controlled oscillator. The digital loop controlled oscillator 30 is an exemplary embodiment of the digital loop controlled oscillator 20 shown in Fig. 2. In the present embodiment, the recirculation delay line module 204 (shown in Fig. 2) is composed of a recirculation delay line 〇2, a first selection unit, and a second selection unit. The fine delay line 206 is the same as the fine delay line 304 (shown in Fig. 3). The delay adjustment unit 208 (not shown in Fig. 2) is composed of a one-point integral interpolator (ΣΔ interp〇iator) 3〇6. By repeating = the delay of the recirculation delay line 3 〇 2, the range of operating frequencies can be increased with less hardware overhead. The repeated use of the delay unit is a j-loop operation. The recirculation operation can be performed by the closed delay path formed by the recirculation delay line 302 and the path 316. Therefore, when the minimum operating frequency requirement is reached by increasing the number of cycles of the ί = 单元 unit, then : = = : frequency requirement. The delay unit is repeated 丄 疋 the number of recirculations. The number of recirculations depends on the cycle control 〇758-A32056TWF; MTKI.〇6.〇5〇 201025829 202. After the recirculation operation, the recirculation delay line 3〇2 is connected to the fine delay line 304. The recirculation delay line 〇2, the fine delay line, and the path 318 form a second closed loop. The required operational cycle line 304 can compensate for the remaining delay. The interpolator 3〇6 is more scalable. The round-out signal of the digital loop control oscillation ϋ 30 is provided at the node 〇 2β. The operating frequency range of the digital loop control IH3G is as follows: γ —— Τ T, <T^M *Cnax*At + Cl*At + C2*At + Tl 〇 < Cl < C 1
max 0<C2<1 其中，T係為延遲線（包含再循環延遲線3〇2及細微延 遲線304)的總延遲，當所有控制位元均為低時，T1係為原 始的延遲’ Μ縣重覆❹的:欠數，^係為再循環延遲 線302的延遲單元的數量，C1係為細微延遲線3〇4的延遲 單元的數量，C2係為内插因數，ci和C2即内插器306 的控制碼。數位循環控制振盪器30的最大操作頻率範圍與 習知數位控制震蕩器之最大操作頻率範圍的比率如下式所 示： ^ *Ai + Cl*Ai + C2*Ai+T, —-7：-« A/ + 1 由於控制器的硬體複雜度與操作頻率的範圍成正比 例，所以在給定的操作頻率範圍及時間解析度下，數位循 環控制振盪器30的硬體複雜度大大小於習知數位循環控 制振盪器的硬體複雜度。 在本實施例中，第一選擇單元308係由一第一多工器 所實現，而第二選擇單元310係由一第二多工器所實現。 數位循環控制振盪器30更具有一 d型正反器312。再循環 〇758-A32056TWF;MTKI-06-050 7 201025829 延遲包含兩多工器（308及310)、延遲單元3〇2以及D型正 反器312所造成的延遲。延遲單元的頻寬可被設計成最 大，以達到所需之最大操作頻率。在本實施例中，循環控 制器202(第2圖所示）可由一計數器314所實現。計數器 314產生一循環控制信號B。循環控制信號B控制多工器 (308及310)，用以選擇節點01或〇2的信號並傳送至再循 環延遲線302。舉例而言，當循環控制信號B為高位準時， 便可致能一再循環模式。因此，節點〇1的信號便可被傳 ❹送至再循環延遲線302,並且節點Ο連接節點01。當循環 控制信號B為低位準時，便禁能該再循環模式。因此，節 點02的信號便可被傳送至再循環延遲線302，並且節點〇 連接節點C。藉由不同的操作頻率，便可使時脈在再循環 延遲線302循環。藉由重覆使用延遲單元’便可增加再循 環延遲線302的延遲時間，而不需額外增加延遲單元的數 量。計數器314設定再循環延遲線302最理想的循環次數。 由於再循環延遲線302的NMOS及PMOS的驅動能力不匹 ® 配，再循環延遲線302不期望的工作周期（duty cycle)失真 可使得在低操作頻率下，節點Ο的輸出信號會消失。為解 決此問題’可將邊緣觸發的D型正反器312設置在再循環 延遲線302之前，用以對得到的邊緣作出反應。若需產生 極高的輸出頻率時，節點02的信號可直接旁路再猶環延 遲線302，並只使用細微延遲線304。在此情況下，路徑 320、318以及細微延遲線304構成一閉迴路，用以提供最 大輸出頻率。在本實施例中，内插器306根據控制媽ci， 在細微延遲線中，選擇兩個依序的相位，作為一内插相位。 0758-A32056TWF;MTKI-06-050 8 201025829 然後，被選定的相位會被内插，以根據控制碼C2，產生最 終相位。在高速顫動（dithering)下’可調變控制碼(C2)，用 以改善時間解析度。 第4圖及第5圖為模擬結果’顯示節點C、循環控制 信號B、節點〇及節點02的信號和計數器314的計數值》 假設，At=2ns ; Cmax=4 ; Cl=2 ; C2=0.25。第 4 圖為 M=5 的模擬結果。再循環延遲線302的延遲單元被重覆使用5 次。總延遲時間如下所示： 鲁 T=5*4*2ns+2*2ns+0.25*2ns=44.5ns 第5圖為M=100的模擬結果。再循環延遲線302的延 遲單元被重覆使用100次。總延遲時間如下所示： T=100*4*2ns+2*2ns+0.25*2ns=804.5ns 雖然本發明已以較佳實施例揭露如上，然其並#用以 限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作些許之更動與潤傅， 因此本發明之保護範圍當視後附之申請專利範圍所界定者 β為準。 【圖式簡單說明】 第1圖係為習知數位控制振盪器之示意圖； 第2圖係為數位循環控制振盪器之方塊圖； 第3圖為數位循環控制振盪器之一可能實施例；以及 第4圖及第5圖為模擬結果。 【主要元件符號說明】 0758-A32056TWF;MTKI-06-050 9 201025829 ίο :數位控制振盪器； 12 :延遲線； 14 :相位選擇器； 121~12n :延遲單元； 20、30 :數位循環控制振盪器； 202 :循環控制器； 204 :再循環延遲線模組； 206、304 :細微延遲線； ❹ 208 :延遲調整單元； 302 :再循環延遲線； 308、310 :選擇單元； 306 :三角積分内插器； 316、318、320 :路徑； 312 : D型正反器； 314 :計數器。 0758-A32056TWF;MTKI-06-050 10Max 0<C2<1 where T is the total delay of the delay line (including the recirculation delay line 3〇2 and the fine delay line 304). When all control bits are low, T1 is the original delay' Μ Counties repeat: 欠, ^ is the number of delay units of the recirculation delay line 302, C1 is the number of delay units of the fine delay line 3〇4, C2 is the interpolation factor, ci and C2 are within The control code of the interpolator 306. The ratio of the maximum operating frequency range of the digital loop controlled oscillator 30 to the maximum operating frequency range of the conventional digitally controlled oscillator is as follows: ^ *Ai + Cl*Ai + C2*Ai+T, —-7:-« A/ + 1 Since the hardware complexity of the controller is proportional to the range of the operating frequency, the hardware complexity of the digital loop controlled oscillator 30 is much smaller than that given the operating frequency range and time resolution. The digital loop controls the hardware complexity of the oscillator. In the present embodiment, the first selection unit 308 is implemented by a first multiplexer, and the second selection unit 310 is implemented by a second multiplexer. The digital loop controlled oscillator 30 further has a d-type flip-flop 312. Recycling 〇758-A32056TWF; MTKI-06-050 7 201025829 The delay includes delays caused by two multiplexers (308 and 310), delay unit 3〇2, and D-type flip-flop 312. The bandwidth of the delay unit can be designed to be maximum to achieve the desired maximum operating frequency. In the present embodiment, the loop controller 202 (shown in Fig. 2) can be implemented by a counter 314. Counter 314 generates a loop control signal B. The loop control signal B controls the multiplexers (308 and 310) for selecting the signal of node 01 or 〇2 and transmitting it to the recirculation delay line 302. For example, when the cycle control signal B is at a high level, a recirculation mode can be enabled. Therefore, the signal of node 〇1 can be transmitted to the recirculation delay line 302, and the node Ο is connected to node 01. When the cycle control signal B is at a low level, the recirculation mode is disabled. Therefore, the signal of node 02 can be transmitted to the recirculation delay line 302, and the node 〇 is connected to the node C. The clock is cycled through the recirculation delay line 302 by different operating frequencies. The delay time of the recirculation delay line 302 can be increased by repeatedly using the delay unit' without additionally increasing the number of delay units. Counter 314 sets the optimal number of cycles for recirculation delay line 302. Since the NMOS and PMOS drive capabilities of the recirculation delay line 302 are not matched, the undesired duty cycle distortion of the recirculation delay line 302 can cause the output signal of the node 会 to disappear at low operating frequencies. To solve this problem, an edge-triggered D-type flip-flop 312 can be placed before the recirculation delay line 302 to react to the resulting edge. To produce a very high output frequency, the signal at node 02 can be bypassed directly to the delay loop 302 and only the fine delay line 304 is used. In this case, paths 320, 318 and fine delay line 304 form a closed loop to provide the maximum output frequency. In the present embodiment, the interpolator 306 selects two sequential phases as an interpolated phase in the fine delay line according to the control mom ci. 0758-A32056TWF; MTKI-06-050 8 201025829 Then, the selected phase is interpolated to produce the final phase based on control code C2. Adjustable control code (C2) under high-speed dithering to improve time resolution. Fig. 4 and Fig. 5 are simulation results 'display node C, loop control signal B, node 〇 and node 02 signal and counter 314 count value' hypothesis, At=2 ns; Cmax=4; Cl=2; C2= 0.25. Figure 4 shows the simulation results for M=5. The delay unit of the recirculation delay line 302 is reused 5 times. The total delay time is as follows: Lu T=5*4*2ns+2*2ns+0.25*2ns=44.5ns Figure 5 shows the simulation results of M=100. The delay unit of the recirculation delay line 302 is reused 100 times. The total delay time is as follows: T = 100 * 4 * 2 ns + 2 * 2 ns + 0.25 * 2 ns = 804.5 ns Although the invention has been disclosed above in the preferred embodiment, it is intended to define the invention, any technology It is to be understood that the scope of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a conventional digitally controlled oscillator; FIG. 2 is a block diagram of a digital loop controlled oscillator; FIG. 3 is a possible embodiment of a digital loop controlled oscillator; Figures 4 and 5 show the simulation results. [Main component symbol description] 0758-A32056TWF; MTKI-06-050 9 201025829 ίο: digitally controlled oscillator; 12: delay line; 14: phase selector; 121~12n: delay unit; 20, 30: digital loop control oscillation 202: loop controller; 204: recirculating delay line module; 206, 304: fine delay line; ❹ 208: delay adjustment unit; 302: recirculation delay line; 308, 310: selection unit; Interpolator; 316, 318, 320: path; 312: D-type flip-flop; 314: counter. 0758-A32056TWF; MTKI-06-050 10