TWI478485B - Digitally controlled oscillator - Google Patents

Description

Digitally controlled oscillator

The present invention relates to a digitally controlled oscillator, and more particularly to a digitally controlled oscillator having a dual delay loop.

At present, most electronic products require clock signals when they are in operation, and the oscillation frequency of the clock signals may be different for the operation speeds required by different electronic products. Therefore, a Digitally Controlled Oscillator (DCO), which can output clock signals of different oscillation frequencies by inputting appropriate control signals, has been proposed and widely used in various types of electronic products.

Compared with the analog voltage controlled oscillator, the oscillation frequency of the clock signal output by the digitally controlled oscillator is less affected by factors such as process, and the digitally controlled oscillator has a smaller wafer area and better anti-noise capability. .

Currently known digitally controlled oscillators use more complex circuits to generate clock signals as signals for electronic products. For example, a digitally controlled oscillator consisting of a multiplexer and a buffer can control a signal to output a clock signal of a different oscillation frequency through a plurality of different buffers (ie, a path through which the control signal passes different time delays). .

However, the greater the number of multiplexers and buffers, the greater the propagation delay caused by each delay cell in the digitally controlled oscillator, and the relative increase in manufacturing costs. In this way, the gate delay of the clock signal will increase greatly, and the high frequency portion of the oscillation frequency range of the clock signal will be forced to decrease and cannot be improved, so the conventional digitally controlled oscillator may not be able to satisfy the high frequency. System requirements.

In addition, the currently known digitally controlled oscillators use the design of custom active components, so the same circuit design method cannot easily use different process technologies to manufacture digitally controlled oscillators with the same oscillation frequency range. As such, the process complexity, manufacturing cost, and manufacturing time of the digitally controlled oscillator may increase.

Embodiments of the present invention provide a digitally controlled oscillator that is low-cost, high-frequency wide, and can quickly adjust the oscillation frequency of a clock signal. The digital oscillating controller can be implemented by using a full digital position, and the user can change the control signal to cause the digital oscillating controller to generate an oscillating signal corresponding to the oscillating frequency of the control signal.

The embodiment of the present invention provides a digitally controlled oscillator, and the digitally controlled oscillator includes a first delay loop, a second delay loop, and an oscillating signal control circuit, wherein the oscillating signal control circuit is electrically connected to the first and second delays. Loop. The first delay loop has a plurality of first delay units connected in series. The second delay loop has a plurality of second delay units connected in series. The oscillating signal control circuit is configured to receive the first delayed signal output by the first delay loop, and determine to output the first delayed signal to the input end of the first or second delay loop according to the number of times the first delayed signal is received. After the oscillating signal control circuit inputs the first delayed signal to the second delay loop, the second delay loop outputs a second delayed signal to the output of the digitally controlled oscillator.

The embodiment of the invention provides an electronic device, and the electronic device includes at least one electronic chip and the digitally controlled oscillator. The electronic chip is configured to receive a clock signal generated according to the second delayed signal for operation.

In the embodiment of the present invention, the second delay signal output by the second delay loop is further received by the oscillating signal control circuit and transmitted to the input end of the first delay loop.

In an embodiment of the invention, the digitally controlled oscillator further includes a feedback circuit. The feedback circuit is electrically connected to the feedback signal input terminal of the oscillation signal control circuit. The feedback circuit is configured to generate a reset signal to the feedback signal input end of the oscillation signal control circuit according to the second delay signal, and the oscillation signal control circuit determines to recount the number of times the first delay signal is received according to the reset signal.

In summary, the digitally controlled oscillator provided by the embodiment of the present invention has a double delay loop. By the number of times the control signal passes through the first delay loop, it is possible to reduce the number of delay units and the gate delay experienced by the clock signal. As such, the digitally controlled oscillator has lower circuit design complexity, less circuit area, lower cost, and higher bandwidth than conventional digitally controlled oscillators. In addition, the oscillation frequency of the second delayed signal output by the digital control oscillator can be quickly adjusted by adjusting the number of times the signal passes through the first loop.

For a better understanding of the technical features and the contents of the present invention, reference should be made to the accompanying drawings and the accompanying drawings.

The embodiment of the invention provides a digital control oscillator with low cost, high frequency width and fast adjustment of the oscillation frequency. This digitally controlled oscillator can be used in a variety of systems or electronic devices that require high speed clock inputs.

[Example of Digital Control Oscillator]

Please refer to FIG. 1. FIG. 1 is a block diagram of a digitally controlled oscillator according to an embodiment of the present invention. The digitally controlled oscillator 1 includes an oscillating signal control circuit 10, a first delay circuit 12 and a second delay circuit 14. One of the input terminals of the oscillating signal control circuit 10 is electrically connected to the output terminal OUT1 of the first delay circuit 12, and the other input terminal of the oscillating signal control circuit 10 receives the predetermined number of times Y. The two output ends of the oscillating signal control circuit 10 are electrically connected to the input terminal IN1 of the first delay circuit 12 and the input terminal IN2 of the second delay circuit 14. The output terminal OUT2 of the second delay circuit 14 is electrically connected to the output of the digital control oscillator 1.

The first delay circuit 12 has a plurality of first delay units connected in series, and is electrically connected to the oscillation signal control circuit 10 to form an oscillation circuit, so that the first delay signal can be generated. The first delayed signal input is received by the oscillating signal control circuit 10, and the oscillating signal control circuit 10 determines to send the first delayed signal according to the number of times the first delayed signal is received, that is, the number of times the signal passes through the first delay circuit 12. To input IN1 or IN2. After the oscillating signal control circuit 10 determines to input the first delayed signal to the second delay circuit 14, the second delay circuit 14 outputs a second delayed signal to the output terminal OUT2 of the second delay circuit 14.

More specifically, the oscillating signal control circuit 10 determines whether the number of times the first delayed signal is received has reached a predetermined number of times Y. If the number of times the oscillating signal control circuit 10 receives the first delayed signal does not reach the predetermined number of times Y (ie, less than the predetermined number of times Y), the oscillating signal control circuit 10 determines to input the first delayed signal to the input terminal IN1 of the first delay circuit 12. . If the number of times the oscillating signal control circuit 10 receives the first delayed signal reaches the predetermined number of times Y (that is, greater than or equal to the predetermined number of times Y), the oscillating signal control circuit 10 determines to input the first delayed signal to the second delay circuit 14, and The second delay circuit 14 outputs a second delay signal to the output terminal OUT2 of the second delay circuit 14 according to the first delay signal it receives. In addition, the second delay signal outputted by the second delay circuit 14 may be directly used as a clock signal of the electronic chip, or may be used as a clock signal of the electronic chip after being processed by other circuits.

The digitally controlled oscillator 1 is controlled by the oscillation signal control circuit 10 so that the first delayed signal is output to the input terminal IN2 of the second delay circuit 12 after being passed through the first delay circuit 12 for Y times. Thereby, it is possible to reduce the total number of delay units, thereby reducing the gate delay of the second delayed signal.

In addition, since the preset number Y can be defined by the user, the oscillation frequency of the second delayed signal output by the digital control oscillator 1 at the output terminal OUT2 can be adjusted by changing the preset number Y, and The total number of delay units can be reduced, and the bandwidth of the second delayed signal (the range of the oscillation frequency) can be boosted.

In addition, it is worth mentioning that the plurality of first delay units of the first delay loop 12 are circuits composed of a plurality of logic gates, and the plurality of first delay units may be different from each other. Likewise, the plurality of second delay units of the second delay loop 14 are circuits composed of a plurality of logic gates, and the plurality of second delay units may be different from each other. In addition to this, the first and second delay units can be designed to receive delay control signals. The delay generated by the first delay signal passing through the first delay loop 12 and the second delay loop is controlled by the delay control signal, whereby the oscillation frequency of the second delay signal can be adjusted. In other words, the oscillation frequency of the second delayed signal can be adjusted by delaying the control signal.

Please note that although the above description mentions that the user can adjust the oscillation frequency of the second delay signal by changing the preset number Y and the delay control signal received by the second delay circuit 12, the preset number of times Y is changed to adjust the number. The manner of oscillating the frequency of the delayed signal belongs to the oscillating frequency adjustment mode of the coarse tune phase, and the manner of changing the swaying frequency of the second delayed signal by adjusting the delay control signal received by the second delay circuit 12 is fine-tuned. (fine tune) phase of the oscillation frequency adjustment method.

In other embodiments, the first delay loop 12 may be provided with an inverter before the output terminal OUT1 except for a plurality of first delay units composed of a plurality of logic gates. In addition, the second delay circuit 14 may be provided with a gate for receiving the window signal before the output terminal OUT2, in addition to the first delay unit composed of a plurality of logic gates, wherein the window signal is used to control the digital oscillation control. Whether the device 1 outputs the second delayed signal. In addition, the digital control oscillation controller 1 may further include an inverter and a buffer disposed after the output terminal OUT2, and even the digital control oscillation controller 1 is further capable of having a feedback circuit for feeding back the second delayed signal to The signal control circuit 10 is oscillated.

Please refer to FIG. 2. FIG. 2 is a block diagram of an oscillating signal control circuit according to an embodiment of the present invention. The oscillating signal control circuit 20 can be an embodiment of the oscillating signal control circuit 10 of FIG. The oscillating signal control circuit 20 includes a counter 22, latches 24 and 28. The input ends of the latching devices 34 and 38 are electrically connected to the output terminal OUT1 of the first delay circuit. The trigger terminals of the latching devices 24 and 28 are electrically connected to the counter 22, and the outputs of the latching devices 24 and 28 are electrically connected to the first. And the input terminals IN1 and IN2 of the second delay loop. One input of the counter 22 is electrically connected to the output terminal OUT1 of the first delay loop, and the other input of the counter 22 is received a predetermined number of times Y.

The counter 22 is used to count the number of times the oscillating signal control circuit 20 receives the first delayed signal. The counter 22 generates control signals to the trigger terminals of the latches 24 and 28 in accordance with the number of times the oscillating signal control circuit 20 receives the first delayed signal and the predetermined number of times Y. When the number of times the oscillating signal control circuit 20 receives the first delayed signal is less than the predetermined number of times Y, the latches 24 and 28 are respectively turned on and off, so that the first delayed signal is again input to the first delay loop. When the number of times the oscillating signal control circuit 20 receives the first delayed signal is greater than or equal to the predetermined number of times Y, the latches 24 and 28 are respectively turned off and on, so that the first delayed signal is input to the second delay loop.

[Another embodiment of the digitally controlled oscillator]

Please refer to FIG. 3. FIG. 3 is a block diagram of a digitally controlled oscillator according to another embodiment of the present invention. The digitally controlled oscillator 3 includes a digital oscillation signal control circuit 30, a first delay circuit 32, a second delay circuit 34, a feedback circuit 36, an inverter 37, and a buffer 38. The two input ends of the oscillating signal control circuit 30 are electrically connected to the output terminal OUT1 of the first delay circuit 32 and the output terminal OUT2 of the second delay circuit 34, respectively, and the other input terminal of the oscillating signal control circuit 30 receives the predetermined number of times Y. . The two output ends of the oscillating signal control circuit 30 are electrically connected to the input terminal IN1 of the first delay circuit 32 and the input terminal IN2 of the second delay circuit 34, respectively, and the feedback signal input terminal of the oscillating signal control circuit is electrically connected to the feedback terminal. Output OUT3 of circuit 36. The input end of the inverter 37 is electrically connected to the output terminal OUT2 of the second delay circuit 34, and the output end of the inverter 37 is electrically connected to the input end of the feedback circuit. The input of the buffer 38 is electrically connected to the output of the inverter 37, and the output of the buffer 38 is electrically connected to the output of the digital control oscillator 2.

In the embodiment of FIG. 3, the second delay loop 34 can receive a plurality of delay control signals C1 CN CN from the outside, and the delay control signals C1 CN CN control the delay generated by the first delay signal through the second delay loop 34. In addition, the second delay circuit 34 can also receive the window signal WIN from the outside, wherein the window signal WIN is used to control whether the output terminal OUT2 of the second delay circuit 62 can output the second delay signal. However, it should be noted that the second delay loop 34 in the embodiment of FIG. 3 is not intended to limit the present invention, and as described above, the second delay loop 34 may also be designed not to be externally given the delay control signal C1. ~CN and the delay loop of the window signal WIN.

The first delay circuit 32 has a plurality of first delay units connected in series, and is electrically connected to the oscillation signal control circuit 30 to form an oscillation circuit, so that the first delay signal can be generated. If the number of times the oscillating signal control circuit 30 receives the first delayed signal does not reach the predetermined number of times Y (i.e., less than the predetermined number of times Y), the oscillating signal control circuit 30 determines to input the first delayed signal to the first delay circuit 32. If the number of times the oscillating signal control circuit 30 receives the first delayed signal reaches the predetermined number of times Y (that is, greater than or equal to the predetermined number of times Y), the oscillating signal control circuit 30 determines to input the first delayed signal to the second delay circuit 34, and The second delay circuit 34 outputs a second delay signal to the output terminal OUT2 of the second delay circuit 34 according to the first delay signal it receives. The second delayed signal output by the second delay loop 34 can pass through the inverter 37 and the buffer 38 as a clock signal of the electronic chip. In addition, the second delayed signal outputted by the second delay circuit 34 is also received by the oscillating signal control circuit 30 and sent to the input terminal IN1 of the first delay circuit 32.

In addition, the feedback circuit 36 is configured to generate a reset signal to the feedback signal input end of the oscillation signal control circuit 30 according to the second delay signal, and the oscillation signal control circuit 30 determines whether to re-count the reception according to the reset signal. The number of times the signal is delayed. In other words, the feedback circuit 36 is designed to generate a reset signal for the oscillating signal control circuit 30 to recount after the second delay signal is outputted from the output terminal OUT2 of the second delay circuit 34.

Please refer to FIG. 4. FIG. 4 is a block diagram of an oscillating signal control circuit according to another embodiment of the present invention. The oscillating signal control circuit 40 can be an embodiment of the oscillating signal control circuit 30 of FIG. The oscillating signal control circuit 40 includes a counter 42, a latch 44, and a multiplexer 48. The input end of the latching device 44 is electrically connected to the output end OUT1 of the first delay circuit, the trigger end of the latching device 44 is electrically connected to the counter 42 , and the output end of the latching device 44 is electrically connected to the input end IN2 of the second delay circuit. One input terminal of the counter 42 is electrically connected to the output terminal OUT1 of the first delay loop, the other input terminal of the counter 32 is received a predetermined number of times Y, and the counter 42 further has a feedback signal input terminal (reset signal input terminal). The output is connected to the output terminal OUT3 of the feedback circuit. The two input ends of the multiplexer 48 are electrically connected to the output terminals OUT1 and OUT2 of the first and second delay circuits, respectively. The input end of the multiplexer 48 is electrically connected to the input terminal IN1 of the first delay circuit, and is multiplexed. The control terminal of the device 48 is electrically connected to the counter 42.

The counter 42 is used to count the number of times the oscillating signal control circuit 40 receives the first delayed signal. The counter 42 generates a control signal and a selection signal to the trigger terminal of the latch 44 and the control terminal of the multiplexer 48 respectively according to the number of times the oscillating signal control circuit 40 receives the first delay signal and the predetermined number of times Y. When the number of times the oscillating signal control circuit 40 receives the first delayed signal is less than the predetermined number Y, the latch 44 is turned off, and the multiplexer 48 selects to output the first delayed signal from the output terminal OUT1 to the input terminal IN1. When the number of times the oscillating signal control circuit 40 receives the first delayed signal is greater than or equal to the predetermined number of times Y, the latch 44 is turned on, and the multiplexer 48 selects to output the second delayed signal from the output terminal OUT2 to the input terminal IN1. In addition, after the second delay circuit outputs the second delay signal to the output terminal OUT2, the feedback circuit receives the second delay signal and generates a reset signal accordingly. The counter 42 receives the reset signal and recounts the number of times the first delayed signal is received, depending on the reset signal.

Please refer to FIG. 5. FIG. 5 is a circuit diagram of a first delay loop according to an embodiment of the present invention. The first delay loop 50 can be used as one of the embodiments of the first delay loop of the above embodiment. The first delay loop 50 includes a plurality of first delay units 52 and inverters 33 connected in series. The output of the first delay unit 52 of each stage is electrically connected to the input of the first delay unit 52 of the subsequent stage, except that the output of the first delay unit 52 of the last stage is electrically connected to the input of the inverter 53. The input end of the first delay unit 52 of the first stage is electrically connected to the input end IN1, and the output end of the inverter 53 is electrically connected to the output end OUT1.

The first delay unit 52 includes an OR gate 521 and a AND gate 522. The two inputs of the AND gate 522 are used in this embodiment to receive a particular value, such as a logic zero, although it is to be noted that the invention is not limited thereto. The two input terminals of the OR gate 521 are electrically connected to the output end of the first delay unit 52, and the output end of the OR gate 521 is electrically connected to the output end of the first delay unit 52.

In addition, it should be noted that the foregoing embodiment of the first delay unit 52 is not intended to limit the present invention, and the first delay unit 52 of FIG. 5 is only one of the embodiments. In other words, the first delay unit 52 includes at least one logic gate, and the manner of connecting the logic gates in the first delay unit 52 is not limited.

Please refer to FIG. 6. FIG. 6 is a circuit diagram of a second delay loop according to an embodiment of the present invention. The second delay loop 60 can be used as one of the embodiments of the second delay loop of the above embodiment. The second delay loop 60 includes a plurality of cascaded second delay units 62 and gates 63. Each of the second delay units 62 has first to third inputs. The output of the second delay unit 62 of each stage is electrically connected to the first of the second delay unit 62 of the subsequent stage, except that the output of the second delay unit 62 of the last stage is electrically connected to one of the inputs of the gate 63. Input. The second input end of each of the second delay units 62 is electrically connected to the input terminal IN2. The first input of the second delay unit 62 of the first stage receives a particular value, such as a logic zero. The output end of the gate 63 is electrically connected to the output terminal OUT1. In addition, the other input terminal of the AND gate 63 receives the window signal WIN, and the third input terminal of each of the second delay units 62 can receive one of the plurality of delay control signals C1 CN CN.

The second delay unit 62 includes an OR gate 621 and a AND gate 622. The two input terminals of the gate 622 (ie, the second and third input terminals of the second delay unit 62) are electrically connected to the input terminal IN2 and receive one of the plurality of delay control signals C1 CN CN, respectively. The two input terminals of the OR gate 621 are electrically connected and the output end of the gate 622 is connected to the first input end of the first delay unit 62, and the output end of the OR gate 621 is electrically connected to the output end of the first delay unit 62. The second delay loop 62 controls whether the output terminal OUT2 can output the second delay signal according to the window signal WIN.

In addition, it should be noted that the embodiment of the second delay unit 62 is not intended to limit the present invention, and the second delay unit 62 of FIG. 6 is only one of the embodiments. In other words, the second delay unit 62 includes at least one logic gate, and the manner of connecting the logic gates in the second delay unit 62 is not limited.

Please refer to FIG. 7. FIG. 7 is a circuit diagram of a feedback circuit according to an embodiment of the present invention. The feedback circuit 70 can be used as one of the embodiments of the feedback circuit of the above embodiment. The feedback circuit 70 includes a mutex or gate 72 and a buffer module 74. Buffer module 74 has a plurality of buffers connected in series. The input end of the buffer module 74 is electrically connected to the input terminal IN3, and the output end of the buffer module 74 is electrically connected to one of the inputs of the mutex or gate 72. The other input of the mutex or gate 72 is electrically connected to the input terminal IN3, and the output of the mutex or gate 72 is electrically connected to the output terminal OUT3. The feedback circuit 70 can generate a reset signal according to the second delayed signal (such as the second delayed signal in the reverse direction of FIG. 3).

Through the above description, please continue to refer to FIG. 3, the oscillation frequency of the second delayed signal is a two-stage adjustment, and the two phases are a coarse adjustment phase and a fine adjustment phase, respectively. In the coarse adjustment phase, the user can set the predetermined number of times Y to roughly adjust the oscillation frequency of the second delayed signal. After the oscillation signal control circuit 30 receives the first delay signal for a predetermined number of times Y, the user can finely adjust the oscillation frequency of the second delay signal by changing the delay control signals C1 CN CN in the fine adjustment phase.

In addition, it should be noted that in the embodiment of FIG. 3, the inverter 37 can be moved to the feedback circuit 36 and the buffer 38 can be removed. In other words, the circuit after the output terminal OUT2 can be designed according to the needs of the user, and the feedback circuit 36 can also be designed according to the needs of the user.

[Embodiment of Electronic Device]

Please refer to FIG. 8. FIG. 8 is a block diagram of an electronic device according to an embodiment of the present invention. The electronic device 8 includes a digitally controlled oscillator 81, electronic wafers 82-84, and inverters 85-87. The electronic chip 82 is directly electrically connected to the digitally controlled oscillator 81. The electronic chip 83 is electrically connected to the digitally controlled oscillator 81 through the inverter 85, and the electronic chip 84 is electrically connected to the digitally controlled oscillator 81 through the inverters 86 and 87.

The digitally controlled oscillator 81 can be a digitally controlled oscillator of the previous embodiment or a digitally controlled oscillator that varies slightly in accordance with the teachings of the previous embodiments for generating a second delayed signal. The second delayed signal can be used to generate clock signals for the electronic wafers 82-84 such that the electronic wafers 82-84 can operate in accordance with the clock signals. In more detail, in this embodiment, the second delayed signal is directly used as the clock signal of the electronic chip 82. Further, the second delayed signal passes through the inverter 85 as a clock signal of the electronic chip 83, and the second delayed signal passes through the inverters 86, 87 as a clock signal of the electronic chip 84.

However, it is to be noted that the embodiment of Figure 8 is not intended to limit the invention. The back end of the digitally controlled oscillator 81 may also have other circuitry to process the second delayed signal, as well as the direct clock signal. In other embodiments, the inverters 85-87 may also be moved into the digitally controlled oscillator 81. In addition, the types and numbers of electronic wafers 82-84 are not intended to limit the invention.

[Possible efficacy of the embodiment]

In summary, the digital control oscillator in the embodiment of the present invention can greatly reduce the number of delay units (that is, reduce the number of logic gates and multiplexers) by designing a double delay loop. Accordingly, the digitally controlled oscillator has lower circuit design complexity and smaller circuit area than conventional digitally controlled oscillators.

In addition, the clock delay (generated by the second delayed signal) passes less delay, so that the high frequency portion of the oscillation frequency range of the clock signal can be boosted. In addition, by increasing the number of bits of the counter, it is also possible to increase the gate delay experienced by the clock signal, so that the low frequency portion of the oscillation frequency range of the clock signal can be reduced.

In addition to the above-mentioned possible effects, the digitally controlled oscillator can be turned on or off by the window signal control, so that the operating time of the digitally controlled oscillator can be reduced to reduce power consumption. In summary, the digitally controlled oscillator has the potential for low cost, low power consumption, high frequency bandwidth, and rapid adjustment of the oscillation frequency.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Therefore, the equivalent technical changes of the present invention and the contents of the drawings are included in the invention.

1, 3, 81. . . Digitally controlled oscillator

10, 20, 30, 40. . . Oscillating signal control circuit

12, 32, 50. . . First delay loop

14, 34, 60. . . Second delay loop

22, 42. . . counter

24, 28, 44. . . Door latch

36, 70. . . Feedback circuit

37, 53, 85-87. . . Inverter

38. . . buffer

48. . . Multiplexer

52. . . First delay unit

521, 621. . . Gate

522, 622, 63. . . Gate

62. . . Second delay unit

72. . . Mutual exclusion or gate

74. . . Buffer module

8. . . Electronic device

82~84. . . Electronic chip

1 is a block diagram of a digitally controlled oscillator in accordance with an embodiment of the present invention.

2 is a block diagram of an oscillating signal control circuit in accordance with an embodiment of the present invention.

3 is a block diagram of a digitally controlled oscillator in accordance with another embodiment of the present invention.

4 is a block diagram of an oscillating signal control circuit in accordance with another embodiment of the present invention.

FIG. 5 is a circuit diagram of a first delay loop according to an embodiment of the present invention.

FIG. 6 is a circuit diagram of a second delay loop according to an embodiment of the present invention.

Fig. 7 is a circuit diagram of a feedback circuit of an embodiment of the present invention.

Figure 8 is a block diagram of an electronic device in accordance with an embodiment of the present invention.

3. . . Digitally controlled oscillator

30. . . Oscillating signal control circuit

32. . . First delay loop

34. . . Second delay loop

36. . . Feedback circuit

37. . . Inverter

38. . . buffer

Claims (7)

A digitally controlled oscillator comprising: a first delay loop having a plurality of first delay units connected in series; a second delay loop having a plurality of second delay units connected in series; and an oscillating signal control circuit, The first delay signal is connected to the first delay circuit, and is configured to receive a first delay signal output by the first delay circuit, and output the first delay signal to the first according to the number of times the first delay signal is received. Or an input end of the second delay circuit; wherein when the oscillating signal control circuit inputs the first delay signal to the second delay circuit, the second delay circuit outputs a second delay signal to the digital control oscillator An output of the second delay circuit is further received by the oscillating signal control circuit and transmitted to the input end of the first delay circuit; wherein the digital control oscillator further comprises: a feedback circuit electrically connected to a feedback signal input end of the oscillation signal control circuit for generating a reset signal to the oscillation signal according to the second delay signal The feedback signal input end of the control circuit; wherein the oscillation signal control circuit determines whether to recount the number of times the first delay signal is received according to the reset signal; wherein the oscillation signal control circuit comprises: a latch device, according to a control signal Outputting the first delay signal to the input end of the second delay loop; a multiplexer that inputs the first or the second delayed signal to the input end of the first delay loop according to a selection signal; and a counter for counting the oscillating signal control circuit to receive the first delayed signal The number of times, the control signal and the selection signal are generated according to the number of times the oscillating signal control circuit receives the first delayed signal and a predetermined number of times. The digital control oscillator of claim 1, wherein the first delay circuit further comprises: an inverter, an input end of which is electrically connected to the output end of the first delay unit of the last stage, and An output end thereof is electrically connected to an output end of the first delay loop. The digital control oscillator of claim 1, wherein the second delay circuit further comprises: a gate, a first input terminal electrically connected to the second delay unit of the last stage, and a second The input end receives a window signal, and an output end is electrically connected to an output end of the second delay loop. The digitally controlled oscillator of claim 1, wherein the second delay units of the second delay circuit respectively receive a plurality of delay control signals, wherein the delay control signals are used to control the first delay signal. The delay generated by the second delay loop to thereby generate the second delay signal. The digitally controlled oscillator of claim 1, further comprising: an inverter electrically coupled between the feedback circuit and the second delay circuit for generating the second delay in the reverse direction A signal is sent to the feedback circuit. The digital control oscillator of claim 5, wherein the feedback circuit comprises: a buffer module having a plurality of serially connected buffers, wherein an input end receives the reversed second delayed signal And a mutual exclusion or gate, an output end of the output signal is electrically connected to the feedback signal input end of the oscillation signal control circuit, and a first input end receives the reversed second delay signal, and a second input The terminal is electrically connected to an output end of the buffer module. An electronic device comprising: at least one electronic chip for receiving a clock signal generated according to a second delay signal for operation; and a digital control oscillator comprising: a first delay loop having a plurality of serial connections a first delay unit; a second delay loop having a plurality of second delay units connected in series; and an oscillating signal control circuit electrically coupled to the first and second delay loops for receiving the first delay a first delay signal output by the loop, and determining, according to the number of times the first delay signal is received, outputting the first delay signal to an input end of the first or second delay loop; wherein the oscillation signal control circuit After the first delay signal is input to the second delay loop, the second delay loop outputs the second delay signal to an output of the digitally controlled oscillator; wherein the second delay signal output by the second delay loop is further Be Receiving, by the oscillating signal control circuit, and transmitting to the input end of the first delay circuit; wherein the digital control oscillator further comprises: a feedback circuit electrically connected to a feedback signal input end of the oscillating signal control circuit And generating, by the second delay signal, a reset signal to the feedback signal input end of the oscillation signal control circuit; wherein the oscillation signal control circuit determines, according to the reset signal, whether to recount the receiving the first delayed signal The oscillating signal control circuit includes: a latching device that outputs the first delayed signal to the input end of the second delay circuit according to a control signal; a multiplexer that the first or the first signal according to a selection signal The second delay signal is input to the input end of the first delay loop; and a counter is configured to count the number of times the oscillating signal control circuit receives the first delay signal, and the control circuit receives the first delayed signal according to the oscillating signal The number of times and the predetermined number of times produces the control signal and the selection signal.