JP2003008435A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit that can properly obtain an oscillation output clock whose frequency is multiplied with a non-integer multiple. SOLUTION: The PLL circuit is provided with; a VCO circuit 4 that has a plurality of delay elements, generates an oscillation signal as an output and a feedback clock signal; and a phase comparator 2 that compares phases of the feedback clock signal and a reference clock signal and provides its output to the VCO circuit 4. The PLL circuit selectively extracts a phase clock signal among a plurality of phase clock signals respectively generated by a plurality of delay elements in the VCO circuit 4 and uses the selected phase clock signal to obtain the oscillation output clock whose frequency is multiplied with a non-integer multiple.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit, and more particularly to a PLL (Phase_Phase_) incorporated in a semiconductor integrated circuit.
In the Locked_Loop circuit, the present invention relates to a PLL circuit that performs non-integer multiplication on a reference clock.

[0002]

2. Description of the Related Art In recent years, as LSI systemization has progressed,
The number of cases where functions such as various media are incorporated in one LSI is increasing, and the number of LSIs having a plurality of different operating frequencies is increasing. Under such circumstances, there is a great demand for a PLL circuit that generates a clock frequency that is a non-integer multiplication of the frequency of a certain operation clock.

FIG. 13 shows a conventional non-integer multiplication.
PLL with voltage controlled oscillator (hereinafter referred to as VCO)
It shows a circuit. In the figure, 101 is an input terminal for inputting a reference clock, 102 is a frequency dividing circuit for dividing the reference clock by N, 103 is a phase comparator, 104 is a low-pass filter, and 105 is a VCO (Voltage_Con).
controlled_Oscillator), 106 is V
A frequency divider circuit that divides the oscillation clock of CO: 105 by M,
The feedback clock is output to the phase comparator 103. 10
Reference numeral 7 is an output terminal.

In this conventional PLL circuit, when the input frequency of the reference clock is Fin and the output frequency is Fout, an output frequency of Fout = (M / N) * Fin can be obtained. That is, a clock of M / N multiplication can be generated.

However, the frequency dividing values M and N are integer values, and when N becomes a large value, the input clock frequency to the phase comparator becomes remarkably low, which causes deterioration of the jitter characteristic of the PLL.

FIG. 14 shows another conventional example. The feature of this example is that the input frequency of the phase comparator: 103a is not low, but the frequency of the oscillation clock of the VCO: 105a is M.
The frequency is increased to the multiplication and then divided by N, and output Fou
This is a method for realizing M / N multiplication at t: 107a.

However, if the M value is large, VCO: 105a
It is conceivable that the design margin is reduced due to the increase in the oscillating frequency and the lack of the margin of the transistor capability, which adversely affects the manufacturing quality or the yield.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to obtain a PLL circuit which can properly obtain a non-integer multiple oscillation output.

[0009]

A PLL according to the first invention.
The circuit has a plurality of delay elements, generates an oscillation signal as an output, and compares the phase of the feedback clock signal and the reference clock signal with the voltage controlled oscillation means provided for generating the feedback clock signal. And a phase comparison means for supplying an output to the voltage controlled oscillation circuit, selectively extracting a plurality of phase clock signals respectively generated by a plurality of delay elements in the voltage controlled oscillation means, and using them as feedback clock signals. By using it, a non-integer multiple oscillation signal output is obtained.

In the PLL circuit according to the second aspect of the present invention, there is provided a plurality of delay elements, which generates an oscillation signal as an output and which is provided for generating a feedback clock signal, and the feedback clock. A plurality of phase clock signals respectively generated by a plurality of delay elements in the voltage controlled oscillation means, the phase controlled means comparing the phase of the signal and the reference clock signal and supplying an output to the voltage controlled oscillation means. Is selectively output to output a non-integer multiple oscillation signal.

In the PLL circuit according to the third aspect of the present invention, in the second aspect of the present invention, a plurality of sets of phase clock signals are independently and selectively taken out so that different phase / frequency clock signals are output from a single PLL circuit. Is output.

In the PLL circuit according to a fourth aspect of the invention, in the first or second aspect of the invention, an output signal is obtained by extracting a plurality of phase clocks generated by the voltage controlled oscillation means at different timings. It is the one.

A PLL circuit according to a fifth aspect of the present invention is the PLL circuit according to any one of the first to fourth aspects, wherein the predetermined clock signal is selectively extracted from the plurality of phase clock signals.
Selecting means for selectively extracting a predetermined phase clock signal by the selecting control signal, and causing the selecting operation by the selecting means to perform the selecting operation, and successively selecting at the falling edge of the clock signal selected by the selecting means And a phase clock selection control means for updating the control signal.

In the PLL circuit according to the sixth invention, in the first to fifth inventions, selection control means for selecting the phase clock signal is provided, and a multiplication set value is externally applied to the selection control means. The variable multiplication setting can be performed.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. The first embodiment according to the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing the overall configuration of the first embodiment. FIG. 2 is a connection diagram showing the configuration of the VCO circuit according to the first embodiment. FIG. 3 is a connection diagram showing the configuration of the waveform shaping circuit according to the first embodiment. FIG. 4 is a block diagram showing the configuration of the phase clock selection circuit according to the first embodiment. FIG. 5 is a timing chart showing the operation in the first embodiment.

1 to 5 show the configuration and timing chart of the PLL circuit according to the first embodiment. In FIG. 1, 1 is a terminal for inputting a reference clock, 2 is a phase comparator for inputting a reference clock and a feedback clock, 3 is a low-pass filter, 4 is a plurality of inversions capable of outputting a plurality of phase clocks with equal periods. A VCO circuit having a delay element such as an element or a differential element. A selection circuit 5 receives a selection control signal and selects and outputs one clock phase among a plurality of phase clocks output from the VCO circuit 4 (hereinafter, this output signal is referred to as a selection phase clock), 6
Is a waveform shaping circuit that absorbs noise such as hazards that occur at the changing point of the selected phase clock output from the selection circuit 5 and outputs a shaped selection clock, and 7 is input with the shaped selection phase clock and responds to the desired clock multiplication. A frequency dividing circuit for performing a frequency division to generate a feedback clock to the phase comparator, 8 receives a selection phase clock, generates a selection control signal having a sequential periodicity at any edge of the clock, and selects the selection circuit 5 A phase clock selection control circuit that outputs this selection control signal, and 9 is an output terminal that outputs the oscillation clock of the VCO circuit 4.

FIG. 2 shows an example of the configuration of a ring oscillator in the VCO circuit 4, and in order to simplify the explanation of the operation, a VCO circuit which outputs a phase clock whose period is divided into 5 equal parts by 5 stages of inverting elements is shown. Shown as VCO circuit 4 '.

FIG. 3 shows, as an example, a waveform shaping circuit 6 composed of a delay element and an OR gate.

FIG. 4 shows an example of the phase clock selection control circuit according to the first embodiment, which is composed of a combinational circuit group and a flip-flop group.

FIG. 5 shows an example 7 for explaining the operation.
The phase clocks PHASE <0> to PHASE <4> output from the VCO circuit 5'when set to / 5 and the selection control signal of the phase clock selection control circuit 8 that outputs the selection control signal at the falling edge are phase clocks. The following is a timing chart of the output of the selection circuit 5 and the shaped selection phase clock.

Next, the operation of this embodiment will be described. In the description of this operation, for simplification, the case of 7/5 multiplication oscillation with respect to the reference clock will be described. First, in the PLL circuit, negative feedback control works in the PLL system so that the reference clock and the feedback clock input to the phase comparator 2 have the same phase and the same frequency. Therefore, the feedback clock is VCO
If the period of the oscillation clock is 7/5 times the period of the oscillation clock, the oscillation clock of 7/5 times the reference clock can be generated.

From the five phase clocks PHASE <0> to PHASE <4> output from the VCO circuit 4 ', one phase clock is extracted from the selection circuit 5 by the selection control signal generated by the phase clock selection control circuit 8. Be done. However, the value of the selection control signal is updated at the falling edge of this phase clock, and a new phase clock is selected. The order of the phase clocks to be selected in this embodiment is 0, 2, 2, 4, 4, 1, 1, 3, 3, 0, 0,
2, 2, ... Since this order is cyclic, the phase clock selection control circuit 8 can easily design the sequence of the selection control signals with the configuration of the combination circuit and the flip-flop.

Here, the output of the selection circuit 5 is a clock waveform having a period which is 7/5 times the period of the VCO oscillation clock as shown in FIG. However, since noise is generated at the switching timing of H, noise is absorbed by the delay element and the logical sum element of the waveform shaping circuit 6 ′, and the shaped clock is output. This clock is already VCO
Since the frequency is divided by 7/5 with respect to the oscillation clock, the phase comparator 2 is directly used as the feedback clock without passing through the frequency dividing circuit 7.
By inputting into, a 7/5 multiplication circuit is realized. For example,
When the desired number of oscillation multiplications is 14/5, if the frequency dividing circuit 7 is set to divide by 2, the feedback clock becomes 14
It becomes / 5 frequency division, and 14/5 multiplication oscillation can be realized.

According to the conventional method, the clock input to the phase comparator needs to be divided by 5 with respect to the reference clock in order to multiply by 7/5. It can be directly input to the phase comparator, and good VCO oscillation characteristics can be obtained without lowering the input frequency of the reference clock.

In addition, as a conventional method, the reference clock is directly used as the input frequency and once the VCO oscillation is performed.
There is a method of multiplying by 4 and dividing by 10 before output.
Although a high oscillating frequency is required, in the first embodiment, the VCO oscillating frequency is 7/5 multiplication with respect to the reference clock, so that oscillation can be easily performed.

According to the first embodiment of the present invention, the delay element including a plurality of inverting elements or differential elements is provided,
A VCO circuit 4'provided to generate an oscillation signal as an output and a feedback clock signal.
The voltage-controlled oscillating means composed of the VCO circuit 4 whose configuration is shown in FIG. 2 is compared with the phase of the feedback clock signal and the reference clock signal, and the output is supplied to the voltage-controlled oscillating means composed of the VCO circuit 4. And a phase comparison means composed of a phase comparator 2 for the purpose of selectively outputting a plurality of phase clock signals respectively generated by a plurality of delay elements in the voltage controlled oscillation means composed of the VCO circuit 4 into a feedback clock signal. Since the non-integer multiple oscillation signal output is obtained by using the non-integer multiple oscillation signal, the non-integer multiple oscillation output can be appropriately obtained by using a plurality of phase clock signals in the voltage controlled oscillation means composed of the VCO circuit 4 as feedback clock signals. It is possible to obtain a PLL circuit that can be obtained.

According to the first embodiment of the present invention, in a circuit for selectively extracting a predetermined clock signal from a plurality of phase clock signals, a selection circuit for selectively extracting a predetermined phase clock signal by a selection control signal. 5 and the selection control signal causes the selection circuit to perform the selection operation, and the selection control is sequentially performed at the falling edge of the clock signal selected by the selection circuit 5. Since the phase clock selection control means including the phase clock selection circuit 8 for updating the signal is provided, by updating the selection control signal at the falling edge of the selected clock signal,
P that can obtain a non-integer multiple oscillation output properly and accurately
An LL circuit can be obtained.

Embodiment 2. A second embodiment according to the present invention will be described with reference to FIGS. FIG. 6 is a block diagram showing the overall configuration of the PLL circuit according to the second embodiment. FIG. 7 is a timing chart showing the operation of the PLL circuit according to the second embodiment.

6 and 7 show P according to the second embodiment.
The structure and timing chart of the LL circuit are shown. In FIG. 6, 1a is a terminal for inputting a reference clock, 2a is a phase comparator for inputting a reference clock and a feedback clock, 3a is a low-pass filter, 4a is a plurality of inversions capable of outputting a plurality of phase clocks with equal periods. A VCO circuit having a delay element such as an element or a differential element. A selection circuit 5a receives a selection control signal and selects and outputs a selected phase clock from the phase clock of the VCO circuit 4a, and 7a inputs one oscillation clock output from the VCO and divides the phase according to a desired multiplication. A frequency dividing circuit for generating a feedback clock to the comparator, 8a receives a selected phase clock, and a phase clock selection control circuit for generating a control signal of the successive selection circuit 5a at the edge of the clock, 10a is a clock for the selected phase clock. A frequency dividing circuit for making the duty 50%, 9a is an output terminal of the clock output from the frequency dividing circuit 10a.

FIG. 7 shows 5 as an example for explaining the operation.
The phase clocks of the phase clocks PHASE <0> to PHASE <4> output from the VCO circuit 4a and the selection control signal of the phase clock selection control circuit 8a which outputs the selection control signal at the rising edge are phase clocks. The timing chart of the waveform represented by the selection number and the output waveform of the selection circuit 5a is shown.

Next, the operation of this embodiment will be described. In the description of this operation, for simplification, an example of obtaining a 5/4 multiplied output clock with respect to the reference clock will be described. First,
The frequency divider circuit 7a for feedback is set to divide by two. With this setting value, the VCO oscillation clock is 2
A multiplied frequency clock is generated. Five phase clocks PHASE <0> to PHA output from the VCO circuit 4a
From SE <4>, one phase clock is extracted from the selection circuit 5a by the selection control signal generated by the phase clock selection control circuit 8a. However, the value of the selection control signal is updated at the rising edge of this phase clock and a new phase clock is selected. In this embodiment, the order of the phase clocks to be selected is 4, 3, 2, 1,
0, 4, 3, 2, 1, 0 ... Since this order has cyclicity, the sequence of selection control signals can be easily designed in the phase clock selection control circuit 8a.

Here, the selected phase clock from the selection circuit 5a outputs a clock waveform having a period of 5/4 times the period of the VCO oscillation clock as shown in FIG. Since the frequency divider circuit 7a is set to divide by two, the cycle of the feedback clock input to the phase comparator 2a is 10/4 times the cycle of the VCO oscillation clock. Therefore, the reference clock is multiplied by 10/4. Finally, in order to set the clock duty to 50%, the frequency divider circuit 10a divides the frequency by 2 to realize 5/4 multiplication.

In the conventional method, the clock input to the phase comparator needs to be divided by 4 with respect to the reference clock in order to multiply by 5/4, whereas in the second embodiment, the reference clock is used. It is possible to directly input to the phase comparator without dropping the frequency, and it is possible to obtain a good VCO oscillation characteristic.

If the conventional method uses the input clock as it is as the reference clock, the VCO oscillation must be multiplied by 10 and divided by 8 before output, which requires a high oscillation frequency. However, the second embodiment
Then, since the VCO oscillation frequency is doubled with respect to the reference clock, it is possible to oscillate reasonably.

According to the second embodiment of the present invention, it has a delay element composed of a plurality of inverting elements or differential elements,
In addition to generating an oscillating signal as an output, a voltage controlled oscillating means including a VCO circuit 4a provided for generating a feedback clock signal is compared with the phase of the feedback clock signal and the reference clock signal to output the VCO circuit. Four
a phase comparator 2 comprising a phase comparator 2 for supplying the voltage-controlled oscillation means a.
Since the non-integer multiple oscillation signal is output by selectively taking out the plurality of phase clock signals respectively generated by the plurality of delay elements in the voltage control oscillating means consisting of a, the voltage control consisting of the VCO circuit 4 is provided. By using a plurality of phase clock signals in the oscillating means as output signals, it is possible to obtain a PLL circuit that can appropriately obtain a non-integer multiple oscillation output.

Embodiment 3. A third embodiment according to the present invention will be described with reference to FIG. FIG. 8 is a block diagram showing the configuration of the PLL circuit according to the third embodiment.

FIG. 8 shows the configuration of the PLL circuit according to the second embodiment. In FIG. 8, 4b is a VCO circuit that outputs a plurality of phase clocks similar to the VCO circuits 4 (4 ′) and 4a in the first and second embodiments.
5b1 is a selection circuit [1] for selecting one from a plurality of phase clocks output from the VCO circuit 4b, and 5b2 is a selection circuit [1]: a plurality of phase clocks output from the VCO circuit 4b, similar to 5b1. Of the selection circuits [2] and 8b1 for selecting one from the selection circuits [1]: 5b1 and a phase for generating the selection control signal of the successive selection circuit [1]: 5b1 at the edge of the clock The clock selection control circuits [1] and 8b2 are phase clock selection control circuits [2] that generate selection control signals for the sequential selection circuits [2]: 5b2, similar to the phase clock selection control circuits [1]: 8b1. .

Next, the operation of this embodiment will be described. In this embodiment, two selection circuits that select the phase clock output from the VCO circuit 4b are independently set, a plurality of desired selection phase clocks are generated, and each outputs a clock of non-integer multiplication. In the method, by having two selection circuits and a phase clock selection control circuit that controls each of the selection circuits in parallel with the output unit, two clocks can be independently generated at the same time.

In this way, two sequences of clocks having different phases and frequencies are combined into one PLL by setting the sequence of the selection signal in the phase clock selection control circuit as desired and setting two different values. Can be realized with.

According to the third embodiment of the present invention, a delay element including a plurality of inverting elements or differential elements is provided,
In addition to generating an oscillating signal as an output, a voltage controlled oscillating means including a VCO circuit 4a provided for generating a feedback clock signal is compared with the phase of the feedback clock signal and the reference clock signal to output the VCO circuit. Four
a phase comparator 2 comprising a phase comparator 2 for supplying the voltage-controlled oscillation means a.
a non-integer multiple oscillation signal is output by selectively extracting a plurality of phase clock signals respectively generated by a plurality of delay elements in the voltage controlled oscillating means consisting of a. By selectively extracting multiple clock signals independently, a single PLL
Since different phase / frequency clock signals are output from the circuit, a plurality of sets of phase clock signals in the voltage controlled oscillating means composed of the VCO circuit 4 are independently taken out and used as output signals. It is possible to obtain a PLL circuit that can appropriately obtain a double oscillation output.

Fourth Embodiment A fourth embodiment according to the present invention will be described with reference to FIGS. 9 and 10. FIG. 9 is a block diagram showing the configuration of the fourth embodiment. FIG. 10 is a timing chart showing the operation in the fourth embodiment.

9 and 10 show a PL according to the fourth embodiment.
The structure of an L circuit and the timing chart of each point are shown. Figure 9
4c is a VCO circuit that outputs a plurality of phase clocks similar to the VCO circuits 4 (4 ′) and 4a in the first and second embodiments, and 5c1 is a VCO circuit 4c.
The selection circuits [1] and 5c2 for selecting one from the plurality of phase clocks output from the same select one from the plurality of phase clocks output from the VCO circuit 4c, like the selection circuit [1]: 5c1. The selection circuits [2] and 8c for selecting receive the selection clock output from the selection circuit [2]: 5c2,
The selection control signal of the selection circuit [1]: 5c1 is sequentially generated at one edge of the clock, and the selection circuit [2]: 5c2 is further generated.
3 is a phase clock selection control circuit for generating the selection control signal of FIG.

FIG. 10 shows the first embodiment for explaining the operation.
As the same example as above, PHASE <0> to when the selected phase clock is 7/5 times the cycle of the VCO oscillation clock.
PHASE <4>, selection circuit [1]: selection phase clock of 5c1, selection circuit [2]: selection phase clock of 5c2, phase clock selection control circuit [1]: selection control signal [1] of 8b1 ( The timing charts of the phase clock selection number) and the selection control signal [2] (phase clock selection number) of the phase clock selection control circuit [2]: 8b2 are shown.

As a condition similar to that of the first embodiment, the VCO
The operation in the case of outputting a clock having a cycle that is 7/5 times the cycle of the oscillation clock from the selection circuit 1 will be described. Phase clock selection control circuit 8c to selection circuit [2]: 5c2
The change timing of the phase selection sequence [2]
1 from the timing of the selection signal in FIG. 1D of the embodiment
The rising edge is used so that it becomes / 10 cycle earlier. Actual selection signal [2]: PHASE selection number of 5c2 is 2, 4, 4, 1, 1, 3, 3, 0, 0, 2, ...
And output in a circular order. On the other hand, the selection number of PHASE of the selection circuit [1]: 5c1 is 0, 2, 2, 4, 4, 1, 1, 3, at the same time as the selection signal [2].
Outputs 3, 0, .... Select circuit [1]: In 5c1,
At the change point of the phase selection number, the clock that is always selected does not change from "H" to "H", so that noise does not occur in the selected clock [1].

In this method, the output can be taken out with a simple timing design without using a waveform shaping circuit for adjusting the delay.

According to a fourth embodiment of the present invention, in the structure of the first to third embodiments, the V
With respect to the phase clocks PHASE <0> to PHASE <4> generated by the voltage controlled oscillator including the CO circuit 4c, a plurality of respective signals are selectively taken out at different timings to obtain an output signal. Therefore, it is possible to obtain the PLL circuit which can appropriately and easily obtain the non-integer multiple oscillation output by setting the timing.

Embodiment 5. The fifth embodiment according to the present invention will be described with reference to FIG. FIG. 11 is a timing chart showing the operation in the fifth embodiment. In the fifth embodiment, the configuration other than the peculiar configuration described here has the same configuration as that of the first embodiment and has the same operation.

According to the fifth embodiment, in the circuit configuration of the first embodiment, the output clocks for which the phases have been selected are alternately set to have different cycle widths, so that the oscillation clock of an intermediate cycle is output. explain. FIG. 11 shows a timing chart of main operating points according to the fifth embodiment. Referring to FIG. 11, using the circuit of the first embodiment, the sequence of the selection signal output from the phase clock selection control circuit 8 is 4, 3, 3, 2, 2, 1, 1, 0, 0,
... are output in order with periodicity. Here, the clocks that can be taken out from the selection circuit 5 are 4 / 5T, 1T, 4 in alternate cycles, where the cycle of the VCO oscillation frequency is 1T.
/ 5T, 1T, ...

In the case of such an output, in the phase comparator 2, the phase of the feedback clock always comes before or after the reference clock input from the input terminal 1. At this time, if the frequency response of the phase comparator 2 or the low-pass filter 3 is lowered, the voltage output to the VCO: 4 has an almost intermediate value, and the oscillation clock of the VCO: 4 is stable at 9/10 with respect to the reference clock. The multiplication can be oscillated.

By this method, a plurality of different frequencies are repeatedly taken out from the selection circuit, or the ratio of the different frequencies is changed, regardless of the number of stages of the inverting circuit forming the VCO ring oscillator in the VCO.
An oscillation clock having an arbitrary multiplication value can be generated relatively easily.

Sixth Embodiment A sixth embodiment according to the present invention will be described with reference to FIG. FIG. 12 is a block diagram showing the configuration of the sixth embodiment.

In the sixth embodiment, as an example of the phase clock selection control circuit, a circuit configuration in which the multiplication factor can be arbitrarily set from the outside will be described. FIG. 12 shows a block configuration of the phase clock selection control circuit according to the sixth embodiment. 8d1 is a clock terminal for inputting a selected phase clock output from the selection circuit, 8d2 is a group of state holding flip-flops for holding the internal state of this phase clock selection control circuit, and 8d3 is a selection control signal for holding the output selection control signal. A group of holding flip-flops, 8d4 is a group of input terminals for multiplying set value for giving a multiplying set value from the outside,
Reference numeral 8d5 is a combinational circuit for generating the value of the next selection control signal from the multiplication set value from the outside and the current internal state value and the value of the selection control signal, and 8d6 is the selection control signal output for outputting the selection control signal to the selection circuit. It is a terminal.

As shown in the first to fifth embodiments, VC
Various multiplication clocks could be output by setting the selection order of the selection control signal of the selection circuit for extracting the O phase clock to a desired value.

As shown in FIG. 12, by inputting the multiplication set value to the combination circuit 8d5, the next selection control signal is calculated from the values of the state holding flip-flop group 8d2 and the selection control signal holding flip-flop group 8d3.

According to this embodiment, it is possible to set the output of the desired multiplied clock by the external setting. Further, the non-integer multiple setting PLL enables fine adjustment of the output frequency after manufacturing.

According to the sixth embodiment of the present invention, in the configurations of the first to fifth embodiments, selection control means for selecting a phase clock signal is provided, and the multiplication set value is externally selected and controlled. Since it is possible to perform variable multiplication setting by giving it to the means, it is possible to appropriately obtain a non-integer multiple oscillation output, and it becomes possible to set the output of a desired multiplication clock by external setting, and to output the output frequency. It is possible to obtain a PLL circuit that enables fine adjustment later.

[0057]

According to the first aspect of the present invention, there is provided a plurality of delay elements to generate an oscillation signal as an output, and voltage control oscillation means provided to generate a feedback clock signal, and the feedback clock. A plurality of phase clock signals respectively generated by a plurality of delay elements in the voltage controlled oscillation means, the phase controlled means for comparing the phases of the signal and the reference clock signal and supplying an output to the voltage controlled oscillation circuit. Is selectively taken out and used as a feedback clock signal to obtain a non-integer multiple oscillation signal output. Therefore, by using a plurality of phase clock signals in the voltage controlled oscillating means for the feedback clock signal, It is possible to obtain a PLL circuit that can appropriately obtain an oscillation output.

According to the second aspect of the invention, there is provided a plurality of delay elements, which generates an oscillation signal as an output and is provided for generating a feedback clock signal, and the feedback clock signal. A phase comparison means for comparing the phase with a reference clock signal and supplying an output to the voltage controlled oscillation means, and selecting a plurality of phase clock signals respectively generated by a plurality of delay elements in the voltage controlled oscillation means Since the non-integer multiple oscillation signal is output by taking out the non-integer multiple oscillation signal, the non-integer multiple oscillation output can be appropriately obtained by using a plurality of phase clock signals in the voltage controlled oscillation means as output signals. The circuit can be obtained.

According to a third aspect of the present invention, in the second aspect, a plurality of sets of phase clock signals are independently and selectively taken out so that different phase signals are output from a single PLL circuit.
Since the frequency clock signal is output, a PLL circuit that can appropriately obtain a non-integer multiple oscillation output by using a plurality of sets of phase clock signals in the voltage controlled oscillator independently as independent output signals. Can be obtained.

According to a fourth invention, in the first or second invention, an output signal is obtained by extracting a plurality of phase clocks generated by the voltage controlled oscillation means at different timings. Therefore, it is possible to obtain the PLL circuit that can appropriately and easily obtain the non-integer multiple oscillation output by setting the timing.

According to a fifth aspect of the invention, in the circuit of the first to fourth aspects of the invention, in the circuit for selectively extracting a predetermined clock signal from a plurality of phase clock signals, the predetermined phase clock signal is selectively selected by a selection control signal. And a phase clock selection control means for causing the selection operation by the selection control signal to be performed by the selection means and for updating the selection control signal sequentially at the falling edge of the clock signal selected by the selection means. Since it is provided, it is possible to obtain the PLL circuit that can appropriately and appropriately obtain the non-integer multiple oscillation output by updating the selection control signal at the falling edge of the selected clock signal.

According to a sixth invention, in the first to fifth inventions, a selection control means for selecting the phase clock signal is provided, and a multiplication set value is externally given to the selection control means, whereby the variable multiplication is performed. Since the setting can be performed, the non-integer multiple oscillation output can be properly obtained, and the output of the desired multiplication clock can be set by the external setting, and the fine adjustment of the output frequency after manufacturing is also possible. The PLL circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration according to a first embodiment of the present invention.

FIG. 2 is a VCO according to the first embodiment of the present invention.
It is a block diagram which shows the structure of a circuit.

FIG. 3 is a block diagram showing a configuration of a waveform shaping circuit according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a phase clock selection control circuit according to the first embodiment of the present invention.

FIG. 5 is a timing chart showing an operation in the first embodiment according to the present invention.

FIG. 6 is a block diagram showing an overall configuration according to a second embodiment of the present invention.

FIG. 7 is a timing chart showing an operation in the second embodiment according to the present invention.

FIG. 8 is a block diagram showing a configuration in a third embodiment according to the present invention.

FIG. 9 is a block diagram showing a configuration in a fourth embodiment according to the present invention.

FIG. 10 is a timing chart showing an operation in the fourth embodiment according to the present invention.

FIG. 11 is a timing chart showing an operation in the fifth embodiment according to the present invention.

FIG. 12 is a block diagram showing a configuration in a sixth embodiment according to the present invention.

FIG. 13 is a block diagram showing a configuration of an example of a conventional technique.

FIG. 14 is a block diagram showing the configuration of another example in the related art.

[Explanation of reference numerals] 1,1a reference clock input terminal, 2,2a phase comparator, 3,3a low-pass filter, 4,4 ', 4a, 4
b, 4c VCO circuit, 5, 5a, 5b1, 5b2, 5
c1, 5c2 selection circuit, 6 waveform shaping circuit, 7 frequency divider circuit, 8, 8a8b1, 8b2, 8c phase clock selection control circuit, 9 oscillation clock output terminal.

Claims (6)

[Claims] 1. A voltage-controlled oscillating means having a plurality of delay elements for generating an oscillation signal as an output and for generating a feedback clock signal, and a phase of the feedback clock signal and a reference clock signal. And a phase comparison means for supplying an output to the voltage controlled oscillation circuit, selectively extracting a plurality of phase clock signals respectively generated by a plurality of delay elements in the voltage controlled oscillation means, and providing a feedback clock. A PLL characterized in that a non-integer multiple oscillation signal output is obtained by using it as a signal
circuit. 2. A voltage-controlled oscillator having a plurality of delay elements for generating an oscillation signal as an output and for generating a feedback clock signal, and a phase of the feedback clock signal and a reference clock signal. And a phase comparison means for supplying an output to the voltage controlled oscillation means and selectively extracting a plurality of phase clock signals respectively generated by a plurality of delay elements in the voltage controlled oscillation means. A PLL circuit characterized in that it outputs an integer multiple oscillation signal. 3. A plurality of sets of phase clock signals are independently and selectively taken out to output different phase / frequency clock signals from a single PLL circuit. The PLL circuit described in 1. 4. The output signal is obtained by extracting a plurality of phase clocks generated by the voltage controlled oscillator at different timings. PLL circuit. 5. A circuit for selectively extracting a predetermined clock signal from a plurality of phase clock signals, selecting means for selectively extracting a predetermined phase clock signal by a selection control signal, and selection by said selection means by a selection control signal. 2. The PLL circuit according to claim 1, further comprising: a phase clock selection control unit that operates and sequentially updates the selection control signal at a falling edge of the clock signal selected by the selection unit. . 6. A variable multiplication setting can be performed by providing selection control means for selecting a phase clock signal and externally supplying a multiplication setting value to the selection control means. The PLL circuit according to any one of claims 1 to 5.