CN109787619B - Multi-phase clock generation circuit - Google Patents
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Abstract
The invention provides a multi-phase clock generating circuit, comprising: m n-stage self-timing oscillation rings; the m n-stage self-timed oscillation rings are coupled. The invention is based on the all-digital design, has the comprehensive performances of good mobility between processes, area, power consumption and PVT resistance, and has the advantages of high resolution and strong noise resistance.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and in particular to a multi-phase clock generation circuit.
Background
A high resolution, multiphase clock signal generation circuit is required in many communication or signal processing systems, such as serial-to-parallel/serial conversion circuits in high speed interconnects, synthetic fractional clock modules in phase locked loops, high precision test and measurement circuits, and the like. Currently, there are three main methods for generating a multi-phase clock: (1) the multi-phase clock generating circuit based on the inverter chain has the main problems of large power consumption and low resolution; (2) a voltage controlled oscillator based on a phase interpolator can output a multi-phase clock with higher resolution, but is sensitive to process, voltage and temperature (PVT) variations; (3) the feedback-based voltage-controlled oscillator VCO can improve phase resolution and has better PVT change resistance, but the feedback-based voltage-controlled oscillator belongs to an analog circuit, has poor portability between processes, and has large circuit area and power consumption.
Patent document CN1897583A (application number: 200610043016.6) discloses a multiphase quadrature clock generating circuit for completing clock data recovery at the receiving end of a high-speed transceiver, which includes eight phase interpolation and selection circuits and one phase selection circuit. The phase interpolation and selection circuit divides a reference clock with 16-phase intervals pi/8 output by the PLL/VCO into 8 groups for phase interpolation, generates a clock with 32-phase intervals pi/16, performs phase selection through control signals SLC1_ I, I is 1,2,3 and 4, and generates clocks with 8-phase two groups and intra-group phase intervals pi/2, wherein CLK1,3,5,7, CLK2,4,6 and 8 respectively increases and decreases in phase according to the sequence valid in sequence of SLC1_1, SLC1_2, SLC1_3 and SLC1_4, and the step size is pi/16. When the SLC2_5 is effective, the phase of the output clock signal CLKI is between pi and 2 pi, the phases are sequentially decreased according to the sequence of SLC2_1, SLC2_2, SLC2_3 and SLC2_4 which are effective in sequence, and the step length is pi/4; when the SLC2_6 is effective, the phase of CLKI is between 0 and pi, and the phases are increased progressively according to the sequence of SLC2_1, SLC2_2, SLC2_3 and SLC2_4 which are effective in sequence, and the step size is pi/4.
Disclosure of Invention
In view of the drawbacks of the prior art, it is an object of the present invention to provide a multi-phase clock generation circuit.
According to the present invention, there is provided a multi-phase clock generating circuit comprising:
m n-stage self-timing oscillation rings;
the m n-stage self-timed oscillation rings are coupled.
Preferably, the n-stage self-timed oscillation ring comprises:
n multi-input miller units Muller C _ element;
the multi-input Miller unit Muller C _ element comprises: and a plurality of groups of inputs with the same function, wherein at least one group is used for generating an oscillating signal, and at least one group is used for coupling with other n-stage self-timing oscillating rings.
Preferably, the multi-input miller unit Muller C _ element:
the multi-input miller element Muller C _ element logical expression is as follows:
f is n sets of inputs of the same function: f1 ═ F2 ═ Fn
R is n groups of inputs with the same function: r1 ═ R2 ═ Rn
Wherein,
SET denotes the SET signal of the multi-input miller C _ element;
RESET represents the RESET signal of the multi-input miller C _ element;
c denotes the output of the multi-input miller unit Muller C _ element.
Preferably, the at least one set of same-function inputs:
and the output of one or more other Miller units Muller C _ element except the Miller unit with multiple inputs in the n-stage self-timing oscillation ring is connected, so that the n-stage self-timing oscillation ring with multiple inputs is connected with the Muller C _ element with multiple inputs.
Preferably, the at least one set of same-function inputs:
and the outputs of one or more multi-input Miller units C _ element in the other n-stage self-timing oscillation rings except the n-stage self-timing oscillation ring in the m n-stage self-timing oscillation rings are connected to couple the m n-stage self-timing oscillation rings.
Preferably, the at least one set of inputs is coupled to a further n-stage self-timed oscillation ring:
at least one set of inputs is connected to the outputs of different miller cells Muller C _ element.
Preferably, the multi-input miller cell Muller C _ element provides an initialization and configuration circuit;
the initialization and configuration circuit performs initialization configuration on the n-stage self-timing oscillation ring, and the self-timing oscillation ring is configured to generate different oscillation frequencies and oscillation waveforms.
Preferably, the n-stage self-timed oscillation ring generates n clock phases;
the m n-stage self-timed oscillation ring couplings produce m × n clock phases.
Preferably, the method further comprises the following steps:
and generating different clock phases by adjusting the number n of the self-timing oscillation rings and the number m of the self-timing oscillation rings.
Preferably, the number n of the self-timing oscillation ring is a positive integer greater than or equal to 3;
the number m of self-timed oscillation rings is a positive integer greater than or equal to 2.
Compared with the prior art, the invention has the following beneficial effects:
the invention is based on the full digital design, has the comprehensive performances of good mobility between the processes, area, power consumption and PVT resistance, and has the advantages of high resolution and strong noise resistance
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
fig. 1 is a schematic structural diagram of a high resolution multi-phase clock generating circuit according to the present invention.
Fig. 2 is a schematic diagram of a self-timed oscillation ring provided by the present invention.
Fig. 3 is a schematic structural diagram of a multi-input miller cell provided by the present invention.
FIG. 4 is a diagram of an embodiment of a multi-input Miller unit provided by the present invention.
Fig. 5 is a coupling diagram of the high resolution multi-phase clock generation circuit provided by the present invention.
Fig. 6 is a simulation diagram of the coupling of the high resolution multi-phase clock generation circuit provided by the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
According to the present invention, there is provided a multi-phase clock generating circuit comprising:
m n-stage self-timing oscillation rings;
the m n-stage self-timed oscillation rings are coupled.
Specifically, the n-stage self-timed oscillation ring comprises:
n multi-input miller units Muller C _ element;
the multi-input Miller unit Muller C _ element comprises: and a plurality of groups of inputs with the same function, wherein at least one group is used for generating an oscillating signal, and at least one group is used for coupling with other n-stage self-timing oscillating rings.
Specifically, the multi-input miller unit Muller C _ element:
the multi-input miller element Muller C _ element logical expression is as follows:
f is n sets of inputs of the same function: f1 ═ F2 ═ Fn
R is n groups of inputs with the same function: r1 ═ R2 ═ Rn
Wherein,
SET denotes the SET signal of the multi-input miller C _ element;
RESET represents the RESET signal of the multi-input miller C _ element;
c denotes the output of the multi-input miller unit Muller C _ element.
Specifically, the at least one set of same-function inputs:
and the output of one or more other Miller units Muller C _ element except the Miller unit with multiple inputs in the n-stage self-timing oscillation ring is connected, so that the n-stage self-timing oscillation ring with multiple inputs is connected with the Muller C _ element with multiple inputs.
Specifically, the at least one set of same-function inputs:
and the outputs of one or more multi-input Miller units C _ element in the other n-stage self-timing oscillation rings except the n-stage self-timing oscillation ring in the m n-stage self-timing oscillation rings are connected to couple the m n-stage self-timing oscillation rings.
In particular, the at least one set of inputs is coupled with other n-stage self-timed oscillation rings:
at least one set of inputs is connected to the outputs of different miller cells Muller C _ element.
Specifically, the multi-input miller cell Muller C _ element provides an initialization and configuration circuit;
the initialization and configuration circuit performs initialization configuration on the n-stage self-timing oscillation ring, and the self-timing oscillation ring is configured to generate different oscillation frequencies and oscillation waveforms.
Specifically, the n-stage self-timed oscillation ring generates n clock phases;
the m n-stage self-timed oscillation ring couplings produce m × n clock phases.
Specifically, the method further comprises the following steps:
and generating different clock phases by adjusting the number n of the self-timing oscillation rings and the number m of the self-timing oscillation rings.
Specifically, the number n of the self-timing oscillation ring is a positive integer greater than or equal to 3;
the number m of self-timed oscillation rings is a positive integer greater than or equal to 2.
The present invention will be described more specifically below with reference to preferred examples.
Preferred example 1:
aiming at the problems of resolution, power consumption, circuit area, PVT resistance and the like of the current high-resolution multiphase clock generation circuit, the invention generates the high-resolution clock by using a full-digital coupling self-timing oscillation ring, and the design is based on a full-digital design, so that the high-resolution multiphase clock generation circuit has the characteristics of good mobility among processes, good comprehensive performance of area, power consumption and PVT resistance, high resolution, strong noise resistance and the like.
The invention provides a design method of a high-resolution multi-phase clock generating circuit. The multi-phase clock generation circuit is generated by coupling m n-stage Self-timed oscillation rings (STRO). Where m represents the number of n stages of self-timed oscillation rings and n represents the number of stages of self-timed oscillation rings. The number of self-timed oscillation rings and the number of stages of the self-timed oscillation rings may be adjusted to produce different phases. Unlike other coupling modes using RLC, the multi-phase clock of the present invention is generated by different n-stage self-timing oscillation ring coupling. The n-stage self-timing oscillation ring can generate n clock phases, m independent self-timing oscillation rings are synchronized through coupling, and m multiplied by n clock phases are generated through coupling, so that the high-resolution clock is realized.
The n-stage self-timed oscillation ring generates a multi-phase clock signal. The number of the stages of the n-stage self-timing oscillation ring provided by the invention can be adjusted, so that clock signals with different oscillation frequencies and different phases are generated. The self-timing oscillation ring provided by the invention can control the working state of the oscillation ring by setting the initial state of the oscillation ring. Preferably, the oscillation ring should be set to a uniform propagation mode to obtain a higher clock frequency and produce a clock signal of uniform phase.
The n-stage self-timing oscillation ring is composed of n multi-input Miller units Muller C _ element.
The multi-input Miller unit Muller C _ element is composed of a plurality of groups of inputs with the same function, wherein at least one group is used for generating an oscillating signal, and at least one group is used for coupling with other self-timing oscillating rings.
And coupling between the self-timing oscillation rings is realized through a multi-input Miller unit Muller C _ element. The multi-input Miller unit Muller C _ element comprises a plurality of input signals with the same function, and different inputs with the same function are connected to the outputs of different Miller unit Muller C _ elements, so that the delay coupling and synchronization of the circuit are realized.
For example, m multi-input miller C _ elements (F0 … Fn, R0 … Rn, SET, RESET), where F0 and R0 of each miller C _ element are connected to each other to generate an m-stage self-timed oscillation ring, but F1 and R1 are used to connect to F1 and R1 of another self-oscillation ring, thereby generating a coupling effect. As shown in FIG. 5, Miller units Muller C _ element corresponding to C1/C2/C3 form a self-oscillation ring, Miller units Muller C _ element corresponding to C4/C5/C6 form a self-oscillation ring, F1/R1 of the C4/C5/C6 units are respectively connected to C4/C5/C6 (inside the oscillation ring), and F2/R2 is coupled to self-oscillation ring (another oscillation ring) composed of C1/C2/C3.
The conventional miller cell includes F, R, RESET, SET, and C signals, whose truth table is shown in table one, where F, R, SET, and RESET are inputs and C is an output. The invention provides a multi-input Miller cell concept for the first time. The input of the system is characterized by comprising F0 … Fn, R0 … Rn, SET, RESET and C signals. Where F0 … Fn performs the same logic function but has n different inputs. R0 … Rn implements the same logic function but has n different inputs.
Muller C _ element is a relatively common unit in an asynchronous circuit, and the most basic unit comprises two inputs and one output, as shown in the following table
| | R | C | |
| 0 | 0 | |
|
| 0 | 1 | 0 | |
| 1 | 0 | 1 | |
| 1 | 1 | Previous C |
The logic expression is as follows: c ═ C! (F ^ R)&C-1+(F^R)&F
Or alternatively, as shown in the following table
| | R | C | |
| 0 | 0 | 0 | |
| 0 | 1 | |
|
| 1 | 0 | |
|
| 1 | 1 | 1 |
The logic expression is as follows: c ═ F ^ R)&C-1+！(F^R)&F
The Muller C _ element will have Reset and Set ports in use, and the truth table of the Muller C _ element is shown below after adding the Reset and Set signals, taking the first way as an example:
the logic expression is as follows:
the multi-input Muller C _ element in the invention is characterized in that the multi-input Muller C _ element has a plurality of F inputs and a plurality of R inputs, and the truth table of the multi-input Muller C _ element is
The logic expression is as follows:
wherein F0 ═ F1 ═ Fn, R0 ═ R1 ═ Rn
The multi-input Miller unit Muller C _ element provides an initialization and configuration circuit which is used for carrying out initialization configuration on the n-stage self-timing oscillation ring and configuring the self-timing oscillation ring to generate different oscillation frequencies and oscillation waveforms.
Preferred example 2:
fig. 1 is a schematic structural diagram of a high resolution multi-phase clock generation circuit of the present invention, which includes m n-stage self-timed oscillation ring circuits. The M n-stage self-timing oscillation ring circuits are coupled with each other to form a high-resolution multi-phase clock generation circuit. Where the number of m and n is adjusted according to the number of clock phases required, and the frequency of the clock.
Fig. 2 is a self-timing oscillation ring in the present invention, which is composed of n stages of multi-input miller cell Muller C _ elements, where n is a positive integer greater than or equal to 3. In a self-timing oscillation ring composed of a multi-input Miller unit Muller C _ element, two states of a bubble and a token exist according to the principle of a self-timing circuit. Wherein token is defined as the output C in the i stage of the oscillation ringiOutput C not equal to the previous stagei-1The state of (1). Bubble is defined as the output C in the oscillating ring i stageiEqual to the output C of the previous stagei-1The state of (1). The self-timed oscillation loop can produce autonomous oscillation when three conditions are met. These three conditions are: (1) the number n of the oscillating ring stages is more than or equal to 3; (2) the number of bubbles in the oscillation ring should be more than or equal to 1; (3) the number of tokens in the oscillation ring is a positive even number.
The multi-input miller C _ element is shown in fig. 3, and the miller C _ element in the present invention has multiple sets of inputs with the same function. Where F11 through F1n are inputs for n sets of identical functions. R11 through R1n are also n sets of inputs for the same function. One of the main features of the multi-input miller C _ element distinction of the present invention from miller C _ element is the use of multi-input miller C _ element.
As shown in fig. 3, the multi-input miller C _ element includes set and reset signals, which can be used to adjust the initial state of the oscillation loop and set the oscillation mode of the oscillation loop. The ring has two modes of propagation: uniformly spaced propagation modes and burst propagation modes. If the difference between the number of bubbles and the number of tokens in the initial state of the oscillation ring is smaller, the greater the physical effect in the miller cell Muller C _ element is, the higher the output clock frequency is, and the oscillation ring is in the uniform interval propagation mode. If the difference between the number of bubbles and the number of tokens in the initial state of the oscillation ring is larger, the smaller the Charpy effect in the Miller unit Muller C _ element is, the lower the frequency of the output clock is, and the oscillation ring is in a burst propagation mode at the moment. The frequency of the uniformly spaced propagation modes is higher with the same number of stages. In the above way, in the initial configuration, the oscillation mode and the frequency adjustment of the input clock in the self-timing oscillation ring can be realized.
FIG. 4 is a specific embodiment of the multi-input Miller unit Muller C _ element of the present invention, which includes two sets of identical inputs F1 and F2, R1 and R2. The truth table of Miller Unit Muller C _ element is shown in Table 1
Table one, multiple input miller cell truth table
The miller cell Muller C _ element has many circuit configurations, and this embodiment is only an example, and the present invention is not limited to the implementation method shown in fig. 4.
Fig. 5 is an embodiment of the present invention. In an embodiment comprising 3 stages of self-timed oscillating rings. By the coupling method provided by the invention, 3 multiplied by 3 clock phases are generated by coupling, thereby realizing a multi-phase clock. The design is based on a full-digital design, and has the characteristics of good mobility among processes, good comprehensive performance of area, power consumption and PVT (physical vapor transport) resistance, high resolution and the like. Fig. 6 is a simulation of the high resolution multi-phase clock generation circuit of the present invention, which can generate 9-phase clocks for the circuit configuration of fig. 5.
Those skilled in the art will appreciate that, in addition to implementing the systems, apparatus, and various modules thereof provided by the present invention in purely computer readable program code, the same procedures can be implemented entirely by logically programming method steps such that the systems, apparatus, and various modules thereof are provided in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system, the device and the modules thereof provided by the present invention can be considered as a hardware component, and the modules included in the system, the device and the modules thereof for implementing various programs can also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (8)
1. A multi-phase clock generation circuit, comprising:
m n-stage self-timing oscillation rings;
the m n-stage self-timed oscillation ring couplings;
the n-stage self-timed oscillation ring comprises:
n multi-input miller units Muller C _ element;
the multi-input Miller unit Muller C _ element comprises: a plurality of groups of inputs with the same function, wherein at least one group is used for generating an oscillating signal, and at least one group is used for coupling with other n-stage self-timing oscillating rings;
the multi-input Miller unit Muller C _ element:
the multi-input miller element Muller C _ element logical expression is as follows:
f is n sets of inputs of the same function: f1 ═ F2 ═ Fn
R is n groups of inputs with the same function: r1 ═ R2 ═ Rn
Wherein,
^ represents an exclusive or logic;
SET denotes the SET signal of the multi-input miller C _ element;
RESET represents the RESET signal of the multi-input miller C _ element;
c represents the output of the multi-input Miller unit Muller C _ element;
C-1representing the previous output value of the miller cell.
2. The multi-phase clock generation circuit of claim 1, wherein the at least one set of inputs for the same function:
and the output of one or more other Miller units Muller C _ element except the Miller unit with multiple inputs in the n-stage self-timing oscillation ring is connected, so that the n-stage self-timing oscillation ring with multiple inputs is connected with the Muller C _ element with multiple inputs.
3. The multi-phase clock generation circuit of claim 2, wherein the at least one set of inputs for the same function:
and the outputs of one or more multi-input Miller units C _ element in the other n-stage self-timing oscillation rings except the n-stage self-timing oscillation ring in the m n-stage self-timing oscillation rings are connected to couple the m n-stage self-timing oscillation rings.
4. The multi-phase clock generation circuit of claim 3, wherein the at least one set of inputs is coupled with other n-stage self-timed oscillator rings:
at least one set of inputs is connected to the outputs of different miller cells Muller C _ element.
5. The multi-phase clock generation circuit of claim 4, wherein the multi-input Miller cell Muller C _ element provides an initialization and configuration circuit;
the initialization and configuration circuit performs initialization configuration on the n-stage self-timing oscillation ring, and the self-timing oscillation ring is configured to generate different oscillation frequencies and oscillation waveforms.
6. The multi-phase clock generation circuit of claim 5, wherein the n-stage self-timed oscillation ring generates n clock phases;
the m n-stage self-timed oscillation ring couplings produce m × n clock phases.
7. The multi-phase clock generation circuit of claim 6, further comprising:
and generating different clock phases by adjusting the number n of the self-timing oscillation rings and the number m of the self-timing oscillation rings.
8. The multi-phase clock generation circuit of claim 7, wherein the number of stages n of the self-timed oscillation ring is a positive integer greater than or equal to 3;
the number m of self-timed oscillation rings is a positive integer greater than or equal to 2.
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