CN109787619B - Multi-phase clock generation circuit - Google Patents

Abstract

The present invention provides a multi-phase clock generating circuit, comprising: m n-stage self-timing oscillation loops; the m n-stage self-timing oscillation loops are coupled. The invention is based on all-digital design, has good mobility between processes, comprehensive performance of area, power consumption and anti-PVT characteristics, and has the advantages of high resolution and strong anti-noise.

Description

Multiphase Clock Generation Circuit

technical field

The present invention relates to the field of semiconductor integrated circuits, in particular to a multi-phase clock generation circuit.

Background technique

A high-resolution multiphase clock signal generation circuit is required in many communication or signal processing systems, such as serial-parallel/parallel-serial conversion circuits in high-speed interconnects, synthetic fractional clock modules in phase-locked loops, high-precision test and measurement circuits Wait. At present, there are three main methods for generating multi-phase clocks: (1) The multi-phase clock generation circuit based on the inverter chain has the main problems of high power consumption and low resolution; (2) The voltage-controlled oscillator based on the phase interpolator can Multiphase clock with higher output resolution, but sensitive to process, voltage and temperature (PVT) changes; (3) feedback-based voltage controlled oscillator VCO, which can improve phase resolution and has better resistance to PVT However, the feedback-based voltage-controlled oscillator belongs to the analog circuit, and the portability between processes is poor, and the circuit area and power consumption are large.

The patent document CN1897583A (application number: 200610043016.6) discloses a multi-phase quadrature clock generation circuit used for clock data recovery at the receiving end of a high-speed transceiver, including eight phase interpolation and selection circuits and one phase selection circuit. The phase interpolation and selection circuit divides the 16-phase phase interval Π/8 reference clocks output by the PLL/VCO into 8 groups for phase interpolation, generates 32-phase phase interval Π/16 clocks and passes the control signal SLC1_I, I=1,2 , 3, 4 for phase selection, to generate two groups of 8-phase clocks with a phase interval of Π/2, among which CLK1, 3, 5, 7, CLK2, 4, 6, 8 follow SLC1_1, SLC1_2, SLC1_3, SLC1_4 in order The valid sequential phases are incremented and decremented, respectively, with a step size of Π/16. The phase selection circuit selects the appropriate phase from the multi-phase quadrature clock under the action of the control signals SLC2_J, J=1, 2, L, 6: when SLC2_5 is valid, the phase of the output clock signal CLKI is between Π～2Π, according to SLC2_1 , SLC2_2, SLC2_3, SLC2_4 are valid in sequence, the phase is decreasing, and the step size is Π/4; when SLC2_6 is valid, the phase of CLKI is between 0 and Π. is Π/4.

SUMMARY OF THE INVENTION

In view of the defects in the prior art, the purpose of the present invention is to provide a multi-phase clock generating circuit.

A multi-phase clock generating circuit provided according to the present invention includes:

m n-stage self-timed oscillatory loops;

The m n-stage self-timed oscillating rings are coupled.

Preferably, the n-stage self-timed oscillating ring includes:

n multi-input Miller unit Muller C_element;

The multi-input Miller unit Muller C_element includes: multiple sets of inputs with the same function, at least one of which is used to generate an oscillating signal, and at least one of which is used to couple with other n-stage self-timed oscillating loops.

Preferably, the multi-input Miller unit Muller C_element:

The logical expression of Muller C_element of the multi-input Miller unit is as follows:

F is the input of n groups of the same function: F1=F2=....=Fn

R is the input of n groups of the same function: R1=R2=....=Rn

in,

SET represents the SET signal of the multi-input Miller unit Muller C_element;

RESET represents the RESET signal of the multi-input Miller unit Muller C_element;

C represents the output of the multi-input Muller element Muller C_element.

Preferably, the at least one set of inputs of the same function:

It is connected to the output of one or more other Miller C_elements except the multi-input Miller unit in the n-stage self-timed oscillation ring, so that the n multi-input denser elements in the n-stage self-timed oscillation ring are connected Le element MullerC_element connection.

Preferably, the at least one set of inputs of the same function:

It is connected with the output of one or more multi-input Miller units Muller C_element in other n-level self-timing oscillation rings except the n-level self-timing oscillation ring in the m n-level self-timing oscillation rings, so that m n-stage self-timed oscillatory rings are coupled.

Preferably, the at least one set of inputs is coupled to other n-stage self-timed oscillatory loops:

At least one set of inputs is connected to the outputs of different Muller C_elements.

Preferably, the multi-input Miller unit Muller C_element provides an initialization and configuration circuit;

The initialization and configuration circuit initializes and configures the n-stage self-timed oscillating loop, and configures the self-timed oscillating loop to generate different oscillating frequencies and oscillating waveforms.

Preferably, the n-stage self-timed oscillation loop generates n clock phases;

The m n-stage self-timed oscillating rings are coupled to generate m×n clock phases.

Preferably, it also includes:

Different clock phases are generated by adjusting the number of stages n of the self-timed oscillating loops and the number m of the self-timing oscillating loops.

Preferably, the series n of the self-timed oscillation ring is a positive integer greater than or equal to 3;

The number m of self-timed oscillation rings is a positive integer greater than or equal to 2.

Compared with the prior art, the present invention has the following beneficial effects:

The invention is based on all-digital design, has good mobility between processes, comprehensive performance of area, power consumption and anti-PVT characteristics, and has the advantages of high resolution and strong anti-noise

Description of drawings

Other features, objects and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments with reference to the following drawings:

FIG. 1 is a schematic structural diagram of a high-resolution multi-phase clock generation circuit provided by the present invention.

FIG. 2 is a schematic diagram of a self-timed oscillation ring provided by the present invention.

FIG. 3 is a schematic structural diagram of a multi-input Miller unit provided by the present invention.

FIG. 4 is a schematic diagram of an embodiment of the multi-input Miller unit provided by the present invention.

FIG. 5 is a schematic coupling diagram of the high-resolution multi-phase clock generation circuit provided by the present invention.

FIG. 6 is a schematic diagram of the simulation of the coupling of the high-resolution multi-phase clock generation circuit provided by the present invention.

Detailed ways

The present invention will be described in detail below with reference to specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be noted that, for those skilled in the art, several changes and improvements can be made without departing from the inventive concept. These all belong to the protection scope of the present invention.

A multi-phase clock generating circuit provided according to the present invention includes:

m n-stage self-timed oscillatory loops;

The m n-stage self-timed oscillating rings are coupled.

Specifically, the n-stage self-timed oscillation loop includes:

n multi-input Miller unit Muller C_element;

The multi-input Miller unit Muller C_element includes: multiple sets of inputs with the same function, at least one of which is used to generate an oscillating signal, and at least one of which is used to couple with other n-stage self-timed oscillating loops.

Specifically, the multi-input Miller unit Muller C_element:

The logical expression of Muller C_element of the multi-input Miller unit is as follows:

F is the input of n groups of the same function: F1=F2=....=Fn

R is the input of n groups of the same function: R1=R2=....=Rn

in,

SET represents the SET signal of the multi-input Miller unit Muller C_element;

RESET represents the RESET signal of the multi-input Miller unit Muller C_element;

C represents the output of the multi-input Muller element Muller C_element.

Specifically, the at least one set of inputs of the same function:

It is connected to the output of one or more other Miller C_elements except the multi-input Miller unit in the n-stage self-timed oscillation ring, so that the n multi-input denser elements in the n-stage self-timed oscillation ring are connected Le element MullerC_element connection.

Specifically, the at least one set of inputs of the same function:

It is connected with the output of one or more multi-input Miller units Muller C_element in other n-level self-timing oscillation rings except the n-level self-timing oscillation ring in the m n-level self-timing oscillation rings, so that m n-stage self-timed oscillatory rings are coupled.

Specifically, the at least one set of inputs is coupled to other n-stage self-timed oscillatory loops:

At least one set of inputs is connected to the outputs of different Muller C_elements.

Specifically, the multi-input Miller unit Muller C_element provides an initialization and configuration circuit;

The initialization and configuration circuit initializes and configures the n-stage self-timed oscillating loop, and configures the self-timed oscillating loop to generate different oscillating frequencies and oscillating waveforms.

Specifically, the n-stage self-timed oscillation loop generates n clock phases;

The m n-stage self-timed oscillating rings are coupled to generate m×n clock phases.

Specifically, it also includes:

Different clock phases are generated by adjusting the number of stages n of the self-timed oscillating loops and the number m of the self-timing oscillating loops.

Specifically, the series n of the self-timed oscillation ring is a positive integer greater than or equal to 3;

The number m of self-timed oscillation rings is a positive integer greater than or equal to 2.

Hereinafter, the present invention will be described in more detail through preferred examples.

Preferred Example 1:

Aiming at the problems of resolution, power consumption, circuit area and anti-PVT characteristics of the current high-resolution multi-phase clock generation circuit, the present invention generates a high-resolution clock by using an all-digital coupled self-timing oscillation loop. The design is based on all-digital design, with good mobility between processes, good comprehensive performance of area, power consumption and anti-PVT characteristics, and has the characteristics of high resolution and strong anti-noise.

The invention provides a design method of a high-resolution multi-phase clock generating circuit. The multi-phase clock generating circuit is generated by coupling of m n-level self-timed ring oscillators (STROs). where m represents the number of n-stage self-timed oscillatory loops, and n represents the number of stages of self-timed oscillatory loops. The number of self-timed oscillatory loops and the number of series of self-timed oscillatory loops can be adjusted to produce different phases. Different from other coupling modes using RLC, the multi-phase clock of the present invention is generated by coupling of different n-stage self-timed oscillating rings. The n-level self-timed oscillation ring can generate n clock phases, and the m independent self-timed oscillation rings are synchronized by coupling, and the coupling generates m×n clock phases, thereby realizing a high-resolution clock.

The n-stage self-timed oscillator loop generates a multiphase clock signal. The n-stage self-timed oscillating ring provided by the present invention can be adjusted to generate clock signals with different oscillating frequencies and different phases. The self-timed oscillating loop provided by the present invention can control the working state of the oscillating loop by setting the initial state of the oscillating loop. Preferably, the oscillating ring should be set to a uniform propagation mode to obtain a higher clock frequency and generate a uniform phase clock signal.

The n-stage self-timed oscillation ring is composed of n multi-input Muller C_elements.

The multi-input Miller unit Muller C_element is composed of multiple groups of inputs with the same function, at least one of which is used to generate an oscillating signal, and at least one of which is used for coupling with other self-timed oscillating loops.

The coupling between the self-timed oscillating rings is realized by the multi-input Miller unit Muller C_element. The multi-input Miller unit Muller C_element includes multiple input signals with the same function, and these different inputs of the same function are connected to the outputs of different Miller units Muller C_element, so as to realize the delay coupling and synchronization of the circuit.

For example, in m multi-input Miller units Muller C_element (F0...Fn, R0...Rn, SET, RESET), F0, R0 of each Miller unit Muller C_element are connected to each other to generate an m-level self-timed oscillation ring, but F1 and R1 are used to connect with F1 and R1 of another self-oscillating ring, resulting in a coupling effect. As shown in Figure 5, the Muller C_element corresponding to C1/C2/C3 forms a self-oscillating ring, and the Muller C_element corresponding to C4/C5/C6 forms a self-oscillating ring, and these units C4/C5/C6 form a self-oscillating ring. The F1/R1 is connected to C4/C5/C6 (inside the oscillation ring) respectively, while F2/R2 is coupled to the self-oscillating ring (another oscillation ring) composed of C1/C2/C3.

The traditional Miller unit includes signals such as F, R, RESET, SET, and C, and its truth table is shown in Table 1, where F, R, SET, and RESET are the inputs, and C is the output. The present invention proposes a concept of a multi-input Miller unit for the first time. Its characteristic is that the input includes F0...Fn, R0...Rn, SET, RESET and C signals. where F0...Fn implement the same logic function but have n different inputs. R0…Rn implement the same logic function but have n different inputs.

Muller C_element is a relatively common unit in asynchronous circuits. The most basic unit includes two inputs and one output, as shown in the following table

F R C 0 0 Previous C 0 1 0 1 0 1 1 1 Previous C

Its logical expression is: C=! (F^R)&C ^-1 +(F^R)&F

Or another way, as shown in the table below

F R C 0 0 0 0 1 Previous C 1 0 Previous C 1 1 1

Its logical expression is: C=(F^R)&C ^-1 +! (F^R)&F

Muller C_element will have Reset and Set ports in use. Taking the first method as an example, after adding Reset and Set signals, its truth table is as follows:

Its logical expression is:

The multi-input Muller C_element in the present invention is characterized in that it has multiple F and multiple R inputs, and its truth table is

Its logical expression is:

Which requires F0=F1=....=Fn, R0=R1=....=Rn

The multi-input Miller unit Muller C_element provides an initialization and configuration circuit for initializing and configuring the n-stage self-timed oscillating loop, and for configuring the self-timed oscillating loop to generate different oscillating frequencies and oscillating waveforms.

Preferred example 2:

FIG. 1 is a schematic structural diagram of a high-resolution multi-phase clock generation circuit of the present invention. The multi-phase clock generation circuit includes m n-stage self-timed oscillation loop circuits. M number of n-stage self-timed oscillation loop circuits are mutually coupled to form a high-resolution multi-phase clock generating circuit. The numbers of m and n are adjusted according to the number of required clock phases, and the frequency of the clock.

FIG. 2 is a self-timed oscillation loop in the present invention, which is composed of an n-stage multi-input Miller unit Muller C_element, where n is a positive integer greater than or equal to 3. As shown in FIG. In the self-timed oscillation ring composed of multi-input Miller unit Muller C_element, according to the principle of self-timed circuit, there are two states of bubble and token. Among them, token is defined as the state in which the output C _i in the oscillating ring i stage is not equal to the output C _i-1 of the previous stage. Bubble is defined as the state where the output C _i in the oscillating ring i stage is equal to the output C _i-1 of the previous stage. Self-timed oscillatory loops can generate autonomous oscillations when three conditions are met. The three conditions are: (1) the number of oscillation ring series n is greater than or equal to 3; (2) the number of bubbles in the oscillation ring should be greater than or equal to 1; (3) the number of tokens in the oscillation ring is a positive even number.

Multi-input Miller unit Muller C_element As shown in FIG. 3 , the Miller unit Muller C_element in the present invention has multiple sets of inputs with the same function. Among them, F11 to F1n are the input of n groups of the same function. R11 to R1n are also n sets of inputs for the same function. One of the main features of the multi-input Miller unit Muller C_element different from the Miller unit Muller C_element of the present invention is the use of the multi-input Miller unit Muller C_element.

As shown in Figure 3, the multi-input Miller unit Muller C_element includes set and reset signals, which can be used to adjust the initial state of the oscillating ring and set the oscillation mode of the oscillating ring. The oscillating ring has two propagation modes: uniformly spaced propagation mode and burst propagation mode. If the difference between the number of bubbles and the number of tokens in the initial state of the oscillating ring is smaller, the greater the Charlie effect in the Muller C_element of the Miller unit, the higher the output clock frequency, and the oscillating ring is in a uniformly spaced propagation mode. If the difference between the number of bubbles and the number of tokens in the initial state of the oscillation ring is larger, the Charlie effect in the Muller C_element will be smaller, and the frequency of the output clock will be lower. At this time, the oscillation ring is in the burst propagation mode. Evenly spaced propagation modes have higher frequencies for the same series. In the above manner, in the initial configuration, the oscillation mode and frequency adjustment of the input clock in the self-timed oscillation loop can be realized.

FIG. 4 is a specific embodiment of the multi-input Miller unit Muller C_element of the present invention, which includes two sets of identical inputs F1 and F2, R1 and R2. The truth table of the Miller unit Muller C_element is shown in Table 1

Table 1. Multi-input Miller unit truth table

The Muller C_element has many circuit structures, and this specific implementation is just one example, and the present invention is not limited to the implementation method in FIG. 4 .

Figure 5 is an embodiment of the present invention. Three 3-stage self-timed oscillatory loops are included in the embodiment. Through the coupling method provided by the present invention, 3×3 clock phases are generated by coupling, thereby realizing a multi-phase clock. The design is based on an all-digital design, and has the characteristics of good mobility between processes, good comprehensive performance of area, power consumption and PVT resistance, and high resolution. FIG. 6 is a simulation diagram of the high-resolution multi-phase clock generating circuit of the present invention. For the circuit structure of FIG. 5 , clocks of 9 phases can be generated.

Those skilled in the art know that, in addition to implementing the system, device and each module provided by the present invention in the form of pure computer readable program code, the system, device and each module provided by the present invention can be completely implemented by logically programming the method steps. The same program is implemented in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, and embedded microcontrollers, among others. Therefore, the system, device and each module provided by the present invention can be regarded as a kind of hardware component, and the modules used for realizing various programs included in it can also be regarded as the structure in the hardware component; A module for realizing various functions can be regarded as either a software program for realizing a method or a structure within a hardware component.

Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the above-mentioned specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essential content of the present invention. The embodiments of the present application and features in the embodiments may be combined with each other arbitrarily, provided that there is no conflict.

Claims (8)

1. a multi-phase clock generating circuit, is characterized in that, comprises: m n-stage self-timed oscillatory loops; the m n-level self-timed oscillation rings are coupled; The n-stage self-timed oscillating loop includes: n multi-input Miller unit Muller C_element; The multi-input Miller unit Muller C_element includes: multiple sets of inputs with the same function, at least one of which is used to generate an oscillating signal, and at least one of which is used to couple with other n-stage self-timed oscillating loops; The multi-input Miller unit Muller C_element: The logical expression of Muller C_element of the multi-input Miller unit is as follows:

F is the input of n groups of the same function: F1=F2=....=Fn R is the input of n groups of the same function: R1=R2=....=Rn in, ^ means XOR logic; SET represents the SET signal of the multi-input Miller unit Muller C_element; RESET represents the RESET signal of the multi-input Miller unit Muller C_element; C represents the output of the multi-input Miller unit Muller C_element; C ^-1 represents the previous output value of the Miller unit. 2. The multi-phase clock generating circuit according to claim 1, wherein the at least one group of inputs with the same function: It is connected to the output of one or more other Miller C_elements except the multi-input Miller unit in the n-stage self-timed oscillation ring, so that the n multi-input denser elements in the n-stage self-timed oscillation ring are connected ler unit Muller C_element connection. 3. The multi-phase clock generating circuit according to claim 2, wherein the at least one group of inputs with the same function: It is connected with the output of one or more multi-input Miller units Muller C_element in other n-level self-timing oscillation rings except the n-level self-timing oscillation ring in the m n-level self-timing oscillation rings, so that m n-stage self-timed oscillatory rings are coupled. 4. The multi-phase clock generation circuit according to claim 3, wherein the at least one group of inputs is coupled with other n-stage self-timed oscillation loops: At least one set of inputs is connected to the outputs of different Muller C_elements. 5. multiphase clock generation circuit according to claim 4, is characterized in that, the Miller unit Muller C_element of described multi-input provides an initialization and configuration circuit; The initialization and configuration circuit initializes and configures the n-stage self-timed oscillating loop, and configures the self-timed oscillating loop to generate different oscillating frequencies and oscillating waveforms. 6. The multi-phase clock generating circuit according to claim 5, wherein the n-stage self-timed oscillation loop generates n clock phases; The m n-stage self-timed oscillating rings are coupled to generate m×n clock phases. 7. The multi-phase clock generating circuit according to claim 6, further comprising: Different clock phases are generated by adjusting the number of stages n of the self-timed oscillating loops and the number m of the self-timing oscillating loops. 8. The multi-phase clock generating circuit according to claim 7, wherein the number of stages n of the self-timed oscillation loop is a positive integer greater than or equal to 3; The number m of self-timed oscillation rings is a positive integer greater than or equal to 2.

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