KR20010061484A - Delay Locked Loop using Digital Ring Synchronous Mirror Delay - Google Patents

Abstract

PURPOSE: A delay lock loop using a digital synchronous mirror delay is provided to reduce the number of unit delays considerably by changing a linear delay line to a ring structure. CONSTITUTION: In a DLL circuit, an input part(100) receives a CLK signal and a CLKB signal to generate a rising clock by comparing the signals. A delay monitor(100) inputs the rising clock to time-delay the rising clock by a skew to be compensated for the CLK. A forward delay part(200) inputs the output from the rising clock and the delay monitor to control the time delay, while ring-circulating to the first direction. The first counter(210) inputs the signal output from the forward delay part to count the circulating frequency. A mirror control part and a backward delay part(240) input a selection signal, while ring-circulating to the second direction, to control a time delay. The counter inputs the signal output from the backward delay part to count a circulating frequency. A count comparator(230) compares the counting frequency of the first counter with that of the second counter. An output part(250)t inputs the outputs from the count comparator and the backward delay part to output a DLL clock signal.

Description

Delay Locked Loop using Digital Ring Synchronous Mirror Delay

The present invention relates to a semiconductor memory device, and more particularly, to a delay locked loop.

In general, a delay locked loop is a circuit used to make an internal clock of a synchronous memory using a clock coincide with an external clock without error. That is, a timing delay occurs when an external clock is used internally. This timing delay is used to control the internal clock to be synchronized with an external clock. In other words, it is a clock generator for compensating skew between an external clock and data, or an external clock and an internal clock.

1 is a block diagram of a linear delay locked loop of the prior art.

Referring to FIG. 1, the delay lock loop according to the related art receives the clock signal CLK and the anticlock signal CLKB and compares the input signal to generate an rising clock rclk. A delay monitor 110 for receiving the rising clock rclk as a clock signal and delaying the rising clock rclk by a skew to compensate for the clock signal CLK, and the delay monitor 110. Forward delay array 120 for adjusting the time delay in the first direction by receiving the output from the output, and the output delay of the forward delay delay 120 and the rising clock (rclk) by the time delay adjusted delay A mirror controller 130 for inputting a rising clock, a backward delay array 140 for adjusting a time delay in a second direction by receiving an output of the mirror controller 140, and the backward delay array ( From 140) And an output unit 150 for receiving the output and outputting a delay locked loop clock signal.

The delay lock loop corresponds to a case in which the delay d1 of the input part and the delay d2 of the output part are compensated for, and an internal clock that matches the external clock is obtained. Therefore, the delay monitor 110 is a circuit causing a delay by (d1 + d2). First, the time tCK (one clock cycle)-(d1 + d2) is digitized through the forward delay line 120 to determine how many unit delays this time corresponds to. This process converts time into digital delays and is called time to digital conversion.

For example, if up to the black part of FIG. 1 corresponds to tCK-(d1 + d2), the mirror controller 130 allows the rising clock rclk to enter only the corresponding unit delay of the backward delay array 140. . Therefore, the rising clock rclk enters from the black-marked portion of the backward delay array 140 and propagates to the output unit 150. Thus, a delay of tCK − (d 1 + d 2) occurs in this process and the output unit ( And delayed by d2 at 150), and the external clock is delayed by the delay d1 of the input unit 100 because the rising clock rclk itself is delayed loop clock iRclk compared to the clock signal CLK. Since (d1 + d2) = tCK, which is one cycle delayed, we get an internal clock that is synchronized to the external clock. Of course, digital errors follow.

As can be seen from above, since unit delay lines corresponding to tCK-(d1 + d2) should be prepared, a larger number of unit delays are required as the tCK increases.

Therefore, the delay locked loop of the prior art has a problem in that a larger number of unit delays are required as the frequency goes lower, that is, the longer the clock period tCK is, so that the required area becomes very large.

The present invention has been made to solve the above problems of the prior art, an object of the present invention is to provide a delay locked loop that can significantly reduce the number of unit delays by changing the linear delay line into a ring structure.

1 is a block diagram of a linear delay locked loop of the prior art;

2 is a block diagram of a delayed fixed loop of the present invention;

Figure 3 is a schematic diagram re-drawing easy to see the delayed fixed loop of the present invention,

Figure 4 is an embodiment of a delay lock loop of the present invention.

Explanation of symbols on the main parts of the drawings

110: delay monitor 200: forward delay unit

210: first counter 220: second counter

230: count comparator 240: mirror control unit and backward delay unit

In order to achieve the above object, a delay lock loop according to an embodiment of the present invention includes an input unit for receiving a clock signal (CLK) and a half clock signal (CLKB) and comparing the input signal to generate a rising clock (rclk); A delay monitor for receiving the rising clock as a clock signal and delaying the rising clock by a skew to compensate for the clock signal CLK; A forward delay unit configured to adjust a time delay while receiving a rising clock and an output from the delay monitor and performing a ring cycle in a first direction; A first counter for counting the number of rotations of the signal output from the forward delay unit; A mirror controller and a backward delay unit configured to adjust a time delay while receiving a selection signal for inputting a rising clock with a unit delay corresponding to the rising clock and a time delay, and performing a ring circulation in a second direction; A second counter for counting the number of rotations of the signal output from the backward delay unit; A count comparator for comparing the number of counting of the first counter and the second counter; And an output unit configured to receive the output of the count comparator and the backward delay unit and output a delay locked loop clock signal iRclk.

As described above, the present invention includes a forward delay unit composed of delays circulated in a ring, a mirror control unit, and a backward delay unit to reduce a large number of unit delays in the prior art, thereby reducing the layout cost of the chip, thereby reducing low cost. It is possible to achieve a delay locked loop with low power consumption.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2 is a block diagram of a delayed fixed loop of the present invention.

Referring to FIG. 2, an input unit 100 for receiving a clock signal CLK and a half clock signal CLKB and comparing the input signal to generate a rising clock Rclk, and clocks the rising clock Rclk. A delay monitor 110 for delaying the rising clock Rclk by a skew to compensate for the clock signal CLK, the rising clock Rclk, and the delay monitor 110 as a signal; Counting the number of times to rotate the receiving the output from the forward delay unit 200 and the forward delay unit 200 for adjusting the time delay while receiving the output from the ring (Ring) in the first direction To adjust the time delay while receiving the first counter 210 and a selection signal for inputting the rising clock with the unit clock corresponding to the time delay and the rising clock (Rclk) to the ring in the second direction Mirror control unit A second counter 220 for counting the number of times the number of times the number of the rotation of the backward delay unit 240, the signal output from the backward delay unit 240, the first counter 210 and the second A count comparator 230 for comparing the number of counts of the counter 220 and an output of the count comparator 230 and the backward delay unit 240 to output the delay locked loop clock signal iRclk. It is provided with the output part 250.

The concept of time to digital conversion is described in 1998 Symposium on VLSI Circuits Digest of Technical Papers, pp 60-61, "A Compact Ring Delay Line fot High Speed SDRAM", Seong-Jin et. Al (KAIST). The concept of digital to time conversion using the ring structure of the delay locked loop is proposed in the present invention. In the case of the literature, the backward delay line uses a linear structure as it is, but in this case, the unit delay reduction effect is only half. However, as in the present invention, the backward delay line is also configured as a ring to further obtain a unit delay reduction effect. have.

Figure 3 is a schematic diagram re-drawing easy to see the delay lock loop of the present invention.

Since the configuration is the same as that described in FIG. 2, it is omitted.

In the present invention, the signal is circulated along the ring, except that a counter for counting how many turns is added to have a configuration similar to that of a linear delay locked loop. For example, suppose a ring consists of six unit delays. If the time tCK-(d1 + d2) is converted into 34 unit delays, this corresponds to 5 wheels (the first counter counts 5) + 4 unit delays, which is the black part of FIG. Accordingly, in the ring backward delay unit 240, four unit delays are first passed from the black portion to the left, and the remaining five wheels are filled, and the output comparator signal floats in the count comparator 230 and exits to the output terminal 250. The ring backward delay unit 240 and the second counter 220 are reset again and repeat the above process. The difference from a linear delay locked loop is that the signal circulating through the ring must be pulsed.

4 is an embodiment of a delay locked loop of the present invention.

Referring to FIG. 4, the delay monitor 110 receives a rising clock rclk as a clock signal and delays the rising clock rclk by a skew to compensate for the clock signal CLK. And a forward delay unit 200 for adjusting the time delay while receiving the output from the rising clock rclk and the delay monitor 110 in a ring cycle in a first direction, and the rising clock rclk. And a mirror control unit and a backward delay unit 240 for adjusting a time delay while receiving a selection signal for inputting a rising clock with a unit delay corresponding to a time delay and performing a ring cycle in a second direction. And an output unit 250 for receiving the output of the delay unit 240 and outputting the delay locked loop clock signal iRclk.

In this case, the unit delay is configured by the NAND gate, and a signal for resetting each ring is required. The counter and the like are omitted. In this case, a low pulse circulates along the ring. The unit delay may be configured by a noah gate or another combination, and accordingly, a control signal may be appropriately configured.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention configures a synchronous mirror delay (SMD) having a conventional linear structure in a ring shape to significantly reduce the total number of unit delays required, thereby reducing the total area to 1/5 or less. You can achieve the same performance with less.

Claims (3)

In a semiconductor memory device, An input unit configured to receive a clock signal CLK and a half clock signal CLKB and compare the input signal to generate a rising clock rclk; A delay monitor for receiving the rising clock as a clock signal and delaying the rising clock by a skew to compensate for the clock signal CLK; A forward delay unit configured to adjust a time delay while receiving a rising clock and an output from the delay monitor and performing a ring cycle in a first direction; A first counter for counting the number of rotations of the signal output from the forward delay unit; A mirror controller and a backward delay unit configured to adjust a time delay while receiving a selection signal for inputting a rising clock with a unit delay corresponding to the rising clock and a time delay, and performing a ring circulation in a second direction; A second counter for counting the number of rotations of the signal output from the backward delay unit; A count comparator for comparing the number of counting of the first counter and the second counter; An output unit for receiving the output of the count comparator and the backward delay unit and outputting a delay locked loop clock signal iRclk Delay fixed loop made, including. The method of claim 1, The mirror control unit and the backward delay unit, A NAND gate which receives a selection signal for inputting the rising clock with the rising clock and a unit delay and performs a negative logic multiplication; And Unit delay to receive the output of the NAND gate while performing a ring cycle Delay fixed loop made, including. The method of claim 1, The mirror control unit and the backward delay unit, A noah gate that receives a selection signal for inputting the rising clock with the rising clock and a unit delay and performs a negative logic sum; And Unit delay to receive the output of the noble gate while ring cycling Delay fixed loop made, including.