CN110492872B - Digital duty cycle correction circuitry - Google Patents

Digital duty cycle correction circuitry Download PDF

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Publication number
CN110492872B
CN110492872B CN201910861413.1A CN201910861413A CN110492872B CN 110492872 B CN110492872 B CN 110492872B CN 201910861413 A CN201910861413 A CN 201910861413A CN 110492872 B CN110492872 B CN 110492872B
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circuit
port
gate
input
delay unit
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CN110492872A (en
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李路
陈波
方敏
周春元
罗俊
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Zhuhai Weidu Xinchuang Technology Co ltd
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Zhuhai Weidu Xinchuang Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

The invention discloses a digital duty cycle correction circuit system, which comprises: a narrow pulse generating circuit, a half clock period delay circuit, and a trigger reset latch; the narrow pulse generating circuit receives an input clock signal, and an output port of the narrow pulse generating circuit is respectively connected to an input port of the half clock period delay circuit and an S port of the trigger reset latch; an output port of the half-clock period delay circuit is connected to an R port of the trigger reset latch; and the output port of the trigger reset latch obtains an output clock signal. According to the technical scheme, the data latch, the gating device and the OR gate circuit in the half-clock period delay chain are added, so that the risk of circuit output burrs is eliminated at the cost of small area and power consumption, and the robustness of a circuit system is improved.

Description

Digital duty cycle correction circuitry
Technical Field
The invention relates to the technical field of circuits, in particular to a digital duty ratio correction circuit system.
Background
In the prior art, a 50% duty cycle correction circuit (Duty Cycle Correction, DCC for short) is widely used in switched capacitor circuits, phase-Locked Loops (PLL for short), synchronous dynamic random Access memories (Synchronous Dynamic Random-Access memories, SDRAM for short), and dynamic random Access memories (Dynamic Random Access Memory, DRAM for short) systems. For example, in a phase locked loop supporting multiple reference frequencies, a 50% duty cycle correction process is required before the input reference clock is doubled to eliminate jitter on the clock edges after the doubling; in Dynamic Random Access Memory (DRAM) and Synchronous Dynamic Random Access Memory (SDRAM), delay-Locked Loop (DLL) based on 50% duty cycle correction is often used to increase the output data rate.
Common duty cycle correction circuits have both analog and digital implementations. The analog implementation mode comprises a passive device, is large in area and cannot be compatible with a pure digital process; the digital circuit has small area and higher reliability, so that the digital circuit is widely applied, and the specific circuit structure is shown in figure 1. The digital duty ratio correction circuit firstly converts an input clock signal FIN (with a period of T) with any duty ratio (x%) into a narrow Pulse clock signal a by using a narrow Pulse Generator (PG) and then accurately delays the narrow Pulse clock by 1.5 input clock signal periods T through a half clock period delay circuit (Half Cycle Delay Line, HCDL) to obtain b; the delayed narrow pulse clock signal a and the delayed narrow pulse clock signal b are subjected to triggering of a reset LATCH (SR-LATCH) to obtain an output signal with the same frequency as the input clock signal FIN, namely an output clock signal FOUT with a 50% duty cycle, and the timing diagram of the process is shown in figure 2.
As shown in fig. 1, the core component in the 50% duty cycle correction circuit is a half clock cycle delay circuit (HCDL). The circuit structure of the half clock cycle delay circuit (HCDL) is shown in figure 3, and comprises a forward delay chain 31 (Forward Delay Line), an AND gate&) And an OR gate (OR) array, and a reverse delay chain 32 (Backward Delay Line). The forward delay chain 31 and the reverse delay chain 32 are formed by cascading delay units (delta), and the delay units (delta) are shown in fig. 4 and comprise an or gate circuit (42) and a two-stage buffer (41). In the forward delay chain and the reverse delay chain, 1 input terminal of the delay unit (delta) of the first stage needs to be commonly grounded to VSS to ensure that the delay unit (delta) is turned on. In fig. 3, every 2 delay units in the forward delay chain pass through 2 AND gates&) The circuit and 1 OR gate (OR) circuit are correspondingly connected to delay cells in1 reverse delay chain, i.e. the total number of delay cells of reverse delay chain 32 is half of that of forward delay chain 31, wherein the delay cells in the forward delay chain are also referred to as forward delay cells and the delay cells in the reverse delay chain are also referred to as reverse delay cells. As shown in fig. 3, taking 10 forward delay units of the forward delay chain and 5 reverse delay units of the reverse delay chain as examples, fig. 5 is a corresponding half clock period delay circuit (HCDL) operation timing chart, the input signal a is a narrow pulse clock output by the narrow pulse generating circuit (PG), and the configuration is thatThe constant pulse width is the same as the unit delay delta, the input signal a is sequentially delayed by the forward delay units in the forward delay chain, and the output signal a of the forward delay units 1 ～a 10 And the sum of the sum and the input signal a&) Operation, when the delay amount reaches 1 signal period (1T), i.e. the output signal a in FIG. 5 10 The AND gate corresponding to the forward delay unit&) Generates a pulse signal, which enters a reverse delay chain (signal b1 in figures 3 and 5) after passing through a corresponding OR gate circuit, due to other AND gates&) And its corresponding OR gate (OR) both output 0, the reverse delay chain 32 remains on, and the pulse signal b1 passes through the reverse delay chain to output the final output signal b. After passing through an OR gate (OR) circuit, the pulse signal enters the reverse delay chain. Since 1 reverse delay unit is corresponding to every 2 forward delay units, the total delay amount of the reverse is 0.5T, and the AND gate is ignored&) The total delay between the output signal b and the input signal a of the reverse delay chain is 1.5 signal cycles (1.5T) due to the effects of the delays of the circuits and the OR gate (OR) circuits themselves.
However, the inventors have found that, in the prior art, although a half-clock period delay circuit (HCDL) can achieve a delay of 1.5 signal periods, in practice, since the delay amount Δ of the delay unit is an analog amount, the output signal a of the delay unit is forwarded under the influence of fluctuation factors such as process, temperature, and power supply voltage 1 ～a 10 The phase relationship with the second pulse of the input signal a is not as accurate and stable as shown in fig. 5, but the following three cases are possible:
in the first case, the second pulse of the input signal a is coupled to the output signal a of a certain forward delay unit n (e.g. a 10 ) Just overlapping, the circuit works normally without error, as shown in fig. 5;
in the second case, the second pulse of the input signal a is combined with the output signal a of a two-stage forward delay unit i And a i+1 All have partial coincidence, and i is an odd number, a i And a i+1 The corresponding AND gates generate pulse signals, and the two pulse signals enter the same OR gate(OR) is combined into a pulse signal b of the same width as the input signal a k And enters a reverse delay chain, the circuit works normally, but has a certain quantization error, the maximum error value is delta/2, and the time sequence diagram of the situation is shown in figure 6;
in the third case, the second pulse of the input signal a is combined with the output signal a of a two-stage forward delay unit j And a j+1 All have partial coincidence, and j is an even number, then a j And a j+1 The corresponding AND gates generate pulse signals, but the two pulse signals enter different OR gate circuits and are not combined, and a j Pulse ratio a generated j+1 The generated pulse passes through the one-stage reverse delay unit less, so that burrs occur in the reverse delay chain, and the circuit is abnormal in operation, and the timing chart of the situation is shown in fig. 7.
The above-mentioned problems can be solved by reducing the pulse width of the input signal a, as shown in FIG. 8, when the pulse width is less than or equal to Δ/2, no two AND gates will generate the output signals at the same time, so no glitch will occur, but in this case the second pulse of the input signal a may occur exactly at a n And a n+1 And all AND gates have no output, so that the circuits fail and work abnormally.
Disclosure of Invention
Based on the above, in order to solve the technical problems in the prior art, a digital duty ratio correction circuit system is specifically provided.
The digital duty cycle correction circuit system comprises a narrow pulse generation circuit, a half clock period delay circuit and a trigger reset latch;
an input port of the narrow pulse generating circuit receives an input clock signal, and an output port of the narrow pulse generating circuit is respectively connected to the input port of the half clock period delay circuit and the S port of the trigger reset latch; an output port of the half-clock period delay circuit is connected to an R port of the trigger reset latch; the output port of the trigger reset latch obtains an output clock signal;
the half-clock period delay circuit comprises a forward delay chain, a reverse delay chain and a logic gate array; the forward delay chain is connected to the array of logic gates, which is connected to the reverse delay chain;
the forward delay chain comprises n cascaded forward delay units, wherein n is an even number greater than or equal to 2; the reverse delay chain comprises n/2 reverse delay units in cascade; the logic gate array comprises n/2 logic gate circuit modules in parallel, and each logic gate circuit module is correspondingly connected to 2 forward delay units and 1 reverse delay unit.
In one embodiment, each stage of forward delay unit has 2 input ports and 1 output port, the 2 input ports are a first input port of the forward delay unit and a second input port of the forward delay unit, the first input port of each stage of forward delay unit is connected to a power supply, the second input port of the 1 st stage of forward delay unit is connected to the output port of the narrow pulse generating circuit, and the output port of the previous stage of forward delay unit is connected to the second input port of the next stage of forward delay unit; the output port of the i-th stage forward delay unit gets a forward output signal ai, where i=1, 2.
In one embodiment, each stage of reverse delay unit has 2 input ports and 1 output port, the 2 input ports are a first input port of the reverse delay unit and a second input port of the reverse delay unit, the first input port of each stage of reverse delay unit is connected to a power supply, the output port of the previous stage of reverse delay unit is connected to the second input port of the next stage of reverse delay unit, and the output port of the last stage of reverse delay unit is connected to the R port of the trigger reset latch.
In one embodiment, the logic gate module includes a first and gate, a second and gate, a first or gate; the first AND gate circuit and the second AND gate circuit are provided with 2 input ports and 1 output port; the first input port of the first AND gate circuit and the first input port of the second AND gate circuit are connected to the output port of the narrow pulse generating circuit; a second input port of the first and circuit in the kth logic gate circuit module is connected to an output port of the n+1-2k stage forward delay unit, and a second input port of the second and circuit is connected to an output port of the n+2-2k stage forward delay unit, wherein k=1, 2. The first OR gate circuit is provided with 2 input ports and 1 output port; the first input port of the first OR gate circuit is connected with the output port of the first AND gate circuit, and the second input port of the first OR gate circuit is connected with the output port of the second AND gate circuit.
In one embodiment, the logic gate module further comprises a second or gate, a data latch, a two-input gate; the second OR gate circuit is provided with 2 input ports and 1 output port; the output port of the first OR gate is connected to the first input port of the two-input gate;
the clock port of the data latch is connected to the output end of the second AND gate circuit, and the data port of the data latch is connected to a power supply; the inverting output port of the data latch is connected to the selection signal input port of the two-input gate; a second input port of the two-input gate is connected to a power supply, and an output port of the two-input gate is connected to a first input port of the second OR gate;
the second input port of the second OR gate of the 1 st logic gate module is grounded; the second input port of the second OR gate of the kth logic gate module is connected to the output port of the first OR gate of the kth-1 logic gate module, wherein k > 1; the output port of the second or gate of the kth logic gate module is connected to the second input port of the kth stage inverse delay unit, i.e. the second input port of the kth stage inverse delay unit receives the output signal bk of the kth logic gate module, wherein k=1, 2.
In one embodiment, the forward delay unit and the reverse delay unit are delay units composed of 1 AND gate circuit and two stages of buffers.
The implementation of the embodiment of the invention has the following beneficial effects:
the invention eliminates the risk of abnormal circuit operation caused by circuit output burrs with small area and power consumption cost by adding the data latch, the gating device and the OR gate circuit in the half clock period delay chain, and increases the robustness of a circuit system.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Wherein:
FIG. 1 is a schematic diagram of a digital duty cycle correction circuit in the prior art;
FIG. 2 is a timing diagram illustrating the operation of a digital duty cycle correction circuit according to the prior art;
FIG. 3 is a schematic diagram of a half-clock cycle delay circuit in the prior art;
FIG. 4 is a schematic diagram of a prior art delay cell structure;
FIG. 5 is a timing diagram illustrating the operation of a half-clock cycle delay circuit according to the prior art in a first pulse phase relationship;
FIG. 6 is a timing diagram illustrating operation of a half-clock cycle delay circuit according to the second pulse phase relationship of the prior art;
FIG. 7 is a timing diagram illustrating the operation of a third pulse phase relationship of a half-clock cycle delay circuit according to the prior art;
FIG. 8 is a timing diagram illustrating the operation of a half-clock cycle delay circuit in accordance with the prior art when the pulse width of the input signal is reduced;
fig. 9 is a schematic diagram of a half-clock cycle delay circuit in the digital duty cycle correction circuitry according to the present invention.
Fig. 10 is a schematic diagram of a delay unit structure in the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention discloses a digital duty cycle correction circuit system, which comprises a narrow pulse generation circuit (PG), a half clock period delay circuit (HCDL) and a trigger reset LATCH (SR-LATCH);
an input port of the narrow pulse generating circuit receives an input clock signal, and an output port of the narrow pulse generating circuit is respectively connected to the input port of the half clock period delay circuit and the S port of the trigger reset latch; an output port of the half-clock period delay circuit is connected to an R port of the trigger reset latch; the output port of the trigger reset latch obtains an output clock signal;
as shown in fig. 9, the half-clock cycle delay circuit includes a forward delay chain 91, a reverse delay chain 92, and a logic gate array 93;
the forward delay chain 91 includes n cascaded forward delay units, each stage of forward delay unit has 2 input ports and 1 output port, the 2 input ports are a first input port of the forward delay unit and a second input port of the forward delay unit, the first input ports of the forward delay units are all connected to the power supply VDD, the second input port of the 1 st stage of forward delay unit is connected to the output port of the narrow pulse generating circuit, and the output port of the previous stage of forward delay unit is connected to the second input port of the next stage of forward delay unit; the output port of the i-th stage forward delay unit obtains a forward output signal ai, wherein i=1, 2,..n, n is an even number;
as shown in fig. 9, the forward delay units of each stage in the forward delay chain 91 are sequentially arranged from left to right, the leftmost stage is a 1 st stage forward delay unit, and the rightmost stage is an nth stage forward delay unit;
the reverse delay chain 92 includes n/2 reverse delay units in cascade, each stage of reverse delay unit has 2 input ports and 1 output port, the 2 input ports are a first input port of the reverse delay unit and a second input port of the reverse delay unit, the first input ports of the reverse delay units are all connected to the power supply VDD, the output port of the last stage (n/2 stage) reverse delay unit is connected to the R port of the trigger reset latch, and the output port of the previous stage reverse delay unit is connected to the second input port of the next stage reverse delay unit;
as shown in fig. 9, the backward delay units of each stage in the backward delay chain 92 are sequentially arranged from right to left, the rightmost is the 1 st stage backward delay unit, and the leftmost is the n/2 nd stage forward delay unit;
in particular, as shown in fig. 10, the forward delay unit and the reverse delay unit are both delay units, and the delay units include 1 and gate (&) circuit and two-stage buffer 101; in the forward delay chain 91, one input of the AND gate (&) circuit in the forward delay cell is commonly connected to the power supply (VDD) to ensure the turn-on of the delay cell. Compared with a delay unit formed by 1 OR gate (OR) circuit and two stages of buffers, the delay unit has the advantages of unchanged occupied area, power consumption and delay amount.
The logic gate array 93 includes n/2 logic gate modules in parallel, each logic gate module is correspondingly connected to 2 forward delay units and 1 reverse delay unit; the logic gate circuit module comprises a first AND gate circuit (& 1), a second AND gate circuit (& 2), a first OR gate circuit (OR 1), a second OR gate circuit (OR 2), a data LATCH (LATCH) and a two-input strobe (MUX); the first AND gate circuit (& 1) and the second AND gate circuit (& 2) are provided with 2 input ports and 1 output port; the first input port of the first AND gate circuit (& 1) and the first input port of the second AND gate circuit (& 2) are connected to the output port of the narrow pulse generating circuit; a second input port of the first and circuit (& 1) in the kth logic gate circuit module is connected to an output port of the n+1-2k stage forward delay unit, and a second input port of the second and circuit (& 2) is connected to an output port of the n+2-2k stage forward delay unit, wherein k=1, 2.
As shown in fig. 9, each logic gate module in the logic gate array 93 is sequentially arranged from right to left, the 1 st logic gate module is on the rightmost side, and the n/2 nd logic gate module is on the leftmost side;
the first OR-gate circuit (OR 1) and the second OR-gate circuit (OR 2) each have 2 input ports and 1 output port; a first input port of the first OR circuit (OR 1) is connected with an output port of the first AND circuit (& 1), and a second input port of the first OR circuit (OR 1) is connected with an output port of the second AND circuit (& 2); the output port of the first OR gate (OR 1) is connected to the first input port IN0 of the two-input gate (MUX);
the clock port CK of the data LATCH (LATCH) is connected to the output of the second and gate (& 2), and the data port (D) of the data LATCH is connected to the power supply VDD; -the inverting output port (QN) of the data latch is connected to the selection signal input port (S) of the two-input strobe;
a second input port IN1 of the two-input gate (MUX) is connected to the power supply VDD, and an output port of the two-input gate is connected to a first input port of the second or gate;
the second input port of the second OR gate of the 1 st logic gate module is grounded to VSS; the second input port of the second OR gate of the kth logic gate module is connected to the output port of the first OR gate of the previous (i.e., kth-1) logic gate module, where k > 1; the output port of the second OR gate of the kth logic gate module is connected to the second input port of the kth stage inverse delay unit, i.e. the second input port of the kth stage inverse delay unit receives the output signal b of the kth logic gate module k Where k=1, 2,..n/2, n is an even number.
Inputting an input clock signal FIN with arbitrary duty ratio (x%) into the digital duty ratio correction circuit system, wherein the period of the input clock signal FIN is T; converting an input clock signal FIN with an arbitrary duty ratio (x%) into a narrow pulse clock signal a by using the narrow pulse generating circuit and inputting the narrow pulse clock signal a into a half clock period delay circuit; the half clock period delay circuit delays the narrow pulse clock signal a by 1.5 input clock signal periods T to obtain a delayed narrow pulse clock signal b; the delayed narrow pulse clock signal a and the delayed narrow pulse clock signal b trigger the reset latch to obtain an output clock signal FOUT with the same frequency as the input clock signal FIN and 50% duty ratio.
Wherein the data LATCH (LATCH) is a high level that turns on the input of the data port (D), a low level that keeps the current output; the initial state after reset is positive output port q=0, negative output port qn=1, and data port (D) thereof is connected to power supply VDD. When the accumulated delay amount of the forward delay unit is smaller than the input clock signal period T, the corresponding AND gate circuit outputs 0, the data latch is IN the initial state after reset, the output value of the reverse phase output port QN is 1, the second input port (IN 1) IN the two input gates is selected, the outputs of the two input gates and the second OR gate of the rear stage are all 1, and the corresponding reverse delay unit is normally opened. When the cumulative delay amount of the forward delay unit is equal to T, there are still three possibilities of the relative positional relationship between the forward output signal ai obtained at the output port of the i-th stage forward delay unit and the second pulse of the narrow pulse clock signal a:
in the first case, the second pulse of the narrow pulse clock signal a is exactly coincident with a certain forward output signal ai, and the circuit works normally;
in the second case, the second pulse of the narrow pulse clock signal a and the forward output signal a i And a i+1 All have partial coincidence, wherein i is an odd number, then a i And a i+1 The corresponding AND gates generate pulses which enter the first OR gate (OR 1) of the same logic gate module to be combined into a pulse signal with the same width as the narrow pulse clock signal a, and a i+1 The pulse signal generated by AND operation of the sum a triggers a data latch, and the data latch adoptsThe level VDD of the data port (D) is then output qn=0, the two-input gate turns on the first input port (IN 0), and the other input of the second OR circuit (OR 2) is 0, so that the pulse signal output by the first OR circuit (OR 1) enters the reverse delay chain after passing through the two-input gate and the second OR circuit (OR 2), and the circuit works normally;
in the third case, the second pulse of the narrow pulse clock signal a and the forward output signal a j And a j+1 All have partial coincidence, where j is an even number, then a j And a j+1 The corresponding AND gates generate pulses, but the two pulses enter the first OR gate of different logic gate modules, and the two pulses are not combined, a j And the narrow pulse clock signal a is ANDed, the pulse signal generated by the ANDed operation is taken to VDD, so that QN=0 of the data latch, and the pulse can reach the second OR gate (OR 2) through the two-input gate, a j+1 And a is also input to the second OR circuit (OR 2) by the AND operation, the two pulses are combined into a pulse with the same width as the narrow pulse clock signal a in the second OR circuit (OR 2) and enter the reverse delay chain, and the circuit works normally without generating burrs.
The implementation of the embodiment of the invention has the following beneficial effects:
the invention provides a burr-free 50% duty cycle correction circuit based on a half-clock period delay chain, which eliminates the risk of burrs output by the circuit with small area and power consumption cost through a data LATCH (LATCH), a gating device (MUX) and a second OR circuit (OR 2) in the half-clock period delay chain, and increases the robustness of a circuit system.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (2)

1. A digital duty cycle correction circuit system, comprising a narrow pulse generation circuit, a half clock period delay circuit, and a trigger reset latch;
an input port of the narrow pulse generating circuit receives an input clock signal, and an output port of the narrow pulse generating circuit is respectively connected to the input port of the half clock period delay circuit and the S port of the trigger reset latch; an output port of the half-clock period delay circuit is connected to an R port of the trigger reset latch; the output port of the trigger reset latch obtains an output clock signal;
the half-clock period delay circuit comprises a forward delay chain, a reverse delay chain and a logic gate array; the forward delay chain is connected to the array of logic gates, which is connected to the reverse delay chain;
the forward delay chain comprises n cascaded forward delay units, wherein n is an even number greater than or equal to 2; the reverse delay chain comprises n/2 reverse delay units in cascade; the logic gate array comprises n/2 logic gate circuit modules in parallel, and each logic gate circuit module is correspondingly connected to 2 forward delay units and 1 reverse delay unit;
each stage of forward delay unit is provided with 2 input ports and 1 output port, the 2 input ports are a first input port of the forward delay unit and a second input port of the forward delay unit, the first input port of each stage of forward delay unit is connected to a power supply, the second input port of the 1 st stage of forward delay unit is connected to the output port of the narrow pulse generating circuit, and the output port of the previous stage of forward delay unit is connected to the second input port of the next stage of forward delay unit; the output port of the i-th stage forward delay unit obtains a forward output signal a i Wherein i=1, 2,..n;
each stage of reverse delay unit is provided with 2 input ports and 1 output port, the 2 input ports are a first input port of the reverse delay unit and a second input port of the reverse delay unit, the first input port of each stage of reverse delay unit is connected to a power supply, the output port of the previous stage of reverse delay unit is connected to the second input port of the next stage of reverse delay unit, and the output port of the last stage of reverse delay unit is connected to the R port of the trigger reset latch;
the logic gate circuit module comprises a first AND gate circuit, a second AND gate circuit and a first OR gate circuit; the first AND gate circuit and the second AND gate circuit are provided with 2 input ports and 1 output port; the first input port of the first AND gate circuit and the first input port of the second AND gate circuit are connected to the output port of the narrow pulse generating circuit; a second input port of the first and circuit in the kth logic gate circuit module is connected to an output port of the n+1-2k stage forward delay unit, and a second input port of the second and circuit is connected to an output port of the n+2-2k stage forward delay unit, wherein k=1, 2. The first OR gate circuit is provided with 2 input ports and 1 output port; the first input port of the first OR gate circuit is connected with the output port of the first AND gate circuit, and the second input port of the first OR gate circuit is connected with the output port of the second AND gate circuit;
the logic gate circuit module further comprises a second OR gate circuit, a data latch and a two-input gate; the second OR gate circuit is provided with 2 input ports and 1 output port; the output port of the first OR gate is connected to the first input port of the two-input gate;
the clock port of the data latch is connected to the output end of the second AND gate circuit, and the data port of the data latch is connected to a power supply; the inverting output port of the data latch is connected to the selection signal input port of the two-input gate; a second input port of the two-input gate is connected to a power supply, and an output port of the two-input gate is connected to a first input port of the second OR gate;
the second input port of the second OR gate of the 1 st logic gate module is grounded; the second input port of the second OR gate of the kth logic gate module is connected to the kth-1 logic gateAn output port of a first OR gate of the module, where k>1, a step of; the output port of the second OR gate of the kth logic gate module is connected to the second input port of the kth stage inverse delay unit, i.e. the second input port of the kth stage inverse delay unit receives the output signal b of the kth logic gate module k Where k=1, 2,..n/2.
2. The digital duty cycle correction circuit system as set forth in claim 1,
the forward delay unit and the reverse delay unit are delay units formed by 1 AND gate circuit and two stages of buffers.
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