CN110166028A - Digital dock frequency multiplier circuit system, digital dock frequency-doubled signal generation method - Google Patents
Digital dock frequency multiplier circuit system, digital dock frequency-doubled signal generation method Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
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Abstract
The invention discloses a kind of digital dock frequency multiplier circuit systems, comprising: duty ratio digital calibration circuit module, OR circuit module；The duty ratio digital calibration circuit module includes impulse generator, half clock cycle delay circuit；Output clock signal of the input clock signal after duty ratio digital calibration circuit module, OR circuit module output frequency multiplication.In addition, the invention also discloses a kind of digital dock frequency-doubled signal generation methods.The shake of output clock is significantly reduced using the digital dock frequency multiplier circuit system calibrated the present invention is based on 50% duty ratio, save circuit power consumption and area, the response time between input clock signal FIN to output clock signal FOUT reduces 33% simultaneously, can support high-speed response scene.
Description
Technical field
The present invention relates to digital circuit technique field, in particular to a kind of digital dock frequency multiplier circuit system and digital dock
Frequency-doubled signal generation method.
Background technique
Digital dock frequency multiplier circuit is universal asynchronous receiving-transmitting transmitter (Universal Asynchronous Receiver/
Transmitter, abbreviation UART) it commonly uses in the integrated circuits such as interface, phaselocked loop (Phase-locked loops, abbreviation PLL)
Circuit module.For universal asynchronous receiving-transmitting transmitter (UART) interface, digital dock frequency multiplier circuit can be improved universal asynchronous
The Transmission bit rate of receiving-transmitting transmitter；And for phaselocked loop (PLL) circuit, when increasing number on the input path of reference clock
The crystal oscillator frequency that clock frequency multiplier circuit can be such that phaselocked loop (PLL) is supported has more diversity, to improve integrated circuit system
Flexibility and reusability.
There are many schemes for realizing digital dock frequency multiplier circuit in the prior art, such as can be equal to 2 by internal frequency dividing ratio
Phase-locked loop frequency integrator realize.The advantages of implementation is not special to waveform, the duty ratio of input clock etc.
It is required that while have benefited from the characteristic of closed-loop system, output frequency is stable, noise characteristic is good, by technique, temperature, supply voltage etc.
It influences smaller；But at the same time, circuit area and power consumption cost are too big in this kind of implementation, and total system complexity is higher.
Digital dock frequency multiplier circuit system shown in Figure 1 to be realized in the prior art based on XOR gate and delay chain.
The period of the input clock signal FIN of the system is T, obtains postpones signal FIN_D after delay chain (Delay-line), prolongs
The retardation of slow chain (Delay-line) is t；Input clock signal FIN and postpones signal FIN_D carries out exclusive or (XOR) operation,
To obtain the output clock signal FOUT of two frequencys multiplication, the pulsewidth of two frequency multiplied clock signal FOUT of output and delay chain length at
Direct ratio.Circuit system in above-mentioned implementation is all made of digital gate circuit, simple for structure, robustness is good, especially suitable
In the lower situation of input frequency；But it is accurate 50% that the implementation, which needs the duty ratio of input clock, otherwise will be occurred
Clock as shown in Figure 2 is along jitter problem.Therefore, this kind digital dock frequency multiplier circuit system as shown in Figure 1 in signal input
Before system, input clock signal has to pass through the calibration process of 50% duty ratio.50% duty-ratio calibrating circuit can pass through simulation
Or digital form is realized；Since analog form includes passive device, area is larger；Digital circuit mode area is small, and reliability is more
It is good, thus obtained wider use.
Referring to being 50% duty ratio digital calibration circuit (Duty commonly used in the prior art shown in dotted line frame in Fig. 3
Cycle Correction, abbreviation DCC) module.The 50% duty ratio digital calibration circuit module uses impulse generator first
The input clock signal of any duty ratio (x%T) is converted narrow pulse clock signal by (Pulse Generator, abbreviation PG)
a；Then pass through half clock cycle delay circuit (Half Cycle Delay Line, abbreviation HCDL) for narrow pulse clock signal a
Accurately postpone 1.5 input clock cycles and obtains delay narrow pulse clock signal b；Postpone forward and backward narrow pulse clock a and b
The clock signal that with the same frequency of input clock signal and duty ratio is 50% is obtained after triggering reset latch (SR-LATCH)
C, clock signal c, may finally using the digital dock frequency multiplier circuit realized as shown in Figure 1 based on XOR gate and delay chain
Two stable frequency multiplied clock signal FOUT are exported, when this joined the number of 50% duty ratio digital calibration circuit (DCC) module
The timing diagram of clock frequency multiplier circuit system is as shown in Figure 4.
It is illustrated in figure 5 the typical realization circuit for triggering reset latch (SR-LATCH) in the prior art, as shown in Figure 6
Typical for XOR gate in the prior art (XOR) realizes circuit, is illustrated in figure 7 delay chain (Delay-line) in the prior art
Typical realize circuit.Wherein, triggering reset latch (SR-LATCH) is by gate (MUX) and D flip-flop (DFF) group
At to guarantee the input route matching of two input signals of S and R；XOR gate (XOR) includes 5 unit gate circuits；And delay chain
(Delay-line) it is made of multilevel delay unit (Δ) cascade, to guarantee that output clock has reliable pulsewidth.
However, inventor it has been investigated that, in the prior art based on 50% duty ratio calibration digital dock frequency multiplier circuit
Although two double frequency functions may be implemented in system, but circuit structure is still more complicated, and especially Fig. 5, Fig. 6, circuit shown in Fig. 7 are real
It is existing, circuit area and dynamic power consumption is all larger and clock path is very long.Every level-one door electricity for clock signal, on path
Lu Douhui accumulated phase noise increases the shake on clock edge, in turn results in the deterioration of system performance.In order to reduce clock jitter,
Adoptable improved method is to increase its grid width and grid length to the metal-oxide-semiconductor equal proportion of circuits at different levels on clock path, reduces its sudden strain of a muscle
Bright noise contribution, but circuit area can be increased in this way with quadratic relationship；Or when increasing the driving capability of circuits at different levels to inhibit
Clock shake, but circuit power consumption can dramatically increase.Therefore, the clock path of digital dock frequency multiplier circuit is too long can severe exacerbation clock
Shake, while increasing the power consumption and area cost of circuit.Secondly as the input terminal of half clock cycle delay circuit (HCDL) is believed
There are the delays of 1.5 input clock cycles between number a to output end signal b, and which determine the digital dock frequency multiplier circuit systems
The starting working time of system, by first edge prolonging to first edge of output clock signal FOUT of input clock signal FIN
It is late 1.5 input clock cycles, as shown in figure 4, output clock signal FOUT needs to wait after 1.5 input clock cycles
It can normally export, this is unacceptable for needing the application scenarios of high-speed response.
Summary of the invention
Based on this, for solve in the prior art the technical issues of, spy of the present invention proposes a kind of digital dock frequency multiplier circuit
System:
The digital dock frequency multiplier circuit system includes duty ratio digital calibration circuit module, OR circuit module；It is described
Duty ratio digital calibration circuit module includes impulse generator, half clock cycle delay circuit；The output of the impulse generator
End is connected to the input terminal of the half clock cycle delay circuit and the first input end of the OR circuit module；When described half
The output end of clock period delay circuit is connected to the second input terminal of the OR circuit module；
The impulse generator receives the dagital clock signal of any duty ratio as input clock signal, the pulse hair
Input clock signal is converted into narrow pulse signal and exported by raw device；
The half clock cycle delay circuit receives the narrow pulse signal that the impulse generator generates, when described half
Clock period delay circuit will the narrow pulse signal postpone 1.5 input clock cycles after generate delay narrow pulse signal and defeated
Out；
The OR circuit module receives the narrow pulse signal that the impulse generator generates and half clock week
The delay narrow pulse signal that phase delay circuit generates, it is narrow to the narrow pulse signal and the delay by the OR circuit module
Pulse signal carries out logic or operation obtains two frequency multiplied clock signals as output clock signal and exports.
In one embodiment, the narrow pulse signal and the delay narrow pulse signal frequency is identical, phase difference 3
π。
In one embodiment, the digital dock frequency multiplier circuit system includes one or more cascade expansion frequency multiplication
Unit, each multiplier unit of expanding includes the half clock cycle delay circuit and expansion multiplier unit for expanding multiplier unit
OR circuit module.
In one embodiment, when the digital dock frequency multiplier circuit system includes a cascade expansion multiplier unit
When, two frequency multiplied clock signals of the OR circuit module output are divided into two-way and are input to the expansion multiplier unit, wherein one
Road be input to it is described expand multiplier unit half clock cycle delay circuit, another way be input to it is described expand multiplier unit or
The output signal of the first input end of gate circuit module, the half clock cycle delay circuit for expanding multiplier unit is input to institute
State the second input terminal for expanding the OR circuit module of multiplier unit；The OR circuit module output four for expanding multiplier unit
Frequency multiplied clock signal.
In one embodiment, when the digital dock frequency multiplier circuit system includes multiple cascade expansion multiplier units
When, the output clock signal that previous stage expands multiplier unit is divided into two-way and is input to expansion multiplier unit when prime, wherein one
Road is input to when prime expands the half clock cycle delay circuit of multiplier unit, and another way is input to when prime expands multiplier unit
OR circuit module first input end, when prime expand multiplier unit half clock cycle delay circuit output signal it is defeated
Enter to the second input terminal of the OR circuit module for expanding multiplier unit when prime；When prime expands the OR circuit of multiplier unit
Module exports frequency multiplied clock signal.
In addition, the technical issues of to solve in the prior art, spy proposes a kind of digital dock frequency-doubled signal generation method,
Include:
The dagital clock signal of step 1, any duty ratio is input to impulse generator as input clock signal, described
Input clock signal is converted into narrow pulse signal and exported by impulse generator；
Step 2, the narrow pulse signal that the impulse generator generates are input to half clock cycle delay circuit, institute
It states after the narrow pulse signal of input is postponed 1.5 input clock cycles by half clock cycle delay circuit and generates the narrow arteries and veins of delay
It rushes signal and exports；
Step 3, the narrow pulse signal and the half clock cycle delay circuit that the impulse generator generates generate
Delay narrow pulse signal be input to OR circuit module, by the OR circuit module to the narrow pulse signal and institute
It states delay narrow pulse signal progress logic or operation obtains two frequency multiplied clock signals as output clock signal and exports.
In one embodiment, the narrow pulse signal and the delay narrow pulse signal frequency is identical, phase difference 3
π。
In one embodiment, the output of the OR circuit module is connected to one or more cascade expansion frequency multiplication
Unit, each multiplier unit of expanding includes the half clock cycle delay circuit and expansion multiplier unit for expanding multiplier unit
OR circuit module.
In one embodiment, when the digital dock frequency multiplier circuit system includes a cascade expansion multiplier unit
When, two frequency multiplied clock signals of the OR circuit module output are divided into two-way and are input to the expansion multiplier unit, wherein one
Road be input to it is described expand multiplier unit half clock cycle delay circuit, another way be input to it is described expand multiplier unit or
The output signal of the first input end of gate circuit module, the half clock cycle delay circuit for expanding multiplier unit is input to institute
State the second input terminal for expanding the OR circuit module of multiplier unit；The OR circuit module output four for expanding multiplier unit
Frequency multiplied clock signal.
In one embodiment, when the digital dock frequency multiplier circuit system includes multiple cascade expansion multiplier units
When, the output clock signal that previous stage expands multiplier unit is divided into two-way and is input to expansion multiplier unit when prime, wherein one
Road is input to when prime expands the half clock cycle delay circuit of multiplier unit, and another way is input to when prime expands multiplier unit
OR circuit module first input end, when prime expand multiplier unit half clock cycle delay circuit output signal it is defeated
Enter to the second input terminal of the OR circuit module for expanding multiplier unit when prime；When prime expands the OR circuit of multiplier unit
Module exports frequency multiplied clock signal.
Implement the embodiment of the present invention, will have the following beneficial effects:
In the inventive solutions, the triggering reset latch in the clock path of digital dock frequency multiplier circuit system
(SR-LATCH), delay chain (Delay-line) and XOR gate (XOR) enormously simplify circuit only with one or (OR) is replaced
Structure shortens clock path.
It is proposed by the present invention based on 50% duty ratio calibration digital dock frequency multiplier circuit system pass through simplify circuit structure,
Shorten clock path, significantly reduces the shake of output clock, save circuit power consumption and area, while input clock signal
33% is reduced to the response time between output clock signal, can support high-speed response scene.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Wherein:
Fig. 1 is the digital dock frequency multiplier circuit system schematic realized in the prior art based on XOR gate and delay chain；
Fig. 2 is that schematic diagram of the clock along jitter problem occurs in digital dock frequency multiplier circuit system in the prior art；
Fig. 3 is that the digital dock frequency multiplier circuit system of 50% duty ratio digital calibration circuit module is added in the prior art to show
It is intended to；
Fig. 4 is the digital dock frequency multiplier circuit system that joined 50% duty ratio digital calibration circuit module in the prior art
Timing diagram；
Fig. 5 is the circuit diagram for triggering reset latch in the prior art；
Fig. 6 is the circuit diagram of XOR gate in the prior art；
Fig. 7 is the circuit diagram of delay chain in the prior art；
Fig. 8 is digital dock frequency multiplier circuit system schematic of the invention；
Fig. 9 is the timing diagram of digital dock frequency-doubled signal of the invention；
Figure 10 is that the multiple frequence of digital dock frequency multiplier circuit system of the invention extends schematic diagram.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The present invention proposes a kind of digital dock frequency-doubled signal generation method, includes the following steps:
The dagital clock signal FIN of step 1, any duty ratio (x%T) is input to pulse hair as input clock signal
Input clock signal is converted into narrow pulse signal a and exported by raw device (PG), the impulse generator (PG)；
Step 2, the narrow pulse signal a that the impulse generator (PG) is converted into are input to half clock cycle and prolong
The narrow pulse signal a of input is postponed 1.5 inputs by slow circuit (HCDL), the half clock cycle delay circuit (HCDL)
Clock cycle (1.5T) generates delay narrow pulse signal b afterwards and exports；
Wherein, identical, phase difference is 3 π to the narrow pulse signal a with the frequency for postponing narrow pulse signal b；
Step 3, the narrow pulse signal a and the half clock cycle deferred telegram that the impulse generator (PG) generates
The delay narrow pulse signal b that road (HCDL) generates is input to simultaneously or door (OR) circuit module, by described or door (OR) circuit mould
Block carries out logic to the narrow pulse signal a and delay narrow pulse signal b or operation is obtained as output clock letter
Number two frequency multiplied clock signal FOUT and export；It is illustrated in figure 9 the timing diagram of above-mentioned digital dock frequency-doubled signal generation method.
It may further expand and obtain multiple frequence clock signal.The output of described or door (OR) circuit module is connected to one
Or multiple cascade expansion multiplier units, each multiplier unit of expanding includes the half clock cycle delay for expanding multiplier unit
Circuit and the OR circuit module for expanding multiplier unit.
When the output of described or door (OR) circuit module is connected to an expansion multiplier unit, described or door (OR) circuit mould
Two frequency multiplied clock signals of block output are divided into two-way and are input to the expansion multiplier unit, wherein being input to described expand again all the way
The half clock cycle delay circuit of frequency unit, another way are input to the first defeated of the OR circuit module for expanding multiplier unit
Enter end, it is described expand multiplier unit half clock cycle delay circuit output signal be input to it is described expand multiplier unit or
Second input terminal of gate circuit module；The OR circuit module for expanding multiplier unit exports quadruple clock signal.
Further expand obtain multiple frequence clock signal, when the output of the OR circuit module be connected to it is multiple cascade
When expanding multiplier unit, the output clock signal that previous stage expands multiplier unit is divided into two-way and is input to when prime expands frequency multiplication list
Member, wherein being input to all the way when prime expands the half clock cycle delay circuit of multiplier unit, another way is input to when prime is opened up
The first input end for opening up the OR circuit module of multiplier unit, when prime expands the half clock cycle delay circuit of multiplier unit
Output signal is input to when prime expands the second input terminal of the OR circuit module of multiplier unit；When prime expands multiplier unit
OR circuit module export frequency multiplied clock signal.
It is shown in Figure 8, the invention also provides a kind of digital dock frequency multiplier circuit system, the digital dock frequency multiplication electricity
Road system includes duty ratio digital calibration circuit module or door (OR) circuit module；The duty ratio digital calibration circuit module
Including impulse generator (PG), half clock cycle delay circuit (HCDL)；The output end of the impulse generator (PG) is connected to
The input terminal of the half clock cycle delay circuit (HCDL) and the first input end of described or door (OR) circuit module；Described half
The output end of clock cycle delay circuit (HCDL) is connected to described or door (OR) circuit module the second input terminal；
The dagital clock signal FIN that the impulse generator (PG) receives any duty ratio (x%T) believes as input clock
Number, input clock signal is converted into narrow pulse signal and exported by the impulse generator (PG)；
The half clock cycle delay circuit (HCDL) receives the burst pulse letter that the impulse generator (PG) generates
The narrow pulse signal a is postponed 1.5 input clock cycles (1.5T) by number a, the half clock cycle delay circuit (HCDL)
Delay narrow pulse signal b is generated afterwards and is exported；
Wherein, identical, phase difference is 3 π to the narrow pulse signal a with the frequency for postponing narrow pulse signal b；
Described or door (OR) circuit module receives the narrow pulse signal a that the impulse generator (PG) generates and described
The delay narrow pulse signal b that half clock cycle delay circuit (HCDL) generates, by described or door (OR) circuit module to described narrow
Pulse signal a and the delay narrow pulse signal b progress logic or operation obtain two frequency doubling clocks as output clock signal
Signal FOUT is simultaneously exported.Wherein, described or door (OR) circuit module can be adopted according to system application demand to be designed in various manners
It realizes, described or door (OR) circuit module is formed by nor gate and NOT gate connection as shown in Figure 8.
Although still remaining 1.5 inputs between the input signal and output signal of half clock cycle delay circuit (HCDL)
The inherent delay of clock cycle (1.5T), but due to or door (OR) circuit module directly by input signal and output signal by patrolling
It collects or operation synthesizes two frequency multiplied clock signal FOUT, since second edge of the narrow pulse signal a of input, when as output
Two frequency multiplied clock signal FOUT of clock signal are just stable, thus input clock signal FIN to output clock signal FOUT it
Between delay be only 1 input clock cycle (T).
The digital dock frequency multiplier circuit system further includes one or more cascade expansion multiplier unit, each expansion
Multiplier unit includes the half clock cycle delay circuit for expanding multiplier unit and the OR circuit mould for expanding multiplier unit
Block.
When the digital dock frequency multiplier circuit system includes a cascade expansion multiplier unit, described or door (OR) electricity
Two frequency multiplied clock signals of road module output are divided into two-way and are input to the expansion multiplier unit, wherein being input to described open up all the way
The half clock cycle delay circuit of multiplier unit is opened up, another way is input to the of the OR circuit module for expanding multiplier unit
The output signal of one input terminal, the half clock cycle delay circuit for expanding multiplier unit is input to the expansion multiplier unit
OR circuit module the second input terminal；The OR circuit module for expanding multiplier unit exports quadruple clock signal.
When the digital dock frequency multiplier circuit system includes multiple cascade expansion multiplier units, previous stage expands frequency multiplication
The output clock signal of unit is divided into two-way and is input to when prime expands multiplier unit, wherein being input to all the way when prime is expanded again
The half clock cycle delay circuit of frequency unit, another way are input to when prime expands the first of the OR circuit module of multiplier unit
Input terminal, when the output signal that prime expands the half clock cycle delay circuit of multiplier unit is input to when prime expands frequency multiplication list
Second input terminal of the OR circuit module of member；When prime expands the OR circuit module output frequency doubling clock letter of multiplier unit
Number.
Technical solution of the present invention can carry out expanding to obtain multiple frequence clock signal, as shown in Figure 10.Due to defeated
For two frequency multiplied clock signal 2*FIN sheets out as narrow pulse clock signal, rear class does not need impulse generator (PG) can be straight
Succeed continuous expansion frequency.By two frequency multiplied clock signals of output continue to be input to half clock cycle delay circuit (HCDL) and
Or door (OR) circuit module, to obtain quadruple clock signal 4*FIN for clock signal is double again；By the quadruple of output
Clock signal continues to be input to half clock cycle delay circuit (HCDL) and/or door (OR) circuit module, thus by clock signal after
Continue and double obtain octonary clock signal 8*FIN, and so on until working frequency reaches the technique upper limit.In Figure 10, from two
Frequency multiplied clock signal 2*FIN is multiplied to the retardation of the half clock cycle delay circuit (HCDL2) of quadruple clock signal 4*FIN
For the period of 1.5 2*FIN；If expanding to octuple frequency circuit, for 1.5 4*FIN periods, subsequent and so on.
Implement the embodiment of the present invention, will have the following beneficial effects:
In the inventive solutions, it is multiple to eliminate triggering included in digital dock frequency multiplier circuit in the prior art
Position latch (SR-LATCH), delay chain (Delay-Line) and XOR gate (XOR) circuit module, and double of clock cycle delay
The input/output signal of circuit (HCDL) is directly done or (OR) operation obtains two frequency multiplied clock signals.With the scheme of the prior art
It compares, technical solution of the present invention enormously simplifies circuit structure, and shortens clock path, is saving the same of area and power consumption
When improve output clock and mutually make an uproar performance, and from the sequential time delay for being input to output be only 1 input clock cycle, it is more applicable
In high-speed response system.
The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to the foregoing embodiments
Invention is explained in detail, those skilled in the art should understand that: it still can be to aforementioned each implementation
Technical solution documented by example is modified or equivalent replacement of some of the technical features；And these modification or
Replacement, can't be such that the essence of corresponding technical solution departs from the spirit and scope of the technical scheme of various embodiments of the present invention.
Claims (10)
1. a kind of digital dock frequency multiplier circuit system, which is characterized in that
The digital dock frequency multiplier circuit system includes duty ratio digital calibration circuit module, OR circuit module；The duty
It include impulse generator, half clock cycle delay circuit than digital calibration circuit module；The output end of the impulse generator connects
It is connected to the input terminal of the half clock cycle delay circuit and the first input end of the OR circuit module；The half clock week
The output end of phase delay circuit is connected to the second input terminal of the OR circuit module；
The impulse generator receives the dagital clock signal of any duty ratio as input clock signal, the impulse generator
Input clock signal is converted into narrow pulse signal and is exported；
The half clock cycle delay circuit receives the narrow pulse signal that the impulse generator generates, the half clock week
Phase delay circuit generates delay narrow pulse signal after the narrow pulse signal is postponed 1.5 input clock cycles and exports；
The OR circuit module receives the narrow pulse signal that the impulse generator generates and the half clock cycle is prolonged
The delay narrow pulse signal of slow circuit evolving, by the OR circuit module to the narrow pulse signal and the delay burst pulse
Signal carries out logic or operation obtains two frequency multiplied clock signals as output clock signal and exports.
2. digital dock frequency multiplier circuit system according to claim 1, which is characterized in that
The narrow pulse signal is identical with the frequency of the delay narrow pulse signal, phase difference is 3 π.
3. digital dock frequency multiplier circuit system according to claim 1 or 2, which is characterized in that
The digital dock frequency multiplier circuit system includes one or more cascade expansion multiplier unit, each expansion frequency multiplication list
Member includes the half clock cycle delay circuit for expanding multiplier unit and the OR circuit module for expanding multiplier unit.
4. digital dock frequency multiplier circuit system according to claim 3, which is characterized in that
When the digital dock frequency multiplier circuit system includes a cascade expansion multiplier unit, the OR circuit module is defeated
Two frequency multiplied clock signals out are divided into two-way and are input to the expansion multiplier unit, wherein being input to the expansion frequency multiplication list all the way
The half clock cycle delay circuit of member, another way are input to the first input of the OR circuit module for expanding multiplier unit
End, it is described expand multiplier unit half clock cycle delay circuit output signal be input to it is described expand multiplier unit or door
Second input terminal of circuit module；The OR circuit module for expanding multiplier unit exports quadruple clock signal.
5. digital dock frequency multiplier circuit system according to claim 3 or 4, which is characterized in that
When the digital dock frequency multiplier circuit system includes multiple cascade expansion multiplier units, previous stage expands multiplier unit
Output clock signal be divided into two-way and be input to the expansion multiplier unit, wherein being input to the multiplier unit of expanding all the way
Half clock cycle delay circuit, another way are input to the first input end of the OR circuit module for expanding multiplier unit, institute
The output signal for stating the half clock cycle delay circuit of expansion multiplier unit is input to the OR circuit for expanding multiplier unit
Second input terminal of module；The OR circuit module for expanding multiplier unit exports frequency multiplied clock signal.
6. a kind of digital dock frequency-doubled signal generation method characterized by comprising
The dagital clock signal of step 1, any duty ratio is input to impulse generator, the pulse as input clock signal
Input clock signal is converted into narrow pulse signal and exported by generator；
Step 2, the narrow pulse signal that the impulse generator generates are input to half clock cycle delay circuit, and described half
Clock cycle delay circuit generates delay burst pulse letter after the narrow pulse signal of input is postponed 1.5 input clock cycles
Number and export；
Step 3, what the narrow pulse signal and the half clock cycle delay circuit that the impulse generator generates generated prolongs
Slow narrow pulse signal is input to OR circuit module, to the narrow pulse signal and described is prolonged by the OR circuit module
Slow narrow pulse signal carries out logic or operation obtains two frequency multiplied clock signals as output clock signal and exports.
7. digital dock frequency-doubled signal generation method according to claim 6, which is characterized in that
The narrow pulse signal is identical with the frequency of the delay narrow pulse signal, phase difference is 3 π.
8. digital dock frequency-doubled signal generation method according to claim 6 or 7, which is characterized in that
The output of the OR circuit module is connected to one or more cascade expansion multiplier unit, each expansion frequency multiplication list
Member includes the half clock cycle delay circuit for expanding multiplier unit and the OR circuit module for expanding multiplier unit.
9. digital dock frequency-doubled signal generation method according to claim 8, which is characterized in that
When the digital dock frequency multiplier circuit system includes a cascade expansion multiplier unit, the OR circuit module is defeated
Two frequency multiplied clock signals out are divided into two-way and are input to the expansion multiplier unit, wherein being input to the expansion frequency multiplication list all the way
The half clock cycle delay circuit of member, another way are input to the first input of the OR circuit module for expanding multiplier unit
End, it is described expand multiplier unit half clock cycle delay circuit output signal be input to it is described expand multiplier unit or door
Second input terminal of circuit module；The OR circuit module for expanding multiplier unit exports quadruple clock signal.
10. digital dock frequency-doubled signal generation method according to claim 8 or claim 9, which is characterized in that
When the output of the OR circuit module is connected to multiple cascade expansion multiplier units, previous stage expands multiplier unit
Output clock signal be divided into two-way and be input to the expansion multiplier unit, wherein being input to the multiplier unit of expanding all the way
Half clock cycle delay circuit, another way are input to the first input end of the OR circuit module for expanding multiplier unit, institute
The output signal for stating the half clock cycle delay circuit of expansion multiplier unit is input to the OR circuit for expanding multiplier unit
Second input terminal of module；The OR circuit module for expanding multiplier unit exports frequency multiplied clock signal.
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| CN201910508700.4A CN110166028A (en) | 2019-06-13 | 2019-06-13 | Digital dock frequency multiplier circuit system, digital dock frequency-doubled signal generation method |
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| CN201910508700.4A CN110166028A (en) | 2019-06-13 | 2019-06-13 | Digital dock frequency multiplier circuit system, digital dock frequency-doubled signal generation method |
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| CN110492872A (en) * | 2019-09-12 | 2019-11-22 | 珠海微度芯创科技有限责任公司 | Digital duty-cycle correction circuit system |
| CN110649922A (en) * | 2019-10-26 | 2020-01-03 | 复旦大学 | Digital clock frequency multiplier |
| CN111092600A (en) * | 2020-01-15 | 2020-05-01 | 电子科技大学 | FPGA frequency doubling method based on phase superposition method |
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| CN111092600A (en) * | 2020-01-15 | 2020-05-01 | 电子科技大学 | FPGA frequency doubling method based on phase superposition method |
| CN111092600B (en) * | 2020-01-15 | 2021-06-01 | 电子科技大学 | FPGA frequency doubling method based on phase superposition method |
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