CN110492872A - Digital duty-cycle correction circuit system - Google Patents
Digital duty-cycle correction circuit system Download PDFInfo
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- CN110492872A CN110492872A CN201910861413.1A CN201910861413A CN110492872A CN 110492872 A CN110492872 A CN 110492872A CN 201910861413 A CN201910861413 A CN 201910861413A CN 110492872 A CN110492872 A CN 110492872A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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Abstract
The invention discloses a kind of digital duty-cycle correction circuit systems, comprising: narrow-pulse generation circuit, half clock cycle delay circuit, triggering reset latch；Narrow-pulse generation circuit receives input clock signal, and the output port of narrow-pulse generation circuit is respectively connected to the input port of half clock cycle delay circuit and triggers the port S of reset latch；The output port of half clock cycle delay circuit is connected to the port R of the triggering reset latch；The output port of the triggering reset latch obtains output clock signal.Technical solution of the present invention is eliminated the risk of circuit output burr with small area and power consumption cost, increases the robustness of circuit system by increasing data latches, gate and OR circuit in half clock cycle delay chain.
Description
Technical field
The present invention relates to field of circuit technology, in particular to a kind of digital duty-cycle correction circuit system.
Background technique
In the prior art, 50% duty-cycle correction circuit (Duty Cycle Correction, abbreviation DCC) is in switch electricity
Capacitive circuit, phaselocked loop (Phase-Locked Loops, abbreviation PLL), Synchronous Dynamic Random Access Memory (Synchronous
Dynamic Random-Access Memory, abbreviation SDRAM) and dynamic random access memory (Dynamic Random
Access Memory, abbreviation DRAM) it all has a wide range of applications in system.For example, in the phaselocked loop for supporting a variety of reference frequencies
In, the processing of 50% duty cycle correction is needed before input reference clock frequency multiplication to eliminate the shake on clock edge after frequency multiplication；And in dynamic
In random access memory (DRAM) and Synchronous Dynamic Random Access Memory (SDRAM), based on prolonging for 50% duty cycle correction
Slow phaselocked loop (Delay-Locked Loop, abbreviation DLL) is usually utilized to improve output data rate.
Common duty-cycle correction circuit has analog- and digital- two kinds of implementations.Wherein, simulated implementation mode includes nothing
Source device, area is larger, and cannot be compatible with pure digi-tal technique；And digital circuit area is small, reliability is higher, thus has obtained more
It is widely applied, particular circuit configurations are as shown in Figure 1.Digital duty-cycle correction circuit is first with narrow-pulse generation circuit
The input clock signal FIN (period T) of any duty ratio (x%) is converted narrow arteries and veins by (Pulse Generator, abbreviation PG)
Clock signal a is rushed, using half clock cycle delay circuit (Half Cycle Delay Line, abbreviation HCDL) by burst pulse
Clock accurately postpones 1.5 input clock signal cycle Ts and obtains b；It is narrow after narrow pulse clock signal a, delay before delay
Pulse clock signal b obtains believing with input clock signal FIN with the output of frequency after triggering reset latch (SR-LATCH)
Number, i.e. the timing diagram ginseng of the output clock signal FOUT of 50% duty ratio, the process are as shown in Fig. 2.
As shown in Fig. 1, the core component in 50% duty-cycle correction circuit is half clock cycle delay circuit
(HCDL).The circuit structure of half clock cycle delay circuit (HCDL) is as shown in Fig. 3, includes 31 (Forward of forward delay chain
Delay Line), with door (&) and or door (OR) array, revertive delay chain 32 (Backward Delay Line) these three composition
Part.Wherein, forward delay chain 31 and revertive delay chain 32 are cascaded by delay cell (Δ), the delay cell (Δ)
Structure it is as shown in Fig. 4, include an OR circuit (42) and two-stage buffer (41).In forward delay chain and revertive delay
In chain, wherein 1 input terminal of the delay cell (Δ) of the first order needs often to be grounded VSS to guarantee that delay cell (Δ) is opened.
In attached drawing 3, every 2 delay cell in forward delay chain passes through 2 companies corresponding with door (&) circuit and 1 or (OR) circuit
Connecing the delay cell in 1 revertive delay chain, i.e. the total delay unit number of revertive delay chain 32 is the half of forward delay chain 31,
Wherein, the delay cell in forward delay chain is also referred to as forward delay unit, and the delay cell in revertive delay chain is also claimed
For inverting delay cells.As shown in Fig. 3, with 5 10 forward delay units of forward direction delay chain, revertive delay chain revertive delays
For unit as an example, attached drawing 5 is corresponding half clock cycle delay circuit (HCDL) working timing figure, input signal a is narrow arteries and veins
The narrow pulse clock of generation circuit (PG) output is rushed, setting pulse width is identical as cell delay amount Δ, and input signal a passes through
Forward delay unit in forward delay chain successively postpones, the output signal a of forward delay unit1~a10And with input signal a
It does and (&) operation, when retardation reaches 1 signal period (1T), i.e. output signal a in attached drawing 510, this grade of forward delay
Unit is corresponding to generate pulse signal with door (&), and after corresponding or door (OR) circuit, which, which enters, reversely prolongs
Slow chain, i.e. signal b1 in attached drawing 3,5, since other export 0 with door (&) and its corresponding or door (OR), revertive delay chain
32 keep it turned on, and pulse signal b1 exports final output signal b by revertive delay chain.Through or door (OR) circuit
Afterwards, which enters in revertive delay chain.Since due to corresponding 1 inverting delay cells of every 2 forward delay units, institute
It is 0.5T with reversed total delay amount, ignores the influence with door (&) circuit and/or door (OR) circuit self delay, can obtain and reversely prolong
Total delay between the output signal b and input signal a of slow chain is 1.5 signal periods (1.5T).
However, inventor it has been investigated that, in the prior art, half clock cycle delay circuit (HCDL) is although may be implemented
The delay of 1.5 signal periods, but in fact, the retardation Δ due to delay cell is analog quantity, in technique, temperature and power supply
Under the influence of the fluctuating factors such as voltage, the output signal a of forward delay unit1~a10Second pulse with input signal a it
Between phase relation it is inaccurate as shown in FIG. 5 and stablize, and be possible to generate following three kinds of situations:
The first situation, second pulse of input signal a and the output signal a of some forward delay unitn(such as
a10) be just overlapped, circuit works normally and does not have error, as shown in Figure 5；
Second situation, second pulse of input signal a and the output signal a of certain two-stage forward delay unitiAnd ai+1
It partially overlaps, and i is odd number, then aiAnd ai+1Corresponding all to generate pulse signal with door, the two pulse signals can be into
Enter same or door (OR), is merged into one with input signal a with wide pulse signal bkAnd it enters in revertive delay chain, electricity
Road works normally, but has certain quantization error, and worst error value is Δ/2, and the timing diagram of this kind of situation is as shown in Figure 6；
The third situation, second pulse of input signal a and the output signal a of certain two-stage forward delay unitjAnd aj+1
It partially overlaps, and j is even number, then ajAnd aj+1It is corresponding all to generate pulse signal with door, but the two pulse signals into
Enter different OR circuits, and will not merge, and ajThe pulse ratio a of generationj+1Level-one revertive delay is passed through in the pulse of generation less
Unit leads to circuit operation irregularity so that there is burr in revertive delay chain, and the timing diagram of this kind of situation is as shown in Figure 7.
The above problem can be solved by reducing the pulse width of input signal a in the prior art, as shown in figure 8, working as
When pulse width is less than or equal to Δ/2, at this time will not there are two AND gate circuits to generate output signal simultaneously, so being not in
Burr, but second pulse of input signal a is possible to appear precisely at a in this casenAnd an+1Between, cause it is all with
Gate circuit does not all export, so as to cause circuit malfunction, operation irregularity.
Summary of the invention
Based on this, the technical issues of to solve in the prior art, spy proposes a kind of digital duty-cycle correction circuit system.
The number duty-cycle correction circuit system includes narrow-pulse generation circuit, half clock cycle delay circuit, triggering
Reset latch；
The input port of the narrow-pulse generation circuit receives input clock signal, the output of the narrow-pulse generation circuit
Port is respectively connected to the input port of the half clock cycle delay circuit and the port S of the triggering reset latch；Institute
The output port for stating half clock cycle delay circuit is connected to the port R of the triggering reset latch；The triggering resets lock
The output port of storage obtains output clock signal；
The half clock cycle delay circuit includes forward delay chain, revertive delay chain, logic gate array；The forward direction prolongs
For slow chain link to the logic gate array, the logic gate array is connected to the revertive delay chain；
The forward delay chain includes cascade n forward delay unit, and wherein n is the even number more than or equal to 2；It is described anti-
It include cascade n/2 inverting delay cells to delay chain；The logic gate array includes n/2 parallel logic gates mould
Block, each logic gates module are correspondingly connected to 2 forward delay units and 1 inverting delay cells.
In one embodiment, every grade of forward delay unit has 2 input ports and 1 output port, and described 2 defeated
Enter the second input port of first input port and forward delay unit that end is forward delay unit, every grade of forward delay list
The first input port of member is all connected to power supply, and the second input port of the 1st grade of forward delay unit is connected to the burst pulse
The output port of generation circuit, the output port of previous stage forward delay unit are connected to the second of next stage forward delay unit
Input port；The output port of i-stage forward delay unit obtain before to output signal ai, wherein i=1,2 ... n.
In one embodiment, every grade of inverting delay cells have 2 input ports and 1 output port, and described 2 defeated
Enter the second input port of first input port and inverting delay cells that end is inverting delay cells, every grade of revertive delay list
The first input port of member is all connected to power supply, and the output port of previous stage inverting delay cells is connected to next stage revertive delay
Second input port of unit, the output port of afterbody inverting delay cells are connected to the R of the triggering reset latch
Port.
In one embodiment, the logic gates module include the first AND gate circuit, the second AND gate circuit, first or
Gate circuit；First AND gate circuit, the second AND gate circuit all have 2 input ports and 1 output port；Described first with
The first input port of gate circuit, the first input port of second AND gate circuit are all connected to the narrow-pulse generation circuit
Output port；Second input port of the first AND gate circuit in k-th of logic gates module is connected to the (n+1)th -2k grades
The output port of forward delay unit, the second input port of second AND gate circuit are connected to the n-th+2-2k grades of forward delay
The output port of unit, wherein k=1,2 ... n/2；First OR circuit has 2 input ports and 1 output end
Mouthful；The first input port of first OR circuit connects the output port of the first AND gate circuit, first OR circuit
The second input port connect the second AND gate circuit output port.
In one embodiment, the logic gates module further includes the second OR circuit, data latches, two inputs
Gate；Second OR circuit has 2 input ports and 1 output port；The output end of first OR circuit
Mouth is connected to the first input port of the two inputs gate；
The clock port of the data latches is connected to the output end of second AND gate circuit, the data latches
Data port be connected to power supply；The anti-phase output port of the data latches is connected to the selection of the two inputs gate
Signal input port；Second input port of the two inputs gate is connected to power supply, the output of the two inputs gate
Port is connected to the first input port of second OR circuit；
Second input port of the second OR circuit of the 1st logic gates module is grounded；K-th of logic gates mould
Second input port of the second OR circuit of block is connected to the output of first OR circuit of -1 logic gates module of kth
Port, wherein k > 1；The output port of second OR circuit of k-th of logic gates module is connected to kth grade revertive delay
Second input port of unit, i.e. the second input port of kth grade inverting delay cells receive k-th of logic gates module
Output signal bk, wherein k=1,2 ... n/2.
In one embodiment, the forward delay unit and the inverting delay cells be all by 1 AND gate circuit and
The delay cell that two-stage buffer is constituted.
Implement the embodiment of the present invention, will have the following beneficial effects:
The present invention is by increasing data latches, gate and OR circuit in half clock cycle delay chain, with small
Area and power consumption cost eliminate circuit output burr and lead to the risk of circuit operation irregularity, increase the Shandong of circuit system
Stick.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Wherein:
Fig. 1 is digital duty-cycle correction circuit structural schematic diagram in the prior art；
Fig. 2 is the working timing figure of digital duty-cycle correction circuit in the prior art；
Fig. 3 is the structural schematic diagram of half clock cycle delay circuit in the prior art；
Fig. 4 is delay cell structural schematic diagram in the prior art；
Fig. 5 is the working timing figure under the first impulse phase relationship of half clock cycle delay circuit in the prior art；
Fig. 6 is the working timing figure under second of impulse phase relationship of half clock cycle delay circuit in the prior art；
Fig. 7 is the working timing figure under the third impulse phase relationship of half clock cycle delay circuit in the prior art；
Fig. 8 is the working sequence that half clock cycle delay circuit reduces in the case of input signal pulse width in the prior art
Figure；
Fig. 9 be the present invention in digital duty-cycle correction circuit system in half clock cycle delay circuit structural representation
Figure.
Figure 10 is the delay cell structural schematic diagram in the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The invention discloses a kind of digital duty-cycle correction circuit systems, including narrow-pulse generation circuit (PG), half clock
Period delay circuit (HCDL), triggering reset latch (SR-LATCH)；
The input port of the narrow-pulse generation circuit receives input clock signal, the output of the narrow-pulse generation circuit
Port is respectively connected to the input port of the half clock cycle delay circuit and the port S of the triggering reset latch；Institute
The output port for stating half clock cycle delay circuit is connected to the port R of the triggering reset latch；The triggering resets lock
The output port of storage obtains output clock signal；
As shown in figure 9, the half clock cycle delay circuit includes forward delay chain 91, revertive delay chain 92, logic gate
Array 93；
The forward delay chain 91 includes cascade n forward delay unit, and every grade of forward delay unit has 2 inputs
Port and 1 output port, 2 input terminals are the first input port and forward delay unit of forward delay unit
Second input port, the first input port of the forward delay unit are all connected to power vd D, the 1st grade of forward delay unit
The second input port be connected to the output port of the narrow-pulse generation circuit, the output port of previous stage forward delay unit
It is connected to the second input port of next stage forward delay unit；The output port of i-stage forward delay unit obtains preceding to defeated
Signal ai out, wherein i=1,2 ... n, n are even number；
As shown in figure 9, the forward delay units at different levels in the forward delay chain 91 are arranged successively from left to right, the leftmost side
It is the 1st grade of forward delay unit, the rightmost side is n-th grade of forward delay unit；
The revertive delay chain 92 includes cascade n/2 inverting delay cells, and every grade of inverting delay cells are defeated with 2
Inbound port and 1 output port, 2 input terminals are the first input port and inverting delay cells of inverting delay cells
The second input port, the first input port of the inverting delay cells is all connected to power vd D, afterbody (the n-th/2
Grade) inverting delay cells output port be connected to it is described triggering reset latch the port R, previous stage inverting delay cells
Output port is connected to the second input port of next stage inverting delay cells；
As shown in figure 9, the backward delay cells at different levels in the backward delay chain 92 are turned left from the right side and are arranged successively, the rightmost side
It is the 1st grade of backward delay cell, the leftmost side is the n-th/2 grade of forward delay unit；
Particularly, as shown in Figure 10, the forward delay unit and the inverting delay cells are all delay cell, described
Delay cell includes 1 and door (&) circuit and two-stage buffer 101；In forward delay chain 91, in forward delay unit with
One input of door (&) circuit often connects power supply (VDD) to guarantee the unlatching of delay cell.With using 1 or (OR) circuit and
The delay cell that two-stage buffer is constituted is compared, and occupied area, power consumption and retardation are constant.
The logic gate array 93 includes n/2 parallel logic gates module, and each logic gates module is corresponding
It is connected to 2 forward delay units and 1 inverting delay cells；The logic gates module includes the first AND gate circuit (&
1), the second AND gate circuit (&2), the first OR circuit (OR1), the second OR circuit (OR2), data latches (LATCH), two
It inputs gate (MUX)；The first AND gate circuit (&1), the second AND gate circuit (&2) all have 2 input ports and 1 it is defeated
Exit port；The first AND gate circuit (&1) first input port, the second AND gate circuit (&2) first input port
It is all connected to the output port of the narrow-pulse generation circuit；The first AND gate circuit (&1 in k-th of logic gates module)
The second input port be connected to the output port of the (n+1)th -2k grades of forward delay unit, the second AND gate circuit (&2)
Two input ports are connected to the output port of the n-th+2-2k grades of forward delay unit, wherein k=1, and 2 ... n/2, n are even number；
As shown in figure 9, each logic gates module in the logic gate array 93 is turned left from the right side and is arranged successively, it is most right
Side is the 1st logic gates module, and the leftmost side is the n-th/2 logic gates module；
First OR circuit (OR1), second OR circuit (OR2) all have 2 input ports and 1 output
Port；The first input port of first OR circuit (OR1) connects the first AND gate circuit (&1) output port, described the
Second input port of one OR circuit (OR1) connects the second AND gate circuit (&2) output port；First OR circuit
(OR1) output port is connected to the first input port IN0 of two input gate (MUX)；
The clock port CK of the data latches (LATCH) is connected to the second AND gate circuit (&2) output end,
The data port (D) of the data latches is connected to power vd D；The anti-phase output port (QN) of the data latches connects
To the selection signal input port (S) of the two inputs gate；
Second input port IN1 of two input gate (MUX) is connected to power vd D, the two inputs gate
Output port be connected to the first input port of second OR circuit；
Second input port of the second OR circuit of the 1st logic gates module is grounded VSS；K-th of logic gate electricity
Second input port of the second OR circuit of road module is connected to the first of previous (i.e. kth -1) logic gates module
The output port of OR circuit, wherein k > 1；The output port of second OR circuit of k-th of logic gates module is connected to
Second input port of kth grade inverting delay cells, i.e. the second input port of kth grade inverting delay cells are received k-th and are patrolled
Collect the output signal b of gate circuit modulek, wherein k=1,2 ... n/2, n are even number.
The input clock signal FIN of any duty ratio (x%) is input in digital duty-cycle correction circuit system, is inputted
The period of clock signal FIN is T；Using the narrow-pulse generation circuit by the input clock signal FIN of any duty ratio (x%)
Be converted into narrow pulse clock signal a and be input to half clock cycle delay circuit and；Half clock cycle delay circuit is by burst pulse
Clock signal a postpones the narrow pulse clock signal b after 1.5 input clock signal cycle Ts are postponed；Burst pulse before delay
Narrow pulse clock signal b after clock signal a, delay obtains same with input clock signal FIN after triggering reset latch
The output clock signal FOUT with 50% duty ratio of frequency.
Wherein, the data latches (LATCH) are the input that data port (D) is connected in high level, and low level holding is worked as
Preceding output；Original state after reset is positive output end mouth Q=0, anti-phase output port QN=1, data port (D) connection
Power vd D.Start to work after circuit reset, when it is preceding to the accumulated delay amount of delay cell be less than input clock signal cycle T when,
Corresponding AND gate circuit output is 0, and data latches are in the original state after resetting, and the output valve of anti-phase output port QN is
1, the second input port (IN1) in two input gates is selected, two input the second OR circuit of gates and rear class
Output is 1, and corresponding inverting delay cells are normally opened.When it is preceding to the accumulated delay amount of delay cell be equal to T when, i-stage
Between the obtained forward direction output signal ai of the output port of forward delay unit and second pulse of narrow pulse clock signal a
Still there are three types of possible for relative positional relationship:
Second pulse of the first situation, narrow pulse clock signal a is just overlapped with some forward direction output signal ai, electricity
Road works normally；
Second situation, second pulse of narrow pulse clock signal a and forward direction output signal aiAnd ai+1There is part weight
It closes, wherein i is odd number, then aiAnd ai+1Corresponding to generate pulse with Men Jiehui, the two pulses can enter the same logic gate electricity
The first OR circuit (OR1) of road module, to merge into one with narrow pulse clock signal a with wide pulse signal, and ai+1
The pulse signal meeting trigger data latch generated with operation is made with a, data latches adopt the level of its data port (D)
QN=0 is exported after VDD, two input gate conductings first input port (IN0), the second OR circuit (OR2) is another at this time
Input is 0, so the pulse signal of the first OR circuit (OR1) output is by two input gates and the second OR circuit
(OR2) enter revertive delay chain afterwards, circuit works normally；
The third situation, second pulse of narrow pulse clock signal a and forward direction output signal ajAnd aj+1There is part weight
It closes, wherein j is even number, then ajAnd aj+1Corresponding AND gate circuit can all generate pulse, but the two pulses enter different logics
First OR circuit of gate circuit module, and the two pulses will not merge, at this time ajXiang Yuyun is with narrow pulse clock signal a
It calculates the pulse signal generated and adopts the QN=0 for making data latches after VDD, which can pass through two input gates and reach
Second OR circuit (OR2), aj+1It is done with a and mutually also enters into second OR circuit (OR2) with the pulse of operation generation, two
Pulse the second OR circuit (OR2) merge into one with narrow pulse clock signal a with wide pulse and enter revertive delay chain,
Circuit works normally, and will not generate burr.
Implement the embodiment of the present invention, will have the following beneficial effects:
The present invention is based on half clock cycle delay chains to propose a kind of carrot-free 50% duty-cycle correction circuit, when by half
Data latches (LATCH), gate (MUX) and the second OR circuit (OR2) in clock cycle delay chain, with small area
The risk that circuit output burr is eliminated with power consumption cost increases the robustness of circuit system.
The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to the foregoing embodiments
Invention is explained in detail, those skilled in the art should understand that: it still can be to aforementioned each implementation
Technical solution documented by example is modified or equivalent replacement of some of the technical features；And these modification or
Replacement, can't be such that the essence of corresponding technical solution departs from the spirit and scope of the technical scheme of various embodiments of the present invention.
Claims (6)
1. a kind of number duty-cycle correction circuit system, which is characterized in that postpone including narrow-pulse generation circuit, half clock cycle
Circuit, triggering reset latch；
The input port of the narrow-pulse generation circuit receives input clock signal, the output port of the narrow-pulse generation circuit
It is respectively connected to the input port of the half clock cycle delay circuit and the port S of the triggering reset latch；Described half
The output port of clock cycle delay circuit is connected to the port R of the triggering reset latch；The triggering reset latch
Output port obtain output clock signal；
The half clock cycle delay circuit includes forward delay chain, revertive delay chain, logic gate array；The forward delay chain
It is connected to the logic gate array, the logic gate array is connected to the revertive delay chain；
The forward delay chain includes cascade n forward delay unit, and wherein n is the even number more than or equal to 2；It is described reversely to prolong
Slow chain includes cascade n/2 inverting delay cells；The logic gate array includes n/2 parallel logic gates module,
Each logic gates module is correspondingly connected to 2 forward delay units and 1 inverting delay cells.
2. number duty-cycle correction circuit system according to claim 1, which is characterized in that
Every grade of forward delay unit has 2 input ports and 1 output port, and 2 input terminals are forward delay unit
First input port and forward delay unit the second input port, the first input port of every grade of forward delay unit is all
It is connected to power supply, the second input port of the 1st grade of forward delay unit is connected to the output port of the narrow-pulse generation circuit,
The output port of previous stage forward delay unit is connected to the second input port of next stage forward delay unit；Before i-stage to
The output port of delay cell obtain before to output signal ai, wherein i=1,2 ... n.
3. number duty-cycle correction circuit system according to claim 2, which is characterized in that
Every grade of inverting delay cells have 2 input ports and 1 output port, and 2 input terminals are inverting delay cells
First input port and inverting delay cells the second input port, the first input port of every grade of inverting delay cells is all
It is connected to power supply, the output port of previous stage inverting delay cells is connected to the second input terminal of next stage inverting delay cells
Mouthful, the output port of afterbody inverting delay cells is connected to the port R of the triggering reset latch.
4. number duty-cycle correction circuit system according to claim 3, which is characterized in that
The logic gates module includes the first AND gate circuit, the second AND gate circuit, the first OR circuit；Described first and door
Circuit, the second AND gate circuit all have 2 input ports and 1 output port；The first input end of first AND gate circuit
Mouthful, the first input port of second AND gate circuit be all connected to the output port of the narrow-pulse generation circuit；It patrols for k-th
The second input port for collecting the first AND gate circuit in gate circuit module is connected to the output of the (n+1)th -2k grades of forward delay unit
Second input port of port, second AND gate circuit is connected to the output port of the n-th+2-2k grades of forward delay unit,
Middle k=1,2 ... n/2；First OR circuit has 2 input ports and 1 output port；First OR circuit
First input port connect the output port of the first AND gate circuit, the second input port connection the of first OR circuit
The output port of two AND gate circuits.
5. number duty-cycle correction circuit system according to claim 4, which is characterized in that
The logic gates module further includes the second OR circuit, data latches, two input gates；Described second or door
Circuit has 2 input ports and 1 output port；The output port of first OR circuit is connected to the two inputs choosing
The first input port of logical device；
The clock port of the data latches is connected to the output end of second AND gate circuit, the number of the data latches
Power supply is connected to according to port；The anti-phase output port of the data latches is connected to the selection signal of the two inputs gate
Input port；Second input port of the two inputs gate is connected to power supply, the output port of the two inputs gate
It is connected to the first input port of second OR circuit；
Second input port of the second OR circuit of the 1st logic gates module is grounded；K-th logic gates module
Second input port of the second OR circuit is connected to the output end of first OR circuit of -1 logic gates module of kth
Mouthful, wherein k > 1；The output port of second OR circuit of k-th of logic gates module is connected to kth grade revertive delay list
Second input port of member, i.e. the second input port of kth grade inverting delay cells receive the defeated of k-th of logic gates module
Signal b outk, wherein k=1,2 ... n/2.
6. number duty-cycle correction circuit system according to claim 1-5, which is characterized in that
The forward delay unit and the inverting delay cells are all the delay being made of 1 AND gate circuit and two-stage buffer
Unit.
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| CN113258923A (en) * | 2020-02-07 | 2021-08-13 | 瑞昱半导体股份有限公司 | Duty cycle corrector |
| WO2023071007A1 (en) * | 2021-10-29 | 2023-05-04 | 上海亿家芯集成电路设计有限公司 | Pulse width clock topology structure circuit |
| CN116683896A (en) * | 2022-12-27 | 2023-09-01 | 海光集成电路设计(北京)有限公司 | Duty cycle adjustable circuit, chip and electronic equipment |
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| CN116683896B (en) * | 2022-12-27 | 2024-04-02 | 海光集成电路设计(北京)有限公司 | Duty cycle adjustable circuit, chip and electronic equipment |
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| CN110492872B (en) | 2024-04-05 |
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