CN113258923B - Work cycle corrector - Google Patents
Work cycle corrector Download PDFInfo
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- CN113258923B CN113258923B CN202010082549.5A CN202010082549A CN113258923B CN 113258923 B CN113258923 B CN 113258923B CN 202010082549 A CN202010082549 A CN 202010082549A CN 113258923 B CN113258923 B CN 113258923B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
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Abstract
The invention discloses a work cycle corrector, which comprises a buffer circuit, an upper cascade circuit and a lower cascade circuit. The buffer circuit includes: the first buffer circuit is used for outputting a second output signal to a second output end according to the first input signal; the second buffer circuit is used for outputting a first output signal to the first output end according to a second input signal, wherein the second input signal is an inverted signal of the first input signal; and a latch circuit coupled between the first output terminal and the second output terminal. The upper cascade circuit is coupled between the high voltage terminal and the buffer circuit for transmitting current to the first output terminal and the second output terminal according to each of the first input signal and the second input signal. The lower cascode circuit is coupled between the buffer circuit and the low-potential terminal, and is configured to draw a current flowing through the first output terminal and the second output terminal according to each of the first and second input signals.
Description
Technical Field
The present invention relates to signal correctors, and more particularly to a corrector for a duty cycle of a signal.
Background
Fig. 1 shows a conventional AC-coupled self-biased inverter buffer (AC coupling self-bias inverter buffer with latch circuit) 100 with a latch circuit, comprising a first inverter buffer 110, a second inverter buffer 120 and a latch circuit 130. The first inverter buffer 110 is composed of a first capacitor 112, a first inverter 114 and a first resistor 116; the second inverter buffer 120 is composed of a second capacitor 122, a second inverter 124 and a second resistor 126; the latch circuit 130 is composed of an inverter 132 and an inverter 134. As shown in fig. 1, the first capacitor 112 and the second capacitor 122 are used for blocking the dc component; the first inverter 114 outputs an output signal clkon according to the input signal clkip; the second inverter 124 outputs an output signal clkop according to the input signal clkin; the first resistor 116 controls the dc bias voltage of the input terminal of the first inverter 114 according to the output signal clkon of the first inverter 114; the second resistor 126 controls the dc bias voltage of the input terminal of the second inverter 124 according to the output signal clkop of the second inverter 124; the latch circuit 130 may help to achieve a rail-to-rail (rail-to-rail) output, as well as to facilitate a close duty cycle of the two output signals clkon, clkop.
Referring to fig. 1 and 2a, when the duty cycle of the input signal clkip of the first inverter 114 is equal to 50%, the duty cycle of the output signal clkon of the first inverter 114 is also equal to 50%, so that the first resistor 116 biases the dc voltage at the input terminal of the first inverter 114 to V according to the output signal clkon DD 2, wherein V DD Which is the supply voltage for the buffer 100. Referring to fig. 1 and 2b, when the duty cycle of the input signal clkip of the first inverter 114 is less than 50%, the duty cycle of the output signal clkon of the first inverter 114 is greater than 50%, so that the first resistor 116 makes the dc bias voltage of the input terminal of the first inverter 114 greater than V according to the output signal clkon DD 2; in this case, the first inverter 114 pulls down the output signal clkon through the NMOS transistor more than the output signal clkon through the PMOS transistor Guan Lagao, so that the slope of the falling edge of the output signal clkon is greater than the slope of the rising edge, which makes the duty cycle of the output signal clkon approach 50%. Referring to fig. 1 and 2c, when the duty cycle of the input signal clkip of the first inverter is greater than 50%, the duty cycle of the output signal clkon of the first inverter 114 is less than 50%, so that the first resistor 116 makes the dc bias voltage of the input terminal of the first inverter 114 smaller than V according to the output signal clkon DD 2; in this case, the first inverter 114 may pull down the output signal clkon through the NMOS transistor less than the PMOS transistor Guan Lagao clkon, so that the rising edge of the output signal clkon may have a slope greater than the falling edge, which may approach the duty cycle of the output signal clkon to 50%. The output signal clkop also has similar characteristics. As described above, the buffer 100 can correct the duty cycle to approach the duty cycle of the output signals clkon and clkop to 50%. It is noted that the waveforms of the two output signals clkon, clkop of fig. 2 a-2 c are only schematic, and that the actual waveforms are typically not perfect square waves.
However, the buffer 100 of fig. 1 has the following problems: when the driving capability of the latch circuit 130 is smaller than that of the first inverter buffer 110 and the second inverter buffer 120, the duty cycle correction capability of the buffer 100 is lowered; when the driving capability of the latch circuit 130 is much higher than that of the first inverter buffer 110 and the second inverter buffer 120, this results in the latch-up (latch-up) of the output signal clkop/clkon, i.e., the output signal clkop/clkon is constant at 0V or 1V. In view of the above, there is a need in the art for a solution with good duty cycle correction capabilities while avoiding the lock-up problem.
Disclosure of Invention
It is an object of the present invention to disclose a duty cycle corrector to improve the prior art.
Embodiments of duty cycle corrector of the present invention include a buffer circuit, an upper cascode circuit, and a lower cascode circuit. The buffer circuit is used for receiving a first input signal and a second input signal from a first input end and a second input end respectively, outputting a second output signal to a second output end according to the first input signal, and outputting a first output signal to a first output end according to the second input signal, wherein the second input signal is an inverted signal of the first input signal, and the second output signal is an inverted signal of the first output signal. The upper cascade circuit is coupled between the high voltage terminal and the buffer circuit, and comprises: the first upper cascade switch circuit is coupled between the high potential end and the buffer circuit and is used for transmitting current to the second output end and the first output end according to the first input signal when being conducted; and a second upper cascade switch circuit coupled between the high potential end and the buffer circuit and connected in parallel with the first upper cascade switch circuit, wherein the second upper cascade switch circuit is used for transmitting current to the first output end and the second output end according to the second input signal when being conducted. The lower cascode circuit is coupled between the buffer circuit and a low potential terminal, and comprises: the first lower cascade switch circuit is coupled between the buffer circuit and the low potential end, and is used for drawing current flowing through the second output end and the first output end according to the first input signal when the first lower cascade switch circuit is conducted, wherein the conduction condition of the first lower cascade switch circuit is different from that of the first upper cascade switch circuit; and a second lower cascade switch circuit coupled between the buffer circuit and the low potential end and connected in parallel with the first lower cascade switch circuit, wherein the second lower cascade switch circuit is used for drawing current flowing through the first output end and the second output end according to the second input signal when being conducted, and the conduction condition of the second lower cascade switch circuit is different from that of the second upper cascade switch circuit.
Another embodiment of the duty cycle corrector of the present invention comprises a buffer circuit, an upper cascode circuit and a lower cascode circuit. The buffer circuit includes: the first buffer circuit is used for outputting a second output signal to a second output end according to the first input signal; the second buffer circuit is used for outputting a first output signal to the first output end according to a second input signal, wherein the second input signal is an inverted signal of the first input signal; and a latch circuit coupled between the first output terminal and the second output terminal. The upper cascade circuit is coupled between the high potential end and the buffer circuit, and is used for transmitting current to the second output end and the first output end according to the first input signal and transmitting current to the first output end and the second output end according to the second input signal. The lower cascade circuit is coupled between the buffer circuit and a low potential end and used for drawing current flowing through the second output end and the first output end according to the first input signal and drawing current flowing through the first output end and the second output end according to the second input signal, wherein the conduction condition of the lower cascade circuit is different from that of the upper cascade circuit.
The features, implementation and effects of the present invention will now be described in detail with reference to preferred embodiments of the invention as follows.
Drawings
FIG. 1 shows a conventional AC-coupled self-biased inverter buffer with a latch circuit;
FIG. 2a shows waveforms of the output signal clkon when the duty cycle of the input signal clkip of FIG. 1 is 50%;
FIG. 2b shows waveforms of the output signal clkon when the duty cycle of the input signal clkip of FIG. 1 is less than 50%;
FIG. 2c shows waveforms of the output signal clkon when the duty cycle of the input signal clkip of FIG. 1 is greater than 50%;
FIG. 3a shows an embodiment of the duty cycle corrector of the present invention;
FIG. 3b shows the duty cycle correction effect of the output signal clkon/clkop of FIG. 3a compared to the input signal clkip/clkin;
FIG. 4 shows one embodiment of the buffer circuit of FIG. 3 a;
FIG. 5 shows one embodiment of the first upper cascode switch circuit, the second upper cascode switch circuit, the first lower cascode switch circuit, and the second lower cascode switch circuit of FIG. 4; and
FIG. 6 shows another embodiment of the first upper cascode switch circuit, the second upper cascode switch circuit, the first lower cascode switch circuit, and the second lower cascode switch circuit of FIG. 4.
Detailed Description
The present invention discloses a duty cycle corrector having good duty cycle correction capability while avoiding latch-up (latch-up) problems.
Fig. 3a shows an embodiment of the duty cycle corrector of the present invention. The duty cycle corrector 300 of fig. 3a comprises a buffer circuit 310, an upper cascode circuit 320 and a lower cascode circuit 330. The buffer circuit 310 is configured to receive a first input signal clkip (e.g., a pulse signal; or a signal with a duty cycle of 50%) and a second input signal clkin from a first input terminal (in 1) and a second input terminal (in 2), respectively, and output a second output signal clkon to a second output terminal (out 2) according to the first input signal clkip and output a first output signal clkop to a first output terminal (out 1) according to the second input signal clkin. The second input signal clkin is an inverted signal of the first input signal clkip, or the two input signals form a differential input signal; the second output signal clkon is an inverted signal of the first output signal clkop, or the two output signals constitute a differential output signal.
Please refer to fig. 3a. The upper cascode circuit 320 is coupled to the high voltage terminal V DD Between the power supply and the buffer circuit 310, for example, a first upper cascode switch circuit 322 and a second upper cascode switch circuit 324 are included, and each of the two switch circuits 322, 324 is configured to transmit current to the first and second output terminals to improve the duty cycle of the two output signals clkop, clkon. The lower cascode circuit 330 is coupled to the buffer circuit 310 and the low voltage terminal V SS (e.g., ground), including a first lower cascode switch circuit 332 and a second lower cascode switch circuitThe switching circuit 334, each of the two switching circuits 332, 334 is configured to draw a current through the first and second output terminals to improve the duty cycle of the two output signals clkop, clkon. In this embodiment, the absolute value of the difference between the duty cycle of the first input signal clkip and 50% is larger than the absolute value of the difference between the duty cycle of the second output signal clkon and 50%, as shown in fig. 3b.
Please refer to fig. 3b. The first upper cascode switch circuit 322 is coupled to the high voltage terminal V DD And the buffer circuit 310, for conducting or not conducting according to the first input signal clkip, so as to transmit the current I along the original current path when conducting U11 To the second output terminal and along an additional current path to transmit a current I U12 To the first output terminal. The second upper cascode switch circuit 324 is coupled to the high voltage terminal V DD In parallel with the buffer circuit 310 and the first upper cascode switch circuit 322; the second upper cascode switch circuit 324 is configured to be conductive or non-conductive according to the second input signal clkin, so as to transmit the current I along the original current path when being conductive U21 To the first output terminal and along an additional current path to transmit a current I U22 To the second output. The lower cascode circuit 330 is coupled to the buffer circuit 310 and the low voltage terminal V SS (e.g., ground), includes a first lower cascode switch circuit 332 and a second lower cascode switch circuit 334. The first lower cascode switch circuit 332 is coupled to the buffer circuit 310 and the low voltage terminal V SS For conducting or non-conducting according to the first input signal clkip, so as to receive the current I flowing through the second output terminal from the original current path when conducting D11 And receiving a current I flowing through the first output terminal from an additional current path D12 Wherein the conduction condition of the first lower cascode switch circuit 332 is different from the conduction condition of the first upper cascode switch circuit 322. The second lower cascode switch circuit 334 is coupled to the buffer circuit 310 and the low voltage terminal V SS And is connected in parallel with the first lower cascode switch circuit 332; the second lower cascode switch circuit 334 is configured to be conductive or non-conductive according to the second input signal clkin, so as to receive the current flowing through the first current path when conductiveCurrent I at an output terminal D21 And receiving a current I flowing through the second output terminal from an additional current path D22 Wherein the conduction condition of the second lower cascode switch circuit 334 is different from the conduction condition of the second upper cascode switch circuit 324.
Fig. 4 shows an embodiment of the buffer circuit 310 of fig. 3a. The buffer circuit 310 of fig. 4 is an AC-coupled self-biased inverter buffer (AC coupling self-bias inverter buffer with latch circuit) with a latch circuit, and includes a first buffer circuit 410, a second buffer circuit 420 and a latch circuit 430. The first buffer circuit 410 is coupled between the first upper cascode switch circuit 322 and the first lower cascode switch circuit 332, and is configured to receive the first input signal clkip from the first input terminal to output the second output signal clkon to the second output terminal. The second buffer circuit 420 is coupled between the second upper cascode switch circuit 324 and the second lower cascode switch circuit 334, and is configured to receive the second input signal clkin from the second input terminal to output the first output signal clkop to the first output terminal. The latch circuit 430 is coupled between the first output terminal and the second output terminal, and can help to achieve the rail-to-rail output, and also help to approach the duty cycle of the two output signals clkon and clkop.
Please refer to fig. 4. The first buffer circuit 410 includes a first capacitor C1; the first inverter is composed of transistors MI1 and MI 2; and a first impedance circuit R1 (e.g., a resistor). The first capacitor C1 is coupled between the first input terminal and the first inverter; the input end and the output end of the first inverter are respectively coupled with the first capacitor C1 and the second output end; the first impedance circuit R1 is coupled between the input terminal and the output terminal of the first inverter. The second buffer circuit 420 includes: a second capacitor C2; the second inverter is composed of transistors MI3 and MI 4; and a second impedance circuit R2 (e.g., a resistor). The second capacitor C2 is coupled between the second input terminal and the second inverter; the input end and the output end of the second inverter are respectively coupled with the second capacitor C2 and the first output end; the second impedance circuit R2 is coupled between the input terminal and the output terminal of the second inverter. The latch circuit 430 is coupled to the high voltage terminal V DD And the low potential end V SS The two inverters are used for generating inversion signals clkop and clkop according to the output signals clkon and clkop respectively.
Fig. 5 shows one embodiment of the first upper cascode switch circuit 322, the second upper cascode switch circuit 324, the first lower cascode switch circuit 332, and the second lower cascode switch circuit 334 of fig. 4. As shown in fig. 5, the first upper cascode switch circuit 322 includes: a first transistor M1 coupled to the high voltage terminal V DD And the first buffer circuit 410 for transmitting the current I according to the first input signal clkip when conducting U11 To the second output; and a second transistor M2 coupled to the high potential terminal V DD And the second buffer circuit 420 for transmitting a current I according to the first input signal clkip when conducting U12 To the first output terminal. The second upper cascode switch circuit 324 includes: a third transistor M3 coupled to the high voltage terminal V DD And the second buffer circuit 420 for transmitting a current I according to the second input signal clkin when conducting U21 To the first output; and a fourth transistor M4 coupled to the high voltage terminal V DD And the first buffer circuit 410 for transmitting the current I according to the second input signal clkin when conducting U22 To the second output. The first lower cascode switch circuit 332 includes: a fifth transistor M5 coupled to the first buffer circuit 410 and the low voltage terminal V SS For receiving the current I flowing through the second output terminal according to the first input signal clkip when conducting D11 The method comprises the steps of carrying out a first treatment on the surface of the And a sixth transistor M6 coupled to the first buffer circuit 410 and the low voltage terminal V SS For receiving the current I flowing through the first output terminal according to the first input signal clkip when conducting D12 . The second lower cascode switch circuit 334 includes: a seventh transistor M7 coupled to the second buffer circuit 420 and the low voltage terminal V SS For receiving the current I flowing through the first output terminal according to the second input signal clkin when conducting D21 The method comprises the steps of carrying out a first treatment on the surface of the And an eighth transistor M8 coupled to the second buffer circuit 420 and the low voltage terminal V SS For conducting betweenReceiving a current I flowing through the second output terminal according to the second input signal clkin D22 . In this embodiment, each of the transistors M1 to M4 is a first type transistor (e.g., PMOS transistor); each of the transistors M5 to M8 is a second type transistor (e.g., NMOS transistor), and the conduction condition of the first type transistor is different from the conduction condition of the second type transistor.
Fig. 6 shows another embodiment of the first upper cascode switch circuit 322, the second upper cascode switch circuit 324, the first lower cascode switch circuit 332, and the second lower cascode switch circuit 334 of fig. 4. The first upper cascode switch circuit 322 includes: a first transistor M1 coupled to the high voltage terminal V DD And the first buffer circuit 410 for respectively transmitting the current I according to the first input signal clkip when conducting U11 And I U12 To the second output terminal and the first output terminal. The second upper cascode switch circuit 324 includes: a second transistor M2 coupled to the high voltage terminal V DD And the second buffer circuit 420 for respectively transmitting the current I according to the second input signal clkin when conducting U21 And I U22 To the first output terminal and the second output terminal. The first lower cascode switch circuit 332 includes: a third transistor M3 coupled to the first buffer circuit 410 and the low voltage terminal V SS The first input signal clkip is used for respectively drawing the current I flowing through the second output end and the first output end when being conducted D11 And I D12 . The second lower cascode switch circuit 334 includes: a fourth transistor M4 coupled to the second buffer circuit 420 and the low voltage terminal V SS When in conduction, the first and second output terminals respectively draw current I flowing through the first and second output terminals according to the second input signal clkin D21 And I D22 . In this embodiment, each of the transistors M1 to M2 is a first type transistor (e.g., PMOS transistor), and each of the transistors M3 to M4 is a second type transistor (NMOS transistor), and the conduction condition of the first type transistor is different from the conduction condition of the second type transistor. It should be noted that in the present embodiment, each of the transistors M1-M4 may be selectively formed by a plurality of transistors connected in parallel, the transistorsThe gates of the body tubes are connected together, the drains are connected together, and the sources are connected together.
Referring to fig. 4-6, the configuration of the upper cascode circuit 320 enables each of the two output terminals (or the first and second buffer circuits 410, 420) and the high voltage terminal V DD The current path therebetween becomes longer, and the lower cascode circuit 330 is arranged such that each of the two output terminals (or the first and second buffer circuits 410, 420) and the low potential terminal V SS The current path therebetween is lengthened, so as to ensure that the driving capability of the first buffer circuit 410 and the second buffer circuit 420 is sufficiently strong compared to the driving capability of the latch circuit 430, and the equivalent aspect ratio of each transistor in the upper cascode circuit 320, the lower cascode circuit 330, the first buffer circuit 410 and the second buffer circuit 420 is selectively adjusted (e.g., increased) by a multi-finger (multi-finger) layout design and/or by a multiplicative (multi) layout design (i.e., a plurality of transistors with small aspect ratio are connected in parallel to form a transistor with large aspect ratio), thereby ensuring that the influence of the upper cascode circuit 320 and the lower cascode circuit 330 on the driving capability of the first buffer circuit 410 and the second buffer circuit 420 is negligible or tolerable. Since each of the multi-fingered layout design and the multiplicative layout design is a common knowledge in the art, details thereof are omitted herein. It is noted that multi-fingered layout design and/or multiplicative (multiplier) layout design may also be selectively used for the layout design of the transistors of latch circuit 430 depending on implementation requirements.
It should be noted that, where possible, one of ordinary skill in the art may selectively implement some or all of the features of any one of the embodiments described above, or may selectively implement a combination of some or all of the features of any of the embodiments described above, thereby increasing the flexibility in implementing the invention.
In summary, the duty cycle corrector of the present disclosure improves the duty cycle of the output signal and avoids the lock-up problem through the configuration of the cascade circuit.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art may make variations to the technical features of the present invention according to the explicit or implicit disclosure of the present invention, and all variations may belong to the scope of the present invention, that is, the scope of the present invention should be considered as being defined in the claims.
Symbol description
100 A.C. coupled self-biased inverter buffer with latch circuit
110 first inverter buffer
112 first capacitor
114 first inverter
116 first resistor
120 second inverter buffer
122 a second capacitor
124 second inverter
126 second resistor
130 latch circuit
132 inverter
134 inverter
clkip input signal
clkon output signal
clkin input signal
clkop output signal
300 duty cycle corrector
310 buffer circuit
320 upper cascading circuit
322 first upper cascade switch circuit
324 second upper cascade switch circuit
330 lower cascade circuit
332 first lower cascade switch circuit
334 a second lower cascade switching circuit
in1, first input terminal
in2, the second input end
out1 first output terminal
out2 second output terminal
clk first input signal
clkin, second input signal
clkop first output signal
clkon-second output Signal
V DD High potential end
V SS Low potential end
I U11 ～I U22 Current transmitted by upper cascade circuit
I D11 ～I D22 Current received by the lower cascode circuit
410 a first buffer circuit
420 a second buffer circuit
430 latch circuit
C1 first capacitor
C2 second capacitor
MI 1-MI 2 transistors forming an inverter in the first buffer circuit
MI 3-MI 4 transistors forming an inverter in the second buffer circuit
R1:first impedance circuit
R2:second impedance circuit
Transistors of M1-M8 cascade circuit
Claims (10)
1. A duty cycle corrector comprising:
the buffer circuit is used for respectively receiving a first input signal and a second input signal from a first input end and a second input end, outputting a second output signal to a second output end according to the first input signal and outputting a first output signal to a first output end according to the second input signal, wherein the second input signal is an inverted signal of the first input signal, and the second output signal is an inverted signal of the first output signal;
an upper cascode circuit coupled between the high voltage terminal and the buffer circuit, comprising:
the first upper cascade switch circuit is coupled between the high potential end and the buffer circuit, and is used for transmitting current to the second output end and the first output end according to the first input signal when being conducted; and
the second upper cascade switch circuit is coupled between the high potential end and the buffer circuit and connected in parallel with the first upper cascade switch circuit, and is used for transmitting current to the first output end and the second output end according to the second input signal when being conducted; and
a lower cascode circuit coupled between the buffer circuit and a low potential terminal, comprising:
the first lower cascade switch circuit is coupled between the buffer circuit and the low potential end, and is used for drawing current flowing through the second output end and the first output end according to the first input signal when the first lower cascade switch circuit is conducted, wherein the conducting condition of the first lower cascade switch circuit is different from that of the first upper cascade switch circuit; and
the second lower cascade switch circuit is coupled between the buffer circuit and the low potential end and connected in parallel with the first lower cascade switch circuit, and is used for drawing current flowing through the first output end and the second output end according to the second input signal when the second lower cascade switch circuit is conducted, wherein the conduction condition of the second lower cascade switch circuit is different from that of the second upper cascade switch circuit.
2. The duty cycle corrector of claim 1, wherein an absolute value of a difference between a duty cycle of the first input signal and 50% is greater than an absolute value of a difference between a duty cycle of the second output signal and 50%.
3. The duty cycle corrector of claim 1, wherein the buffer circuit comprises:
the first buffer circuit is coupled between the first upper cascade switch circuit and the first lower cascade switch circuit and is used for receiving the first input signal from the first input end so as to output the second output signal to the second output end;
the second buffer circuit is coupled between the second upper cascade switch circuit and the second lower cascade switch circuit and is used for receiving the second input signal from the second input end so as to output the first output signal to the first output end; and
the latch circuit is coupled between the first output end and the second output end.
4. The duty cycle corrector of claim 3, wherein,
the first buffer circuit includes:
a first capacitor coupled between the first input terminal and the first inverter;
the input end and the output end of the first inverter are respectively coupled with the first capacitor and the second output end; and
the first impedance circuit is coupled between the input end and the output end of the first inverter; the second buffer circuit includes:
a second capacitor coupled between the second input terminal and the second inverter;
the input end and the output end of the second inverter are respectively coupled with the second capacitor and the first output end; and
the second impedance circuit is coupled between the input end and the output end of the second inverter; and
the latch circuit includes:
the input end and the output end of the third inverter are respectively coupled with the second output end and the first output end; and
and the input end and the output end of the fourth inverter are respectively coupled with the first output end and the second output end.
5. The duty cycle corrector of claim 3, wherein,
the first upper cascode switch circuit includes:
the first transistor is coupled between the high potential end and the first buffer circuit and used for transmitting current to the second output end according to the first input signal when the first transistor is conducted; and
the second transistor is coupled between the high potential end and the second buffer circuit and is used for transmitting current to the first output end according to the first input signal when the second transistor is conducted;
the second upper cascode switch circuit includes:
a third transistor coupled between the high-potential terminal and the second buffer circuit for transmitting a current to the first output terminal according to the second input signal when the third transistor is turned on; and
a fourth transistor coupled between the high-potential terminal and the first buffer circuit for transmitting a current to the second output terminal according to the second input signal when the fourth transistor is turned on;
the first lower cascode switch circuit includes:
a fifth transistor, coupled between the first buffer circuit and the low-potential terminal, for drawing a current flowing through the second output terminal according to the first input signal when the fifth transistor is turned on; and
a sixth transistor, coupled between the first buffer circuit and the low-potential terminal, for drawing a current flowing through the first output terminal according to the first input signal when the sixth transistor is turned on; and
the second lower cascode switch circuit includes:
a seventh transistor, coupled between the second buffer circuit and the low-potential terminal, for drawing a current flowing through the first output terminal according to the second input signal when the seventh transistor is turned on; and
the eighth transistor is coupled between the second buffer circuit and the low-potential terminal, and is configured to draw a current flowing through the second output terminal according to the second input signal when the eighth transistor is turned on.
6. The duty cycle corrector of claim 5, wherein each of the first, second, third and fourth transistors is a first type transistor, each of the fifth, sixth, seventh and eighth transistors is a second type transistor, and the conduction condition of the first type transistor is different from the conduction condition of the second type transistor.
7. The duty cycle corrector of claim 3, wherein,
the first upper cascode switch circuit includes:
a first transistor coupled between the high-potential terminal and the first buffer circuit for transmitting a current to the second output terminal and the first output terminal according to the first input signal when the first transistor is turned on; the second upper cascode switch circuit includes:
a second transistor coupled between the high-potential terminal and the second buffer circuit for transmitting a current to the first output terminal and the second output terminal according to the second input signal when the second transistor is turned on; the first lower cascode switch circuit includes:
a third transistor coupled between the first buffer circuit and the low-potential terminal for drawing a current flowing through the second output terminal and the first output terminal according to the first input signal when the third transistor is turned on; and
the second lower cascode switch circuit includes:
and the fourth transistor is coupled between the second buffer circuit and the low potential end and is used for drawing current flowing through the first output end and the second output end according to the second input signal when the fourth transistor is conducted.
8. The duty cycle corrector of claim 7, wherein each of the first transistor and the second transistor is a first type transistor, each of the third transistor and the fourth transistor is a second type transistor, and the conduction condition of the first type transistor is different from the conduction condition of the second type transistor.
9. A duty cycle corrector comprising:
a buffer circuit, comprising:
the first buffer circuit is used for outputting a second output signal to a second output end according to the first input signal;
the second buffer circuit is used for outputting a first output signal to a first output end according to a second input signal, wherein the second input signal is an inverted signal of the first input signal; and
a latch circuit coupled between the first output terminal and the second output terminal; the upper cascade circuit is coupled between the high potential end and the buffer circuit and is used for transmitting current to the second output end and the first output end according to the first input signal and transmitting current to the first output end and the second output end according to the second input signal; and
the lower cascade circuit is coupled between the buffer circuit and the low potential end, and is used for drawing current flowing through the second output end and the first output end according to the first input signal and drawing current flowing through the first output end and the second output end according to the second input signal, wherein the conduction condition of the lower cascade circuit is different from the conduction condition of the upper cascade circuit.
10. The duty cycle corrector of claim 9, wherein an absolute value of a difference between a duty cycle of the first input signal and 50% is greater than an absolute value of a difference between a duty cycle of the second output signal and 50%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010082549.5A CN113258923B (en) | 2020-02-07 | 2020-02-07 | Work cycle corrector |
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| CN202010082549.5A CN113258923B (en) | 2020-02-07 | 2020-02-07 | Work cycle corrector |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103262400A (en) * | 2010-08-18 | 2013-08-21 | 芬斯克斯有限公司 | Very high frequency switching cell-ased power converter |
| CN106464260A (en) * | 2014-04-21 | 2017-02-22 | 高通股份有限公司 | Circuit for generating accurate clock phase signals for a high-speed serializer/deserializer |
| CN110492872A (en) * | 2019-09-12 | 2019-11-22 | 珠海微度芯创科技有限责任公司 | Digital duty-cycle correction circuit system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5320979B2 (en) * | 2008-10-24 | 2013-10-23 | 富士通セミコンダクター株式会社 | Transmitter circuit |
| US9438208B2 (en) * | 2014-06-09 | 2016-09-06 | Qualcomm Incorporated | Wide-band duty cycle correction circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103262400A (en) * | 2010-08-18 | 2013-08-21 | 芬斯克斯有限公司 | Very high frequency switching cell-ased power converter |
| CN106464260A (en) * | 2014-04-21 | 2017-02-22 | 高通股份有限公司 | Circuit for generating accurate clock phase signals for a high-speed serializer/deserializer |
| CN110492872A (en) * | 2019-09-12 | 2019-11-22 | 珠海微度芯创科技有限责任公司 | Digital duty-cycle correction circuit system |
Non-Patent Citations (1)
| Title |
|---|
| 数字控制系统等效模拟校正调试研究;王晓丽;赵艳花;周阳;;制造业自动化(08);全文 * |
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| CN113258923A (en) | 2021-08-13 |
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