CN103929159A - Clock frequency doubling circuit with duty ratio capable of being adjusted automatically - Google Patents
Clock frequency doubling circuit with duty ratio capable of being adjusted automatically Download PDFInfo
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- CN103929159A CN103929159A CN201410191415.1A CN201410191415A CN103929159A CN 103929159 A CN103929159 A CN 103929159A CN 201410191415 A CN201410191415 A CN 201410191415A CN 103929159 A CN103929159 A CN 103929159A
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Abstract
The invention discloses a clock frequency doubling circuit with the duty ratio capable of being adjusted automatically, and belongs to the technical field of circuit design. The circuit comprises a programmable delay line, an exclusive-OR gate circuit body and a duty ratio feedback return circuit body composed of a duty ratio judging circuit body and an addition/subtraction circuit body. The programmable delay line is connected with the exclusive-OR gate circuit body and used for realizing delay time of a reference clock, and the precision of the delay time is determined by a minimum delay unit of the circuit. The duty ratio judging circuit body receives output signals of the exclusive-OR gate circuit body, compares duty ratios of clock signals with a preset value and outputs judging results signals. The addition/subtraction circuit body conducts addition/subtraction computation according to the judging result signals output by the duty ratio judging circuit body, the direction where the duty ratios in N duty ratio cycles deviate the preset value and the number of the duty ratios in the N duty ratio cycles are judged, therefore, feedback signals are transmitted to the programmable delay line, and therefore automatic duty ratio adjustment is realized.
Description
Technical field
The present invention relates to a kind of clock multiplier circuit, relate in particular to the automatic adjustable clock multiplier circuit of a kind of duty ratio for circuit design and Design for Programmable Logic.
Background technology
Clock multiplier circuit is widely used in the middle of various chip designs, and frequency doubling clock can be used as the work clock of digital circuit, also can be used as the time interval metrical pulse of some special chips etc.Along with constantly increasing of circuit work frequency, for guaranteeing the correctness of data communication sequential and the accuracy of time measurement, the duty ratio of frequency doubling clock circuit has been proposed to stricter requirement.
Conventionally the duty ratio that requires clock in general digital circuit is 50%, and in high-frequency clock frequency multiplier circuit, surrounding environment or device itself will be larger on the impact of frequency doubling clock waveform, and the consequence of bringing is also more serious.This just requires frequency multiplier circuit itself to have certain error correcting capability, and error correction procedure will be quick and precisely.
At present, the duty cycle adjustment in frequency doubling clock circuit adopts the method for manual adjustments potentiometer mostly, and real-time is poor, can not meet the requirement of current high-frequency clock frequency multiplier circuit development.
Summary of the invention
In view of this, the object of the present invention is to provide the automatic adjustable clock multiplier circuit of a kind of duty ratio, the precision of duty cycle adjustment is determined by programmable delay line minimum delay time.Duty ratio test circuit quantizes duty ratio, forms with programmable delay line control port the automatic adjustable function that feedback loop is realized duty ratio.Meanwhile, programmable delay line makes circuit more flexible, can design different algorithm structures according to actual conditions and improve duty cycle adjustment speed.
For achieving the above object, the invention provides following technical scheme:
The automatic adjustable clock multiplier circuit of duty ratio, comprises programmable delay line, NOR gate circuit and by duty ratio decision circuitry with the duty ratio feedback loop that forms of add/subtraction circuit; Programmable delay line is connected with NOR gate circuit, and for realizing the time of delay of reference clock, the precision of time of delay is determined by the minimum delay unit of circuit; Duty ratio decision circuitry receives the output signal of NOR gate circuit, the duty ratio of clock signal and preset value is compared, and export judging result signal; Add/subtraction circuit does according to the judging result signal of duty ratio decision circuitry output add/subtraction, the duty ratio of judging N duty ratio judgement cycle departs from direction and the number of preset value, thereby feedback signal is sent to programmable delay line, realizes the automatic adjusting of duty ratio.
Further, programmable delay line adopts digital delay structure or analogue delay structure, and the basic delay cell of digital delay structure is gate circuit, and the basic delay cell of analogue delay structure is RC delay circuit.
Further, according to side circuit, postpone scope programmable delay line and can use linear structure or loop configuration.
Further, described duty ratio decision circuitry comprises integrating circuit and comparator, and the integrating circuit output level in duty ratio decision circuitry is directly compared with predetermined level, during higher than preset value, exports 1, during lower than preset value, exports 0.
Beneficial effect of the present invention is: the present invention proposes the automatic adjustable clock multiplier circuit of a kind of duty ratio, can realize the automatically adjustable of frequency doubling clock duty ratio, flexible and changeable, it regulates minimum precision to depend on minimum delay unit, and the speed dependent of adjusting is in programmed algorithm structure.
Accompanying drawing explanation
In order to make object of the present invention, technical scheme and beneficial effect clearer, the invention provides following accompanying drawing and describe:
Fig. 1 is the automatic adjustable clock multiplier circuit structured flowchart of duty ratio;
Fig. 2 is frequency doubling clock circuit input/output signal schematic diagram;
Fig. 3 is the programmable delay line based on gate structure;
Fig. 4 is the programmable delay line based on RC circuit structure.
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are described in detail.
Fig. 1 is the automatic adjustable clock multiplier circuit structured flowchart of duty ratio, as shown in the figure:
This circuit comprises programmable delay line, NOR gate circuit and by duty ratio decision circuitry with the duty ratio feedback loop that forms of add/subtraction circuit; Programmable delay line is connected with NOR gate circuit, and for realizing the time of delay of reference clock, the precision of time of delay is determined by the minimum delay unit of circuit; Duty ratio decision circuitry receives the output signal of NOR gate circuit, the duty ratio of clock signal and preset value is compared, and export judging result signal; Add/subtraction circuit does according to the judging result signal of duty ratio decision circuitry output add/subtraction, the duty ratio of judging N duty ratio judgement cycle departs from direction and the number of preset value, thereby feedback signal is sent to programmable delay line, realizes the automatic adjusting of duty ratio.
Specifically:
Programmable delay line is used for realizing the time of delay of reference clock, and the precision of time of delay determines by the minimum delay unit of circuit, and concrete time of delay is by program control, and this design regulates more flexibly the time of delay of reference clock and accurately.
NOR gate circuit is realized two double frequency functions of circuit, and NOR gate circuit input is the reference clock of reference clock and process delay line.
The effect of duty ratio decision circuitry is that the duty ratio of clock signal and preset value (as 50%) are compared, and when being greater than preset value, input logic signal 1, and when being less than preset value, output logic signal 0.
The function of add/subtracter is to do according to the logical signal of the output of duty ratio decision circuitry add/subtraction, when being output as 1, do add operation and when being output as 0, do subtraction, can judge that the duty ratio in N duty ratio judgement cycle departs from direction and the number of preset value.
The frequency doubling clock node signal figure of reference clock, delayed clock and last output as shown in Figure 2, just can obtain the frequency doubling clock signal of different duty by the control lag clock delay time.
The structure of programmable delay line has digital delay structure and analogue delay structure two schemes, digital delay structure as shown in Figure 3, adopt gate circuit as basic delay cell, by program control, select which tapping switch closure to obtain the loop of varying number gate circuit, thereby obtain different time of delay.Analogue delay structure as shown in Figure 4, adopts RC delay circuit as basic delay cell.
Duty ratio decision circuitry can be realized by integrating circuit and comparator.By M frequency doubling clock, the duty ratio time signal in the cycle is converted to voltage signal to integrating circuit, voltage signal is by comparing with predeterminated voltage value, circuit output high level signal when being greater than predeterminated voltage, circuit output low level signal when being less than preset value voltage.Preset value calculates gained by the required duty ratio of circuit, clock level value and M value, and the general required duty ratio of digital circuit is generally 50%.It should be noted that the M value that duty ratio decision circuitry can identify is less, the frequency of adjusting is just higher, and the duty ratio of frequency doubling clock signal is just more stable.
Add/subtraction circuit is input to programmable delay line control end by the duty ratio real-time condition of frequency doubling clock signal, departs from situation be adjusted accordingly according to duty ratio.Programmable delay line regulates the mode can adopt convergence to regulate, and when duty ratio departs from actual conditions, first macro-control is finely tuned again, stops adjusting after regulating X clock cycle.
Finally explanation is, above preferred embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is described in detail by above preferred embodiment, but those skilled in the art are to be understood that, can to it, make various changes in the form and details, and not depart from the claims in the present invention book limited range.
Claims (4)
1. the automatic adjustable clock multiplier circuit of duty ratio, is characterized in that: comprise programmable delay line, NOR gate circuit and by duty ratio decision circuitry with the duty ratio feedback loop that forms of add/subtraction circuit; Programmable delay line is connected with NOR gate circuit, and for realizing the time of delay of reference clock, the precision of time of delay is determined by the minimum delay unit of circuit; Duty ratio decision circuitry receives the output signal of NOR gate circuit, the duty ratio of clock signal and preset value is compared, and export judging result signal; Add/subtraction circuit does according to the judging result signal of duty ratio decision circuitry output add/subtraction, the duty ratio of judging N duty ratio judgement cycle departs from direction and the number of preset value, thereby feedback signal is sent to programmable delay line, realizes the automatic adjusting of duty ratio.
2. the automatic adjustable clock multiplier circuit of a kind of duty ratio according to claim 1, it is characterized in that: programmable delay line adopts digital delay structure or analogue delay structure, the basic delay cell of digital delay structure is gate circuit, and the basic delay cell of analogue delay structure is RC delay circuit.
3. the automatic adjustable clock multiplier circuit of a kind of duty ratio according to claim 2, is characterized in that: according to side circuit, postpone scope programmable delay line and can use linear structure or loop configuration.
4. the automatic adjustable clock multiplier circuit of a kind of duty ratio according to claim 3, it is characterized in that: described duty ratio decision circuitry comprises integrating circuit and comparator, integrating circuit output level in duty ratio decision circuitry is directly compared with predetermined level, during higher than preset value, export 1, during lower than preset value, export 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410191415.1A CN103929159A (en) | 2014-05-08 | 2014-05-08 | Clock frequency doubling circuit with duty ratio capable of being adjusted automatically |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410191415.1A CN103929159A (en) | 2014-05-08 | 2014-05-08 | Clock frequency doubling circuit with duty ratio capable of being adjusted automatically |
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| CN103929159A true CN103929159A (en) | 2014-07-16 |
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| CN201410191415.1A Pending CN103929159A (en) | 2014-05-08 | 2014-05-08 | Clock frequency doubling circuit with duty ratio capable of being adjusted automatically |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106877845A (en) * | 2015-09-23 | 2017-06-20 | 万国半导体股份有限公司 | Compact Duty Modulator |
| CN110166028A (en) * | 2019-06-13 | 2019-08-23 | 珠海微度芯创科技有限责任公司 | Digital dock frequency multiplier circuit system, digital dock frequency-doubled signal generation method |
| CN110324037A (en) * | 2018-03-31 | 2019-10-11 | 华为技术有限公司 | A kind of frequency multiplier, digital PLL circuit and frequency-doubling method |
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| US5920216A (en) * | 1997-04-03 | 1999-07-06 | Advanced Micro Devices, Inc. | Method and system for generating digital clock signals of programmable frequency employing programmable delay lines |
| JP2002152018A (en) * | 2000-11-07 | 2002-05-24 | Toshiba Corp | Synchronization delay control circuit |
| CN102624360A (en) * | 2012-04-05 | 2012-08-01 | 四川和芯微电子股份有限公司 | Frequency multiplying circuit and system capable of automatically adjusting duty ratio of output signal |
| WO2013140255A1 (en) * | 2012-03-20 | 2013-09-26 | Smith & Nephew Plc | Controlling operation of a reduced pressure therapy system based on dynamic duty cycle threshold determination |
| CN203933571U (en) * | 2014-05-08 | 2014-11-05 | 重庆莲芯电子科技有限公司 | The automatic adjustable clock multiplier circuit of a kind of duty ratio |
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2014
- 2014-05-08 CN CN201410191415.1A patent/CN103929159A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5920216A (en) * | 1997-04-03 | 1999-07-06 | Advanced Micro Devices, Inc. | Method and system for generating digital clock signals of programmable frequency employing programmable delay lines |
| JP2002152018A (en) * | 2000-11-07 | 2002-05-24 | Toshiba Corp | Synchronization delay control circuit |
| WO2013140255A1 (en) * | 2012-03-20 | 2013-09-26 | Smith & Nephew Plc | Controlling operation of a reduced pressure therapy system based on dynamic duty cycle threshold determination |
| CN102624360A (en) * | 2012-04-05 | 2012-08-01 | 四川和芯微电子股份有限公司 | Frequency multiplying circuit and system capable of automatically adjusting duty ratio of output signal |
| CN203933571U (en) * | 2014-05-08 | 2014-11-05 | 重庆莲芯电子科技有限公司 | The automatic adjustable clock multiplier circuit of a kind of duty ratio |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106877845A (en) * | 2015-09-23 | 2017-06-20 | 万国半导体股份有限公司 | Compact Duty Modulator |
| CN106877845B (en) * | 2015-09-23 | 2020-04-07 | 万国半导体股份有限公司 | Compact duty modulator |
| CN110324037A (en) * | 2018-03-31 | 2019-10-11 | 华为技术有限公司 | A kind of frequency multiplier, digital PLL circuit and frequency-doubling method |
| CN110324037B (en) * | 2018-03-31 | 2021-08-20 | 华为技术有限公司 | Frequency multiplier, digital phase-locked loop circuit and frequency multiplication method |
| US11101808B2 (en) | 2018-03-31 | 2021-08-24 | Huawei Technologies Co., Ltd. | Frequency multiplier, digital phase-locked loop circuit, and frequency multiplication method |
| CN110166028A (en) * | 2019-06-13 | 2019-08-23 | 珠海微度芯创科技有限责任公司 | Digital dock frequency multiplier circuit system, digital dock frequency-doubled signal generation method |
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Application publication date: 20140716 |