JP2002152018A - Synchronization delay control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronization delay control circuit that copes with a low frequency clock with a comparatively small number of unit delay elements and obtains high synchronization accuracy with a high frequency clock. SOLUTION: A variable delay element (d) whose delay time is variable from a first stage to a prescribed number of stage is employed for unit delay elements of stages for a first delay line 31 and a second delay line 32 being components of the synchronization delay control circuit and a minimum delay element δwhose delay time is minimum is employed for the unit delay element at succeeding stages to the prescribed number of stage. A frequency detection circuit 33 and a controller 34 control the delay time of the variable delay element (d) depending on the clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a synchronous delay control circuit mounted on a clock synchronous semiconductor device for generating an internal clock synchronized with an external clock within a fixed clock frequency range of the external clock.

[0002]

2. Description of the Related Art Conventionally, SDR has been used as a semiconductor memory capable of high-speed data processing in a computer system.
A clock synchronous semiconductor memory such as an AM is known.
In order to realize a high data rate with this type of synchronous semiconductor memory, the delay of the internal clock with respect to the external clock cannot be ignored. Therefore, a synchronous mirror delay circuit that synchronizes an internal clock with an external clock within a predetermined clock frequency range is disclosed in, for example, the following documents.

A 2.5-ns Clock Access, 250-MHz, 256-Mb
SDRAM with Synchronous Mirror Delay (IEEE JOURNAL
OF SOLID-STATE CIRCUITS, VOL.31, NOVEMBER 1996, pp.16
56-1665) Digital Delay Locked Loop and Design Technique f
or High-Speed Synchronous Interface (IEICE TRANS.EL
(ECTRON, VOL.E79-C, NO.6, JUNE 1996, pp.798-807)

The synchronous mirror delay circuit is configured using a forward pulse delay line in which a plurality of unit delay elements are cascaded, and a backward pulse delay line in which a plurality of unit delay elements are cascade connected. Further, a delay monitor circuit is provided for obtaining a delay corresponding to a total delay time of a delay in a clock buffer receiving an external clock and a delay in a clock driver outputting an internal clock. Then, the output pulse of the delay monitor circuit is input to the first stage of the forward pulse delay line, and its propagation is stopped in synchronization with the external clock. In response to the output of the stop stage, the backward pulse delay line propagates the same propagation time as the forward pulse delay line, and supplies the output pulse to the clock driver.

When such a synchronous mirror delay circuit is used, the internal clock can be synchronized with the external clock with a two-cycle delay. That is, the delay time in the clock buffer is d1, and the delay time in the clock driver is d2.
In the delay monitor circuit, the clock received by the clock buffer is given a delay of d1 + d2 and given to the forward pulse delay line, and the propagation thereof is stopped in synchronization with the clock.
The propagation delay in this forward pulse delay line is tCK- (d1 + d2), where the clock cycle is tCK. Since the backward pulse delay line gives the same propagation delay as the forward pulse delay line, the total delay time from the clock buffer that receives the external clock to the clock driver output that outputs the internal clock is 2 (d1 + d2) + 2 @ tCK- ( d1 + d2)｝ = 2
tCK, and an internal clock synchronized with the external clock is obtained with a delay of two cycles.

[0006]

In such a synchronous delay control circuit, in order to enable synchronous control over a wide clock frequency range, particularly a low frequency range, the number of stages of the unit delay elements of the forward and backward pulse delay lines is required. It is necessary to increase. For example, when the delay time of a unit delay element is tUD and the number of stages is n, the maximum delay time in the forward and backward pulse delay lines is tUD × n. If tU
If D × n <tCK− (d1 + d2), the required delay amount is insufficient. In order to reduce the number of stages of the unit delay element and to cover a wide clock frequency, the delay time of the unit delay element may be increased.

However, when the number of stages of the unit delay elements is increased to cope with a low clock frequency, the area occupied by the forward and backward pulse delay lines becomes large, and the driver for driving these delay lines is increased due to an increase in capacitance. Also requires a large area. On the other hand, if the delay amount of the unit delay element is increased to cover a wide clock frequency while suppressing the increase in the area of the forward and backward pulse delay lines, the synchronization accuracy deteriorates, and high-precision synchronization can be obtained particularly with a high-frequency clock. Disappears.

The present invention has been made in view of the above circumstances, and provides a synchronous delay control which can cope with a low frequency clock with a relatively small number of unit delay elements and can obtain high synchronization accuracy with a high frequency clock. It is intended to provide a circuit.

[0009]

According to the present invention, a clock buffer for receiving an external clock, a clock driver for outputting an internal clock synchronized with the external clock, and a first pulse output from the clock buffer are provided. A delay monitor circuit for outputting a second pulse provided with a total delay time of the clock buffer and the clock driver; and a plurality of unit delay elements connected in cascade, and a second output from the delay monitor circuit is provided. A first delay line for outputting a third pulse given a predetermined propagation delay with respect to the second pulse at a timing synchronized with the external clock when the first pulse is input to the first stage, and a plurality of cascade-connected delay lines. A third delay pulse output from the first delay line with the same propagation delay as that of the first delay line. The second is supplied to the serial clock driver
Wherein the first and second delay lines are constituted by variable delay elements whose delay time is variable from the first stage to a predetermined number of stages, and the delay time is fixed after the predetermined number of stages. And a fixed delay element.

In the synchronous delay control circuit according to the present invention, the unit delay elements forming the first and second pulse delay lines forming the mirror delay circuit are replaced with a variable delay element having a variable delay time and a fixed delay time. It is configured by a combination with a fixed delay element. Thus, by controlling the delay time of the variable delay element according to the clock frequency, it is possible to cope with a low clock frequency with a small number of stages. Further, by using a fixed delay element, particularly a minimum delay element that obtains a minimum delay time as long as the manufacturing process allows, at the subsequent stage of the pulse delay line, highly accurate synchronization with a high-frequency clock can be achieved.

In the present invention, in order to control the variable delay elements of the first and second delay lines, a frequency detecting circuit for detecting a frequency of an external clock, and the variable delay circuit according to an output of the frequency detecting circuit. A controller for controlling a delay time of the element.

In this case, the frequency detecting circuit includes, for example, a pulse generator that generates a pulse signal having a constant pulse width in synchronization with an output clock of the clock buffer, a pulse signal output by the pulse generator, and an output of the clock buffer. And a phase comparator for comparing the phase of the clock.

In the present invention, the fixed delay elements constituting the first and second delay lines are constituted by, for example, clocked inverters to which a fixed power supply voltage is applied, and the variable delay elements are constituted by, for example, a variable power supply voltage. Clocked inverter. When such a variable delay element is used, the controller is controlled to be switched by the output of the frequency detection circuit, and transfers the fixed power supply voltage to the power supply terminal of the variable delay element, and lowers the level of the fixed power supply voltage. And a transfer path for transferring to the power supply terminal of the variable delay element.

The pulse generator constituting the frequency detecting circuit is, for example, a delay circuit for inverting and delaying the output clock of the clock buffer, and the output clock is obtained by the logic of the output of the delay circuit and the output clock of the clock buffer. A logic gate that generates a pulse signal at the edge of
A circuit element monitor circuit for monitoring element characteristics of the delay circuit and performing control for keeping the delay characteristic constant. This makes it possible to suppress variations in the pulse width of the pulse output due to variations in the process.

In the present invention, the fixed delay elements constituting the first and second delay lines are each constituted by, for example, a clocked inverter to which a fixed power supply voltage is applied, and the variable delay element has a variable resistance element in an input path. , And a clocked inverter to which a fixed power supply voltage is applied. When using such a variable delay element, the controller can be configured to control the resistance of the variable resistance element according to the output of the frequency detection circuit. Further, in this case, the frequency detection circuit includes a pulse generator that generates a pulse signal at the edge of the output clock of the clock buffer, and a current source that is controlled by the output of the pulse generator to change the potential according to the frequency of the external clock. An integrator that outputs a frequency detection signal to be controlled, and the controller can be configured to control the resistance of the variable resistance element based on the frequency detection signal obtained from the integrator.

Further, when the fixed delay element is constituted by a clocked inverter to which a fixed power supply voltage is applied, and the variable delay element is constituted by a clocked inverter to which a variable power supply voltage is applied, the frequency detection circuit is provided. ,
A pulse generator that generates a pulse signal at the edge of the output clock of the clock buffer; and an integrator that outputs a frequency detection signal in which the current source is controlled by the output of the pulse generator and the potential changes according to the frequency of the external clock. A differential amplifier to which a frequency detection signal obtained from the integrator and a variable power supply voltage output are input, and a current source controlled by an output of the differential amplifier to control the variable And an output circuit for outputting a power supply voltage.

In the present invention, preferably, a latch circuit for latching the output of the frequency detection circuit is provided between the output of the frequency detection circuit and the controller. This allows
The cause of the increase in jitter can be effectively reduced.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a synchronous delay control circuit according to an embodiment of the present invention. This synchronous delay control circuit is mounted on a clock synchronous semiconductor device such as an SDRAM.

The synchronous delay control circuit has an external clock ECL.
K is input to the clock buffer 1 and the external clock E
It has a clock driver 4 that outputs an internal clock ICLK synchronized with CLK. In order to synchronize the external clock ECLK and the internal clock ICLK within a certain clock frequency range, a delay monitor circuit 2 and a delay control unit 3 are provided between the clock buffer 1 and the clock driver 4.
Are provided.

The delay monitor circuit 2 provides a dummy for giving a total propagation delay (d1 + d2) of the delay time d1 in the dry clock buffer 1 and the delay time d2 in the clock driver 4 for the clock IN obtained in the clock buffer 1. It is a delay circuit. The delay times d1 and d2 are known, and the delay monitor circuit 2 is designed to obtain a fixed propagation delay time (d1 + d2).

The delay control unit 3 has two delay lines 3 for giving different propagation delays to the pulse output obtained from the delay monitor circuit 2 in accordance with the clock frequency.
1, 32. Each of the delay lines 31 and 32 is constituted by a plurality of cascaded unit delay elements. The first delay line 31 has a pulse output obtained from the delay monitor circuit 2 as a start signal START, an output of the clock buffer 1 as a stop signal STOP, and a clock cycle as tCK, and an output pulse with a propagation delay of tCK- (d1 + d2). Obtain D1.

That is, as shown in FIG.
TOP is a signal delayed by a time d1 by the clock buffer 1 with respect to the external clock ECLK, and a start signal START is a signal delayed by a delay time (d1 + d2) of the delay monitor circuit 2 with respect to the stop signal STOP. is there. Therefore, the output D1 can be obtained by extracting each delay element output of the first delay line 31 by the selector 35 controlled by the stop signal STOP.

More specifically, the selector output preceding the selector output D1 of the first delay line 31 is used as an activation signal as the second output.
, And the clock IN enters the unit delay element stage of the second delay line 32 activated by the output D1. Thereby, the second delay line 32 receives the propagation delay output D1 of the first delay line 31 at the same transfer stage and transfers the same in the opposite direction to the first delay line 31, and
A pulse output D2 having the same propagation delay tCK- (d1 + d2) as that of the delay line 31 is output. The pulse output D2 of the second delay line 31 is supplied to the clock driver 4, and the clock driver 4 receives the delay of time d2 to generate the internal clock ICLK. Therefore, as shown in FIG. 3, the internal clock IC
The total delay time until the output of LK is d1 + 2 @ tCK-
(D1 + d2)｝ + d2 = 2tCK, and the internal clock ICL synchronized with the external clock ECLK with a delay of two cycles
K is obtained.

As shown in FIG. 2, a variable delay element d having a variable delay time and a delay time fixed to a minimum value as long as the manufacturing process allows are provided for the unit delay elements constituting the delay lines 31 and 32. And the minimum delay element δ.
That is, the delay lines 31 and 32 are each divided into two stages,
A plurality of variable delay elements d are arranged in the first stage (Coarse Stage), and a plurality of minimum delay elements δ are arranged in the second stage (Fine Stage).

Also, as shown in FIG.
In order to control the two variable delay elements d according to the clock frequency, the output pulse I obtained from the clock buffer 1 is used.
A frequency detection circuit 33 for detecting a clock frequency based on N and a controller 34 for controlling the variable delay element d according to the output FREQ of the frequency detection circuit 33 are provided.

The unit delay elements of the delay lines 31 and 32 are the number of elements necessary to obtain a delay of about two cycles of the external clock frequency specified in the specification. For example, in the case of a semiconductor device operating at an external clock cycle of 10 nsec, 2
A unit delay element group that can provide a delay of about 0 nsec is prepared. If the delay time of each unit delay element is 200 psec, as in the related art, the number of unit delay elements to be arranged is 100 stages. In this case, when operating at the reference clock cycle, only about 50 stages are used.

On the other hand, in the case of this embodiment, two types of variable delay elements d and minimum delay elements δ are used as the unit delay elements. 200 pse delay time for minimum delay element δ
c, the delay time of the variable delay element is from 200 psec to 400
If it can be changed within the range of psec, 200 ns
In order to obtain a delay of ec, the variable delay
Assuming that the number of stages and the minimum delay element δ are 25, a total of 63 stages can be configured.

In the case of this embodiment, the delay amounts of the delay lines 31 and 32 are changed according to the clock frequency as shown in FIGS.
Control is performed as shown in FIG. FIG. 4B shows a standard clock frequency. At this time, the delay lines 31 and 32
Are set to the minimum delay time dmin, and all the variable delay elements (n) and an appropriate number (m) of the minimum delay elements δ are used.

On the other hand, FIG.
In the case of (c), the variable delay element d of the delay lines 31 and 32
Is set to the maximum delay time dmax, and all variable delay elements (n) and the appropriate number of minimum delay elements δ (m
) Are used. As described above, by controlling the delay time of the variable delay element d according to the clock frequency, it is possible to cope with a wide frequency even with a small number of elements. 4 (b) and 4 (c), the delay lines 31 and 3
In No. 2, since the minimum delay element δ is used, high-precision synchronous control with small jitter can be performed.

When the clock frequency is higher than that shown in FIG. 4B, as shown in FIG.
In 2, it is also possible to use only an appropriate number x of the variable delay elements d. In this case, if the variable delay element d is set to the minimum delay time dmin, highly accurate synchronous control can be performed.

In this embodiment, the frequency detection circuit 33 and the controller 34 are mounted in the same semiconductor device when the synchronous delay control circuit of this embodiment is mounted on the semiconductor device. By providing a circuit for detecting the frequency of the external clock in the semiconductor device in this manner, there is no need to perform special register settings or fuse settings in accordance with the external clock, and the clock frequency to be used during operation of the semiconductor device is reduced. Even if it changes, it can automatically respond to this.

FIG. 5 shows the minimum delay element δ and the variable delay element d.
Is shown. The minimum delay element δ is formed by a PMOS transistor QP11 and an NMO
This is a clocked CMOS inverter having an S transistor QN11, a PMOS transistor QP12 controlled by a complementary clock, and an NMOS transistor QN12, and uses a fixed power supply voltage VDD. By setting the power supply voltage VDD to a high value, a minimum delay can be obtained.

The variable delay element d includes a PMOS transistor QP21 and an NMOS transistor QN21 constituting an inverter main body, and a PM controlled by a complementary clock.
OS transistor QP22 and NMOS transistor QN
22 is a clocked CMOS inverter having a variable power supply voltage VVDD. This power supply voltage VVD
D is variably controlled in accordance with the clock frequency so that a large amount of delay can be obtained with a high power supply voltage and a small amount of delay can be obtained with a low power supply voltage.

As shown in FIG. 6, the frequency detection circuit 33 includes a pulse generator 331 for generating a pulse output Pu having a constant pulse width W based on the output pulse IN of the clock buffer 1, and an output of the pulse generator 331. A phase comparator 332 that compares the phase of the pulse Pu with the phase of the output pulse IN of the clock buffer 1 can be used.

As shown in FIG. 7, when the phase θ1 of the falling edge of the pulse output IN and the phase θ2 of the falling edge of the pulse output Pu are detected by the phase comparator 332, the clock frequency is higher than a certain value. Or low. That is, if θ1 <θ2, the clock cycle tC
K is less than tCK0 = 2W, so the clock frequency is high. At this time, for example, the frequency detection output is FREQ
H = “H”. If θ1> θ2, the clock cycle tCK is greater than tCK0, and thus the clock frequency is low. At that time, the output becomes FREQH = "L".

As described above, by the edge detection and the phase comparison,
The clock frequency can be easily detected. In particular, with such a circuit configuration, the frequency can be detected in principle in units of one cycle of the external clock, and high-speed frequency detection can be performed. Further, such a pulse generator 331 and the phase comparator 3
If a plurality of sets of 32 are prepared and the output pulse width W of each pulse generator 331 is set to a different value, the clock frequency can be determined in a plurality of stages.

FIG. 8 shows the output FRE of the frequency detection circuit 33.
It is a configuration example of a controller 34 that controls a variable delay element d in response to QH. The controller 34 is turned on when the frequency detection output FREQH = "H", and turned on when the frequency detection output FREQ = "L", and turned on when the frequency detection output FREQ = "L". CMOS transfer gate TG2 for outputting output voltage VVDD by dropping voltage VDD by a constant voltage
Having.

Here, one diode-connected NMOS transistor QN31 is used to lower the power supply voltage VDD. As a result, the threshold voltage of the NMOS transistor QN31 is set to Vth and VVDD
= VDD-Vth. That is, when the clock frequency is higher than a certain value, the power supply voltage VDD can be applied to the variable delay element d to obtain the minimum delay time. When the clock frequency is lower than the predetermined value, the power supply voltage VVDD can be applied and the minimum delay time can be obtained. A large delay time can be provided.

As described above, two transfer paths which are controlled to be switched by the frequency detection output FREQH are provided, and one transfer path keeps the power supply voltage VDD as it is, and the other transfer path lowers the power supply voltage VDD, and the variable delay Element d
, The delay time can be switched. 8, one diode-connected NMOS transistor QN31 is used, but a plurality of NMOS transistors QN31 are provided in series,
If the number of connection stages can be switched, a variable power supply voltage in a plurality of stages can be obtained. In addition, if a plurality of controllers having different numbers of arranged NMOS transistors QN31 are provided side by side and a power supply voltage that can be switched by a plurality of stages of frequency detection output is prepared, the power supply voltage according to the frequency is quickly determined. This is particularly effective when it is desired to reduce the time from when the external clock is supplied to when the semiconductor device enters a normal operation.

FIG. 9 shows the frequency detection circuit 33 shown in FIG.
5 is a configuration example of the pulse generator 331 in FIG. The pulse generator 331 inputs the captured clock IN and the signal INDLY obtained by inverting and delaying the clock IN by the inverters INV1 to INV3 to the NOR gate G1, and generates a pulse Pu at the edge of the clock IN. Although the basic configuration is well known, in this embodiment, a clocked CMOS inverter is used for the inverters INV1 to INV3 to variably control the delay time here, and the pulse width variation of the pulse output Pu due to process variation. It is trying to suppress.

More specifically, comparators CMP1 and CMP
2 are inverters INV1 to INV constituting a delay circuit
3 constitutes a monitor circuit for monitoring the characteristics of the circuit elements. The threshold voltage of the PMOS transistor is set to a PMOS having a gate and a drain connected to a reference voltage VREFP.
The voltage drop of the transistor QP41 is detected by the input comparator CMP1. If the voltage is low, the PMOS-side control signal Pgat of the inverters INV1 to INV3 is detected.
e is raised. Also, the NMOS transistor QN41
Is detected by a comparator CMP2 which receives a reference voltage VREFN and a voltage drop of an NMOS transistor QN41 having a gate and a drain connected thereto, and when the voltage is low, the NMOS of the inverters INV1 to INV3 is detected.
The side control signal Ngate is lowered. By performing such control, the pulse width variation of the pulse output Pu due to the process variation can be suppressed.

FIG. 10 shows the phase comparator 332 shown in FIG.
This is an example of the configuration. The output pulse Pu of the pulse generator 331
And the clock input IN to the NOR gate G2,
Obtain the signal PD. Then, the clock IN is supplied to the inverter I
A signal slightly delayed by NV6 and INV7, and a signal P
D is taken into the latch circuit LAT. The inverter INV5 provided on the input side of the pulse Pu of the NOR gate G2 is a dummy for balancing input impedance.

As shown in FIGS. 11A and 11B, "H" and "L" of the signal PD fall at the falling timing of the clock input IN when the clock input IN is at a high frequency or at a low frequency. different. Therefore, with a certain frequency as a reference, if the frequency is higher than that, FREQH = “L”
However, when the frequency is low, FREQH = "H" is latched.

FIG. 12 shows another combination of the minimum delay element δ and the variable delay element d. The minimum delay element δ is
It is the same as that of FIG. The variable delay element d is a clocked inverter that supplies a fixed power supply voltage VDD, and has a transfer gate TG3 inserted as a variable resistance element in its signal input path. This transfer gate has a CMOS structure. This transfer gate TG3
In addition, different control voltages VP and VN depending on the clock frequency
, The transfer gate TG3 is used as a variable resistor.

When the clock frequency is low, the control voltage V
P is increased and the control voltage VN is decreased. Thereby, the resistance of the transfer gate TG3 can be increased, and the delay amount can be increased. When the clock frequency is high, the resistance of the transfer gate TG3 can be reduced and the delay amount can be reduced by lowering the control voltage VP and raising the control voltage VN. The use of such a variable delay element d is advantageous because the amount of delay can be continuously changed in an analog manner.

FIG. 13 shows an example of the configuration of the frequency detection circuit 33 and the controller 34 shown in FIG. 2 when the unit delay element configuration shown in FIG. 12 is used. The frequency detection circuit 33 has a pulse generator 101 that generates a pulse at the edge of the clock input IN by using the odd-numbered inverters INV10 to INV12 and the NAND gate G5. Further, an integrating circuit 102 is constituted by a PMOS transistor QP51 controlled by the output of the pulse generator 101 and a capacitor C1 provided on the drain side. A constant current source I1 for discharging the integrator output VFREQ is provided in parallel with the capacitor C1.

When the clock frequency is low, the number of times the PMOS transistor QP51 turns on per unit time is small, and when the clock frequency is high, the number of times the PMOS transistor QP51 turns on increases. Therefore, the charging potential of the integrator output VFREQ changes according to the frequency, and frequency detection is performed.

The controller 34 is a circuit that generates control signals VP and VN for the input stage transfer gate TG3 of the variable delay element d shown in FIG. Integrator output VFR
NMOS transistor QN5 whose EQ is input to the gate
1 and a current source PMOS having a gate and drain connected together
The transistor QP52 forms an inverter. The output of this inverter becomes the control signal VP. The output stage includes a PMOS transistor QP5 forming a current mirror circuit with the current source PMOS transistor QP52.
3 and an NMOS transistor QN52 to which a current is supplied and to which a gate and a drain are commonly connected are provided. The drain output of the NMOS transistor QN52 becomes the control signal VN.

That is, when the clock frequency is high and the integrator output VFREQ is at a high potential, the NMOS transistor QN
51 turns on deeply. As a result, the control signal VP becomes low potential. At this time, a large current is supplied from the PMOS transistor QP53, so that the control signal VN becomes high. By giving the control signals VP and VN whose potentials change in accordance with the clock frequency to the input stage transfer gate TG3 of the variable delay element d in FIG. 9, the delay time can be controlled in accordance with the clock frequency.

FIG. 14 shows the case where the frequency detection circuit 3 shown in FIG. 13 is used in the case where the unit delay element configuration shown in FIG. 5 is used.
3 is a configuration example of a controller 34 that controls the power supply voltage of the variable delay element d by using the controller 3. This controller 34
A current mirror type differential amplifier 141, and a current source PMOS transistor QP whose current driving capability is controlled by the current mirror type differential amplifier 141
63 and an output stage 142 having a constant current source I3. Differential NMOS transistor pair QN61, QN62
Is the output VF of the frequency detection circuit 33 shown in FIG.
REQ is input, and the variable power supply voltage VVDD output from the output stage 142 is input to the other end.

When the clock frequency is high and VFREQ is VV
When it is higher than DD, the current driving capability of the PMOS transistor QP63 increases, VVDD increases, and VVDD =
Stabilizes at VFREQ. When VFREQ is lower than VVDD, the current driving capability of the PMOS transistor QP63 decreases, VVDD decreases, and VVDD = VFREQ.
And stabilized. Thereby, the variable delay element d of the system of FIG.
Can be varied to the clock frequency.
If the output of the controller 34 in FIG. 14 is not an appropriate value, a level shifter or the like is inserted into the output,
What is necessary is just to obtain an appropriate value.

FIG. 15 shows the phase comparator 332 shown in FIG.
And the controller 34 shown in FIG.
This is a circuit configuration in which the frequency detection output VFREQ is latched to prevent inadvertent power switching. That is, a latch circuit LATb for holding the frequency detection output FREQH is provided, and its output is
4 to obtain the selection signal SELVDD.

When the frequency detection output FREQH by the phase comparator 332 in FIG. 10 is directly supplied to the controller 334 in FIG. 8, when the pulse width of the pulse output Pu matches the pulse width of the internal clock synchronized with the external clock, The power supply voltage fluctuates, and the jitter increases.
Therefore, when frequency detection is performed by supplying an external clock, it is desirable to keep the result constant.

For example, consider the case of a DRAM. Normal DR
In the AM, the internal operation of the DRAM is stopped until the activation signal is received from the controller. Based on such an activation signal, the latch signal FREQLAT shown in FIG.
Is generated, whereby the frequency detection output FREQH is held in the latch circuit LATb.

FIG. 16 shows the operation timing in this case. When the latch signal FREQLAT is "H" and the latch circuit L
When ATb is in the through state, the frequency detection output FREQH
The selection signal SELVDD changes to “H” and “L” in accordance with “H” and “L” of the signal. On the other hand, when the frequency is detected and FREQH changes from "H" to "L", that is, when it is detected that the clock frequency is lower than a certain value, the latch signal FREQLAT is set to "L". , The selection signal SELVDD can be held at “L”. Thereby, the power supply voltage VVDD of the variable delay element d
Is stably held at a value lower than VDD, and a large delay time can be obtained. Therefore, it is possible to prevent jitter at a specific frequency.

[0056]

As described above, in the synchronous delay control circuit according to the present invention, the variable delay element having a variable delay time and the variable delay element having a fixed delay time are connected to the delay line composed of a plurality of unit delay elements used in the delay control unit. By using a fixed delay element, synchronization control can be performed over a wide clock frequency with a small number of unit delay elements, and high synchronization accuracy can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a synchronous delay control circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a main configuration of a delay unit according to the embodiment.

FIG. 3 is a diagram showing operation timings of the synchronous delay control circuit according to the embodiment.

FIG. 4 is a diagram showing how the combination of unit delay elements changes in relation to the clock frequency in the embodiment.

FIG. 5 is a diagram showing a configuration example of a unit delay element used in the delay line of the embodiment.

FIG. 6 is a diagram illustrating a specific configuration example of the frequency detection circuit of FIG. 2;

FIG. 7 is an operation timing chart of the pulse generator of FIG. 6;

FIG. 8 is a diagram illustrating a specific configuration example of a controller in FIG. 2;

FIG. 9 is a diagram illustrating a specific configuration example of the pulse generator of FIG. 6;

FIG. 10 is a diagram illustrating a specific configuration example of the phase comparator of FIG. 6;

FIG. 11 is a timing chart illustrating the principle of frequency detection by the phase comparator.

FIG. 12 is a diagram illustrating another configuration example of the unit delay element.

13 is a diagram illustrating another configuration example of the frequency detection circuit and the controller in FIG. 2;

14 is a diagram illustrating a configuration example of another controller combined with the frequency detection circuit of FIG. 13;

15 is a diagram showing a preferred circuit configuration when the phase comparator of FIG. 11 and the controller of FIG. 8 are combined.

16 is an operation timing chart of the circuit of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Clock buffer, 2 ... Delay monitor circuit, 3 ... Delay control unit, 31, 32 ... Delay line, 4 ... Clock driver, d ... Variable delay element, delta ... Minimum delay element, 33 ...
Frequency detection circuit, 34: controller, 331: pulse generator, 332: phase comparator.

Claims (11)

[Claims] A clock buffer for receiving an external clock; a clock driver for outputting an internal clock synchronized with the external clock; and a first pulse output by the clock buffer for the first pulse output from the clock buffer and the clock driver. A delay monitor circuit for outputting a second pulse having a total delay time, and a plurality of cascade-connected unit delay elements;
A second pulse output from the delay monitor circuit is input to a first stage, and a first pulse is output at a timing synchronized with the external clock, the third pulse being given a predetermined propagation delay with respect to the second pulse. And a plurality of cascade-connected unit delay elements, and the third pulse output from the first delay line is given the same propagation delay as that of the first delay line to the clock driver. A synchronous delay control circuit including a second delay line to be supplied, wherein the first and second delay lines are each configured by a variable delay element having a variable delay time from a first stage to a predetermined number of stages, and Is a fixed delay element having a fixed delay time. 2. The synchronous delay control circuit according to claim 1, wherein said fixed delay element is a minimum delay element capable of obtaining a minimum delay time as long as a manufacturing process allows. 3. A frequency detection circuit for detecting a frequency of an external clock, and a controller for controlling a delay time of the variable delay element according to an output of the frequency detection circuit. Synchronization delay control circuit. 4. A pulse generator for generating a pulse signal having a constant pulse width in synchronization with an output clock of the clock buffer; a pulse signal output by the pulse generator and an output of the clock buffer. 4. The synchronous delay control circuit according to claim 3, further comprising a phase comparator for comparing a phase of the clock. 5. The fixed delay element is constituted by a clocked inverter to which a fixed power supply voltage is applied, the variable delay element is constituted by a clocked inverter to which a variable power supply voltage is applied, and the controller comprises: A transfer path for transferring a fixed power supply voltage to a power supply terminal of the variable delay element, which is switched and controlled by an output of the frequency detection circuit, and transferring the fixed power supply voltage to a power supply terminal of the variable delay element by lowering the level of the fixed power supply voltage 4. The synchronous delay control circuit according to claim 3, wherein the synchronous delay control circuit comprises: 6. A pulse generator, comprising: a delay circuit for inverting and delaying an output clock of the clock buffer; and a pulse at an edge of the output clock based on a logic of an output of the delay circuit and an output clock of the clock buffer. 5. The synchronous delay control circuit according to claim 4, further comprising: a logic gate that generates a signal; and a circuit element monitor circuit that monitors element characteristics of the delay circuit and controls the delay circuit to keep the delay characteristic constant. 7. The fixed delay element includes a clocked inverter to which a fixed power supply voltage is applied, and the variable delay element includes a clocked inverter to which a variable resistance element is inserted into an input path to supply a fixed power supply voltage. The synchronous delay control circuit according to claim 3, wherein the synchronous delay control circuit is configured by an inverter, and wherein the controller controls the resistance of the variable resistance element according to an output of the frequency detection circuit. 8. The frequency detection circuit, comprising: a pulse generator for generating a pulse signal at an edge of an output clock of the clock buffer; and a current source controlled by an output of the pulse generator so as to correspond to a frequency of the external clock. An integrator that outputs a frequency detection signal whose potential changes with the change in the potential, wherein the controller controls the resistance of the variable resistance element by a frequency detection signal obtained from the integrator. 7. The synchronous delay control circuit according to 7. 9. The fixed delay element is constituted by a clocked inverter to which a fixed power supply voltage is applied; the variable delay element is constituted by a clocked inverter to which a variable power supply voltage is applied; A pulse generator that generates a pulse signal at an edge of an output clock of the clock buffer, and a current source controlled by an output of the pulse generator to output a frequency detection signal whose potential changes according to the frequency of the external clock. An integrator, wherein the controller has a differential amplifier to which a frequency detection signal obtained from the integrator and a variable power supply voltage output are input, and a current source is controlled by an output of the differential amplifier. 4. The synchronous delay system according to claim 3, further comprising an output circuit for outputting the variable power supply voltage. Your circuit. 10. The synchronous delay control circuit according to claim 3, further comprising a latch circuit between the output of the frequency detection circuit and the controller for latching the output of the frequency detection circuit. 11. A clock synchronous semiconductor device incorporating the synchronous delay control circuit according to claim 1.