CN110995241B - LVDS delay circuit with self-adaptive phase adjustment - Google Patents
LVDS delay circuit with self-adaptive phase adjustment Download PDFInfo
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- CN110995241B CN110995241B CN201911279697.XA CN201911279697A CN110995241B CN 110995241 B CN110995241 B CN 110995241B CN 201911279697 A CN201911279697 A CN 201911279697A CN 110995241 B CN110995241 B CN 110995241B
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Abstract
The invention provides an adaptive phase adjustment LVDS delay circuit, wherein input signals of a multi-stage delay circuit are LVDS input data, a multiplexer selects and outputs several stages of delay, the output signal of the multiplexer is a data signal subjected to delay selection, the data signal is an input signal subjected to adaptive judgment, the adaptive judgment determines delay parameters of a clock alignment data intermediate window, and the delay parameters are output to serve as control signals of the multiplexer. The invention reduces the iteration times of determining proper delay parameters, reduces the scale and complexity of a delay circuit, improves the time sequence convergence speed and eliminates the deburring problem caused by clock switching; the appropriate delay parameter can be automatically found without repeated iterative tests by the user; the delay value of the data middle window aligned to the clock edge can be accurately found, and the stability of the sampled data is greatly improved.
Description
Technical Field
The invention relates to the technical field of signal processing, in particular to an LVDS delay circuit which can meet the requirements of different application systems on accurate sampling of high-speed LVDS.
Background
With the increase of the transmission rate of the LVDS signals, the time window occupied by each bit of the signals is continuously reduced, so that the sampling accuracy of the sampling clock to the sampling points of the signals in the effective interval is reduced; in addition, due to the difference of transmission paths, the delay time of each data line and the delay time of the sampling clock reaching the receiving end cannot be guaranteed to be completely consistent, and therefore, the offset between the clock and the data signal is brought. The LVDS delay circuit adjusts the relative phase of the clock and the data by adjusting the data or the delay of the clock, and completes stable and correct sampling.
The traditional LVDS delay circuit adjusts the relative phase of the clock and the data by adjusting the delay of the clock, as shown in fig. 1, the circuit needs to precisely control the delay time of the clock, so that the phases of the multi-bit data and the clock can simultaneously meet the timing sequence requirement. And the circuit does not have the function of self-adaptive phase adjustment. As shown in fig. 2. In practical application, the following disadvantages exist:
1. the requirement on the precision of the delay time is high, so that the iteration times and delay steps are more, and the scale of a delay circuit is large;
2. the circuit cannot automatically find out proper delay amount, the delay time needs to be changed continuously for testing in different application scenes until a proper delay value is found, and the found delay value cannot ensure that the clock edges are aligned to a data middle window;
3. the clock is used as a global variable, once the path delay is changed, the phase relation between other data of the clock domain and the clock is changed, and the time sequence convergence of other data paths becomes difficult;
4. the output clock of the circuit is obtained by selecting the clock after different delays, the selection of the clock needs to be carried out with special deburring treatment, the complexity of the circuit is increased, the delay of a clock path is changed, and the delay difference with the design requirement is large.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides an LVDS delay circuit device with a self-adaptive phase adjustment function. The clock is used as a reference, each bit of data is delayed, the adjustment of data and clock phases is realized, and the delay amount required by each bit of data is found in a self-adaptive manner, so that the aim of stable and accurate sampling is fulfilled.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a self-adaptive phase-adjusting LVDS circuit comprises a multistage delay circuit, a multiplexer and a self-adaptive judging module, wherein the self-adaptive judging module comprises training code matching, delay control, data left edge determination, delay parameter calculation of alignment in the middle of a data window and data right edge determination.
The input signal of the multistage time delay circuit is LVDS input data, the multistage time delay circuit is formed by 32 stages of time delay, several stages of time delay are selected and output through a multiplexer, the input signal of the multiplexer is a data signal after 32 stages of time delay, a control signal is output by self-adaptive judgment, the output signal of the multiplexer is the data signal after time delay selection, the data signal is the input signal of the self-adaptive judgment, the self-adaptive judgment determines the time delay parameter of a clock alignment data middle window, and the time delay parameter is output to serve as the control signal of the multiplexer.
The input signal entering the self-adaptive judgment enters the training code matching for judgment, a sampled data signal is output, the data signal enters the delay control, the data signal after the delay is output, the data signal is used as the input of the left edge of the determined data and the right edge of the determined data, when the data signal is judged to enter the right edge of the determined data, the delay parameter when the clock is aligned with the right edge of the data window is calculated, the delayed data is sent to the delay control for delay, and then the data enters the left edge of the determined data; when the data signal is judged to enter the left edge of the determined data, calculating a delay parameter when the clock is aligned with the left edge of the data window, sending the delay parameter to the delay parameter calculation aligned in the middle of the data window, wherein an input signal calculated by the delay parameter aligned in the middle of the data window is the delay parameter determined by the right edge of the determined data or the left edge of the determined data, and obtaining the delay parameter of the middle window of the clock aligned data after calculation.
When the self-adaptive judgment works, firstly, an external circuit sends a group of training codes, the bit width of the training codes is consistent with the bit width of data needing to be processed in parallel at the next stage of LVDS in a system, the code memory of the content of the training codes has the requirement of at least one jump edge, the training codes pass through a multi-stage delay circuit (1) and a multiplexer (2) and enter a self-adaptive judgment (3), the initial delay of the multi-stage delay circuit (1) is 0, after the initial training codes enter the self-adaptive judgment (3), the training codes are matched (31) and sampled by a system clock, whether an output result is consistent with an input training code is checked, if the output result is consistent with the input training code, the delay value at the moment is recorded as 0, the delay value enters a delay control module (32), a plurality of delays are added, the data enter a determined left edge (33) of the data, until the clock sampling data result is matched with the training codes again, the delay value at the moment is recorded, the delay parameter calculation (34) of the delay parameter aligned in the middle of the data window is carried out, and the delay parameter of the middle position of the clock aligned data window is calculated; if the data is inconsistent with the clock sampling data, the data enters a delay control module (32), a plurality of delays are added, the data right edge is determined (35), until the clock sampling data result is matched with the training code, the delay value at the moment is recorded, the delays are continuously increased, the data left edge is determined (33), until the clock sampling data result is matched with the training code again, the delay value at the moment is recorded, the delay parameter calculation (34) of data window middle alignment is carried out, and the delay parameter of the clock edge alignment data window middle position is calculated. The delay parameter determines that the input signal of the delay circuit outputs samples after several stages of delay.
The invention has the beneficial effects that:
1) According to the invention, a data delay mode is adopted, so that the iteration times for determining a proper delay parameter are reduced, the scale and complexity of a delay circuit are reduced, the time sequence convergence speed is improved, and the deburring problem caused by clock switching is eliminated;
2) The invention can automatically find out proper time delay parameters without repeated iterative tests of users due to the adoption of self-adaptive judgment;
3) The invention can accurately find the delay value of the data middle window aligning to the clock edge by adopting the self-adaptive judging method of the left edge and the right edge, thereby greatly improving the stability of the sampling data.
Drawings
FIG. 1 is a block diagram of a clock delay scheme employed by a conventional LVDS delay circuit;
FIG. 2 is a block diagram of a conventional LVDS delay circuit;
FIG. 3 is a block diagram of a data delay sampling scheme employed by the present invention;
FIG. 4 is a block diagram of an adaptive phase adjusted LVDS delay circuit of the present invention;
FIG. 5 is a block diagram of an adaptive decision module of an adaptive phase-adjusted LVDS delay circuit according to the present invention;
fig. 6 is a diagram illustrating an exemplary application of the adaptive phase adjustment LVDS delay circuit according to the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
The present invention aims to overcome the above drawbacks of the prior art, and provide an adaptive phase adjustment LVDS delay circuit, which delays each bit of data with reference to a clock to adjust the phase of the data and the clock, as shown in fig. 3, and adaptively finds the amount of delay required by each bit of data to achieve the purpose of stable and accurate sampling, as shown in fig. 4.
A self-adaptive phase adjustment LVDS circuit comprises a multistage delay circuit, a multiplexer and a self-adaptive judging module, wherein the self-adaptive judging module comprises training code matching, delay control, data left edge determination, delay parameter calculation of alignment in the middle of a data window and data right edge determination.
The input signal of the multistage time delay circuit is LVDS input data, the multistage time delay circuit is formed by 32 stages of time delay, several stages of time delay are selected and output through a multiplexer, the input signal of the multiplexer is a data signal after 32 stages of time delay, a control signal is output by self-adaptive judgment, the output signal of the multiplexer is the data signal after time delay selection, the data signal is the input signal of the self-adaptive judgment, the self-adaptive judgment determines the time delay parameter of a clock alignment data middle window, and the time delay parameter is output to serve as the control signal of the multiplexer.
The input signal entering the self-adaptive judgment enters the training code matching for judgment, a sampled data signal is output, the data signal enters the delay control, the data signal after the delay is output, the data signal is used as the input of the left edge of the determined data and the right edge of the determined data, when the data signal is judged to enter the right edge of the determined data, the delay parameter when the clock is aligned with the right edge of the data window is calculated, the delayed data is sent to the delay control for delay, and then the data enters the left edge of the determined data; when the data signal is judged to enter the left edge of the determined data, calculating a delay parameter when the clock is aligned with the left edge of the data window, sending the delay parameter to the delay parameter calculation aligned in the middle of the data window, wherein an input signal calculated by the delay parameter aligned in the middle of the data window is the delay parameter determined by the right edge of the determined data or the left edge of the determined data, and obtaining the delay parameter of the middle window of the clock aligned data after calculation.
As shown in fig. 5, during the adaptive decision operation, an external circuit first sends a set of training codes, the bit width of the training codes is consistent with the bit width of data to be processed in parallel at the next stage of LVDS in the system, there is a requirement for at least one transition edge in the code of the content of the training codes, for example, the training code of the LVDS delay circuit in a certain radar system is 0000_0000_0011_1111 \, the training codes pass through a multi-stage delay circuit (1) and a multiplexer (2) and enter an adaptive decision (3), the initial delay of the multi-stage delay circuit (1) is 0, after the initial training code enters the adaptive decision (3), the training code matching (31) samples the training code by using a system clock, see whether the output result is consistent with the input training code, if so as to record the delay value at this time as 0, and enter a delay control module (32), add a plurality of delays, enter a left edge of determined data (33), until the clock sampling data result is matched with the training code again, record the delay value at this time, enter a delay parameter of the middle alignment of a data window, calculate a middle position of the delay parameter (34), and calculate a middle position of the delay parameter; if the data is inconsistent with the clock sampling data, the data enters a delay control module (32), a plurality of delays are added, the data right edge is determined (35), until the clock sampling data result is matched with the training code, the delay value at the moment is recorded, the delays are continuously increased, the data left edge is determined (33), until the clock sampling data result is matched with the training code again, the delay value at the moment is recorded, the delay parameter calculation (34) of data window middle alignment is carried out, and the delay parameter of the clock edge alignment data window middle position is calculated. The delay parameter determines that the input signal of the delay circuit outputs samples after several stages of delay.
The self-adaptive phase-adjusting LVDS delay circuit adjusts the relative phase of data and a clock by adopting a data delay mode, automatically finds out a proper delay parameter through self-adaptive judgment, aligns the clock edge with the middle position of a data window, and achieves stable and correct sampling. The data delay mode is based on a clock, each path of data is adjusted to meet the sampling time sequence, compared with the clock delay mode, the iteration times are greatly reduced, the scale and the complexity of a delay circuit are reduced, time sequence convergence is easier, and the LVDS interface can automatically find appropriate delay parameters in various environments by self-adaptive judgment to meet the sampling time sequence requirement. The self-adaptive judging method of the left and right edges can accurately find the delay value of the data middle window aligned to the clock edge, and greatly improves the stability of the sampled data.
As shown in fig. 3, the adaptive phase-adjusted LVDS delay circuit of the present invention adjusts the phase relationship between the clock and the data in a data delay manner, and by determining the left edge and the right edge of the data, the data is delayed, so that the middle window of the data is aligned with the clock edge, thereby ensuring stable and correct sampling. As shown in fig. 4, the LVDS circuit with adaptive phase adjustment of the present invention is integrated with a multi-stage delay circuit (1), a multiplexer (2), and an adaptive decision module (3), wherein the adaptive decision module is composed of a training code matching (31), a delay control 32, a data left edge determination (33), a data window middle alignment delay parameter calculation (34), and a data right edge determination (35).
The circuit reduces the iteration times of finding proper delay parameters through data delay, reduces the scale and complexity of a delay circuit, improves the time sequence convergence speed, eliminates the deburring problem caused by clock switching, automatically finds the proper delay parameters through the self-adaptive judging module, is convenient for a user to use, can accurately find the delay value of a data middle window aligned with the clock edge through the self-adaptive judging method of the left edge and the right edge, and greatly improves the stability of sampled data.
The working principle of the circuit is as follows: in the test mode, an external circuit sends a group of training codes, the training codes enter a self-adaptive judging circuit (3) through a multi-stage delay circuit (1) and a multiplexer (2), a proper delay parameter is found, the group of parameters is recorded, in the normal working mode, the delay parameter determined by the test mode is adopted, and input data are directly output through the multi-stage delay circuit (1) and the multiplexer (2).
An example of the operation of the circuit is as follows: in a certain application environment, an external circuit sends a training code 0000_0000_0011_1111_, the external circuit firstly enters a multi-stage delay circuit (1), the external circuit enters a self-adaptive decision (3) after initial zero delay, the training code is sampled by a training code matching module (31), a sampling output result is inconsistent with the training code, the external circuit enters a delay control module (32), first-stage delay is added, the external circuit enters a data right edge (35) for determining data, a clock sampling data result is inconsistent with the training code, first-stage delay is continuously added, the clock sampling data result is consistent with the training code, a delay value at the moment is recorded to be 4, the external circuit enters delay parameter calculation (34) for data window middle alignment, and a delay parameter of the middle position of a clock edge alignment data window is calculated to be 4+2)/2=3. And during actual work, external data enters the delay circuit and is sampled and output after being delayed by the determined 3 levels.
An example of an application of the present invention is shown in fig. 6. The circuit can work in a transmitting loop and a receiving loop simultaneously, in the receiving loop, a receiving antenna 1 receives radio frequency signals, the radio frequency signals respectively enter a down-conversion circuit 2, an A/D3, an LVDS transmitting circuit 4 and an LVDS receiving circuit 5, then enter an LVDS delay circuit 6 with self-adaptive phase adjustment, and correct sampling data after delay adjustment are sent to a subsequent data transmission and processing circuit 7.
In the sending loop, data transmission and processing 7 sends out data to be sent through an LVDS interface, the data respectively enters an LVDS delay circuit 6 with adaptive phase adjustment after being sent by an LVDS 4 and received by an LVDS 5, the correctly sampled data after being subjected to delay adjustment is sent to a D/A8, and the correctly sampled data is sent out through an up-conversion 9 and finally sent out through a transmitting antenna 10.
Compared with the traditional application mentioned in the background technology, the traditional clock delay circuit has large scale and slow time sequence convergence, burrs are introduced in clock switching, delay parameters cannot be found in a self-adaptive mode, and the use is complex.
The circuit of the invention adopts the self-adaptive data delay, reduces the iteration times of finding the proper delay parameter, reduces the scale and the complexity of the delay circuit, improves the time sequence convergence speed, eliminates the deburring problem caused by clock switching, automatically finds the proper delay parameter through the self-adaptive judging module, is convenient for a user to use, can accurately find the delay value of the data middle window aligned to the clock edge through the self-adaptive judging method of the left edge and the right edge, and greatly improves the stability of the sampling data.
The application of the present invention can be further extended and used in all signal processing systems using high-speed LVDS interfaces.
Claims (2)
1. An adaptive phase adjustment LVDS delay circuit is characterized in that:
the self-adaptive phase-adjusting LVDS circuit comprises a multistage delay circuit, a multiplexer and a self-adaptive judging module, wherein the self-adaptive judging module comprises training code matching, delay control, data left edge determination, delay parameter calculation of alignment in the middle of a data window and data right edge determination;
the input signal of the multistage delay circuit is LVDS input data, and is formed by 32-stage delay, several stages of delay are selected and output through a multiplexer, the input signal of the multiplexer is a data signal after 32-stage delay, a control signal is output by self-adaptive judgment, the output signal of the multiplexer is the data signal after delay selection, the data signal is the input signal of the self-adaptive judgment, the self-adaptive judgment determines the delay parameter of a clock alignment data middle window, and the delay parameter is output to be used as the control signal of the multiplexer;
the input signal entering the self-adaptive judgment enters the training code matching for judgment, a sampled data signal is output, the data signal enters the delay control, the data signal after the delay is output, the data signal is used as the input of the left edge of the determined data and the right edge of the determined data, when the data signal is judged to enter the right edge of the determined data, the delay parameter when the clock is aligned with the right edge of the data window is calculated, the delayed data is sent to the delay control for delay, and then the data enters the left edge of the determined data; and when the data message is judged to enter the left edge of the determined data, calculating a delay parameter when the clock aligns the left edge of the data window, sending the delay parameter to the delay parameter calculation aligned in the middle of the data window, wherein an input signal of the delay parameter calculation aligned in the middle of the data window is the delay parameter determined by the right edge of the determined data or the left edge of the determined data, and obtaining the delay parameter of the middle window of the clock aligning data after calculation.
2. The adaptive phase-adjusted LVDS delay circuit according to claim 1, wherein:
when the self-adaptive judgment works, firstly, an external circuit sends a group of training codes, the bit width of the training codes is consistent with the bit width of data needing to be processed in parallel at the next stage of LVDS in a system, the code memory of the content of the training codes has the requirement of at least one jump edge, the training codes pass through a multi-stage delay circuit (1) and a multiplexer (2) and enter a self-adaptive judgment (3), the initial delay of the multi-stage delay circuit (1) is 0, after the initial training codes enter the self-adaptive judgment (3), the training codes are matched (31) and sampled by a system clock, whether an output result is consistent with an input training code is checked, if the output result is consistent with the input training code, the delay value at the moment is recorded as 0, the delay value enters a delay control module (32), a plurality of delays are added, the data enter a determined left edge (33) of the data, until the clock sampling data result is matched with the training codes again, the delay value at the moment is recorded, the delay parameter calculation (34) of the delay parameter aligned in the middle of the data window is carried out, and the delay parameter of the middle position of the clock aligned data window is calculated; if not, the circuit enters a delay control module (32), a plurality of delays are added, a right edge (35) of the determined data is entered until a clock sampling data result is matched with a training code, a delay value at the moment is recorded, the delays are continuously increased, a left edge (33) of the determined data is entered until the clock sampling data result is matched with the training code again, the delay value at the moment is recorded, a delay parameter calculation (34) aligned in the middle of a data window is entered, a delay parameter of the clock edge aligned with the middle position of the data window is calculated, and the delay parameter determines that an input signal of the delay circuit outputs and samples after several stages of delays.
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| CN114035417B (en) * | 2021-11-26 | 2023-04-14 | 杭州长川科技股份有限公司 | Head edge alignment method, head edge alignment circuit and system for multiple measurement links |
| CN115361344B (en) * | 2022-07-21 | 2023-05-12 | 湖南毂梁微电子有限公司 | Signal inclination compensation device and method |
| CN115801503B (en) * | 2022-11-18 | 2024-03-22 | 电子科技大学 | Cross-chip interconnection-oriented LVDS parallel data automatic calibration circuit and method |
| CN115834015B (en) * | 2023-02-27 | 2023-05-05 | 湖南跨线桥航天科技有限公司 | FPGA-based input signal self-adaptive time sequence alignment method |
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| CN106209341B (en) * | 2016-07-27 | 2019-02-12 | 上海航天控制技术研究所 | Multichannel LVDS timing is aligned detector image acquisition method |
| CN106782669B (en) * | 2016-11-23 | 2020-04-10 | 上海华力微电子有限公司 | Self-calibration extensible SRAM delay test circuit |
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