CN207352481U - Adaptive range rotating speed modulate circuit - Google Patents
Adaptive range rotating speed modulate circuit Download PDFInfo
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- CN207352481U CN207352481U CN201720772083.5U CN201720772083U CN207352481U CN 207352481 U CN207352481 U CN 207352481U CN 201720772083 U CN201720772083 U CN 201720772083U CN 207352481 U CN207352481 U CN 207352481U
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Abstract
It the utility model is related to a kind of adaptive range rotating speed modulate circuit, including signal generating circuit, circuit for signal conditioning, DAC output voltage reference circuit and DSP digital adaptation adjustment circuits.A kind of adaptive range rotating speed Opsonizing method is also disclosed in the utility model.Comparator reference is used as due to introducing 12 BIT DAC outputs, 1/4096 can be reached by comparing precision, introducing hysteresis comparator causes tach signal rising edge to avoid Zero-cross comparator error with trailing edge threshold value difference, due to only adapting to adjustment algorithm using DSP numerals, the optimal comparative level of system meeting Automatic-searching is contrasted with tach signal, avoids manual regulation stall.The adaptive rotating speed modulate circuit has circuit connection succinct, and no to cross zero error, degree of regulation is high, the remarkable advantages such as digital adaptation is adjusted.
Description
Technical field
It the utility model is related to a kind of rotating speed modulate circuit, and in particular to a kind of adaptive range rotating speed modulate circuit and tune
Reason method.
Background technology
Existing rotating speed modulate circuit generally adjusts chip using current potential and adjusts current potential and using multilevel amplifiers comparison circuit
To carry out current potential adjusting, degree of regulation is low, adjusts circuit complexity, it is necessary to the situation of manual facility range.China Patent Publication No.
CN204517772U, publication date are on 07 29th, 2015, and one is disclosed in the utility model patent of entitled rotating speed modulate circuit
Kind of rotating speed modulate circuit, using coarse adjustment and the multistage conditioning of fine tuning and using the potentiometer that limited gear current potential output can only be provided come
Resistance value is adjusted, can only realize that limited gear is adjusted, circuit stages connection is complicated to adapt to tach signal amplitude model, it is necessary to adjust manually
Enclose and degree of regulation is limited.
Utility model content
The purpose of this utility model is can only to realize that limited gear is adjusted for existing rotating speed modulate circuit, and circuit stages connect
Connect complicated, it is necessary to adjust the defects of adapting to tach signal amplitude range and limited degree of regulation manually.A kind of high accuracy is provided
Smooth gear is adjusted, simple circuit, no to cross the adaptive tach signal modulate circuit of zero error and Opsonizing method.
To achieve the above object, the utility model discloses following technical solution：
A kind of adaptive range rotating speed modulate circuit, including signal generating circuit, circuit for signal conditioning, DAC output voltage
Reference circuit and DSP digital adaptation adjustment circuits：
The signal generating circuit is connected to signal conditioning circuit input terminal, and the signal conditioning circuit is by resistance by partial pressure
Circuit, input protection circuit and hysteresis comparator circuit composition, the partial pressure that bleeder circuit obtains are connected to input protection circuit, and then
The negative-going signal input terminal for the comparator circuit being connected in hysteresis comparator circuit；Hysteresis comparator circuit is defeated by the negative terminal of comparator
The anode voltage reference signal for entering signal and comparator is contrasted, negative terminal signal voltage Amplitude Ration anode then hysteresis comparator greatly
Circuit output low level signal, otherwise output high level signal；The adaptive adjustment circuits of DSP are realized by programmable FPGA device,
The circuit includes clock signal input all the way, one group of 12BIT digital signals output, and signal input detecting circuit all the way, by
The DAC digital input ends of FPGA carelessness 12BIT digital signal accesses；DAC output terminal output reference voltages, DAC output voltage ginseng
The forward signal input terminal of the comparator circuit in circuit connection hysteresis comparator circuit is examined, sluggish ratio is provided for hysteresis comparator circuit
Compared with Voltage Reference；Clock reference circuit inputs to FPGA all the way, and clock reference is provided to digital circuit；Hysteresis comparator circuit exports
Square-wave signal all the way, is connected to FPGA signals input detecting circuit.
Further, the voltage signal output speed signal that the signal generating circuit is generated with approach switch sensor；
Approach switch sensor signal circuit includes：24V voltage source circuits are connected to probe power supply port all the way,
Sensor signal output port, current loop and port are provided for power supply with reference to 0 current potential.
Further, the bleeder circuit of the signal conditioning circuit includes resistance R683 and 1 foot of resistance R685, R683 connect
The signal output port of signal generating circuit, 1 foot of the 2 feet connection R685 of R683 are connected to, 2 feet of R685 are connected to 0V；Input
1 foot that protection circuit includes double diode D75, D75 is connected to 0V, and 2 feet are connected to power supply, and 3 feet are connected to 1 foot of R685；Late
Stagnant comparison circuit includes voltage-stablizer U126, resistance R684, R678, R679, R680,1 foot of the 1 foot connection R685 of R684, R684
2 feet be connected to 3 feet of U126,2 feet of the 1 foot connection R678 of U126, the 1 foot connection reference voltage of R678,1 foot of R679 connects
Connect 2 feet of R678, the 4 feet composition hysteresis comparator circuit of the 2 feet connection U126 of R679.
Further, the comparator chip model is LMV331M5.
Further, the DAC output voltage reference circuit includes I2C data communication bus and the 2nd foot of DAC, DAC are
I2C clock signals, the DATA signal that the 3rd foot of DAC is I2C connect FPGA, FPGA output digital reference signals, the 6th pipe of DAC
Foot exports analog voltage reference signal.
Further, the DAC models AD5622BKSZ-2REEL7.
Further, the FPGA models XC7020 of the adaptive adjustment circuits of the DSP.
A kind of adaptive range rotating speed Opsonizing method is also disclosed in the utility model, includes the following steps：
One signal input adaptive adjustment circuit occurs for S1, signal generating circuit；
S2, carry out first step partial pressure to the signal so that the voltage range that the circuit after partial pressure is handled in hysteresis comparator
It is interior；
S3, use clamp circuit so that being input to the signal of comparator in hysteresis comparator voltage encloses, if beyond
The signal input of the scope, clamp circuit can force clamper within the range；
S4, hysteresis comparator can be compared input signal and DAC output reference voltages, and the AC signal of input is whole
The square-wave signal of formation standard；
S5, FPGA receive square-wave signal, using timer calculate square-wave signal high level time and it is low level when
Between, to calculate the frequency of the square wave, to achieve the purpose that to measure key phase model；
If S6, FPGA only recognize high level, it will judge that key signal maximum is smaller than key signal, will pass through
The digital signal that the output of I2C buses reduces level-one is given to DAC, and the analog of DAC output reduction level-ones comes and enter key
Phase signals contrast, untill FPGA can recognize high level and low level in normal square wave；
If S7, FPGA only recognize low level, it will judge that the minimum value of key signal is bigger than reference signal, Jiu Huitong
Cross the output of I2C buses and put forward higher leveled digital signal to DAC, DAC, which is exported, carries higher leveled simulation ginseng ON signal and enter key
Phase signals contrast, and untill FPGA can recognize high level and low level in normal square wave, reach adaptive with this
The target of rotating speed conditioning.
A kind of adaptive range rotating speed modulate circuit and Opsonizing method disclosed in the utility model, due to introducing 12BIT
DAC outputs are used as comparator reference, and 1/4096 can be reached by comparing precision, introduce hysteresis comparator and cause tach signal rising edge
Different with trailing edge threshold value to avoid Zero-cross comparator error, due to only adapting to adjustment algorithm using DSP numerals, system can automatic seeking
Look for optimal comparative level to be contrasted with tach signal, avoid manual regulation stall.The adaptive rotating speed modulate circuit has
Circuit connection is succinct, and no to cross zero error, degree of regulation is high, the remarkable advantages such as digital adaptation is adjusted.
Brief description of the drawings
Fig. 1：Adaptive rotational speed regulation schematic block circuit diagram,
Fig. 2：Signal generating circuit schematic diagram,
Fig. 3：Signal conditioning circuit diagram,
Fig. 4：DAC reference circuit output schematic diagrams,
Fig. 5：DSP adaptively adjusts flow chart.
Fig. 6：The digital TTL circuits that FPGA is realized.
Embodiment
Below by the technical scheme in the utility model embodiment is clearly and completely described, it is clear that described
Embodiment is only the utility model part of the embodiment, instead of all the embodiments.Based on the implementation in the utility model
Example, those of ordinary skill in the art's all other embodiments obtained without making creative work, belongs to
The scope of the utility model protection.
The core of the utility model is to provide a kind of high-precision flat slide piece position and adjusts, simple circuit, and no zero error excessively is adaptive
Answer tach signal modulate circuit and Opsonizing method.
Refer to Fig. 1.A kind of adaptive range rotating speed modulate circuit, including signal generating circuit, circuit for signal conditioning,
DAC output voltage reference circuit and DSP digital adaptation adjustment circuits：
The signal generating circuit is connected to signal conditioning circuit input terminal, and the signal conditioning circuit is by resistance by partial pressure
Circuit, input protection circuit and hysteresis comparator circuit composition, the partial pressure that bleeder circuit obtains are connected to input protection circuit, and then
The negative-going signal input terminal for the comparator circuit being connected in hysteresis comparator circuit；Hysteresis comparator circuit is defeated by the negative terminal of comparator
The anode voltage reference signal for entering signal and comparator is contrasted, negative terminal signal voltage Amplitude Ration anode then hysteresis comparator greatly
Circuit output low level signal, otherwise output high level signal；The adaptive adjustment circuits of DSP are realized by programmable FPGA device,
The circuit includes clock signal input all the way, one group of 12BIT digital signals output, and signal input detecting circuit all the way, by
The DAC digital input ends of FPGA carelessness 12BIT digital signal accesses；DAC output terminal output reference voltages, DAC output voltage ginseng
The forward signal input terminal of the comparator circuit in circuit connection hysteresis comparator circuit is examined, sluggish ratio is provided for hysteresis comparator circuit
Compared with Voltage Reference；Clock reference circuit inputs to FPGA all the way, and clock reference is provided to digital circuit；Hysteresis comparator circuit exports
Square-wave signal all the way, is connected to FPGA signals input detecting circuit.
See Fig. 2, in a kind of embodiment of the utility model, the signal generating circuit is generated with approach switch sensor
Voltage signal output speed signal；
Approach switch sensor signal circuit includes：24V voltage source circuits are connected to probe power supply port all the way,
Sensor signal output port, current loop and port are provided for power supply with reference to 0 current potential.
See Fig. 3, in a kind of embodiment of the utility model, the bleeder circuit of the signal conditioning circuit includes resistance
1 foot of R683 and resistance R685, R683 are connected to the signal output port of signal generating circuit, and 2 feet of R683 connect the 1 of R685
Foot, 2 feet of R685 are connected to 0V；1 foot that input protection circuit includes double diode D75, D75 is connected to 0V, and 2 feet are connected to electricity
Source, 3 feet are connected to 1 foot of R685；Hysteresis comparator circuit includes voltage-stablizer U126, resistance R684, R678, R679, R680, R684
1 foot connection R685 1 foot, 2 feet of R684 are connected to 3 feet of U126,2 feet of the 1 foot connection R678 of U126,1 foot of R678
Connect reference voltage, 2 feet of the 1 foot connection R678 of R679, the 4 feet composition hysteresis comparator circuit of the 2 feet connection U126 of R679.
In a kind of embodiment of the utility model, the comparator chip model is LMV331M5.
See Fig. 4, in a kind of embodiment of the utility model, the DAC output voltage reference circuit leads to including I2C data
The 2nd foot of letter bus and DAC, DAC are I2C clock signals, and the DATA signal that the 3rd foot of DAC is I2C connects FPGA, and FPGA is defeated
Go out digital reference signal, the 6th pin output analog voltage reference signal of DAC.
In a kind of embodiment of the utility model, the DAC models AD5622BKSZ-2REEL7.
Signal conditioning circuit (is connected) by bleeder circuit by R683 and R685, is taken the voltage that R685 divides to be connected to input and is protected
Protection circuit (uses diode D75 clampers), is connected to hysteresis comparator circuit (by comparator LMV331M5 and resistance R678, R679
Composition), sluggish comparison voltage reference circuit 4 is provided by the output of R678 connection DAC reference circuits.
See Fig. 5, in a kind of embodiment of the utility model, the FPGA models of the adaptive adjustment circuits of DSP
XC7020.The adaptive adjustment circuits of DSP are connected to XC7020 by hysteresis comparator output circuit, and by digital algorithm, (DSP is adaptive
Flow chart should be adjusted) judge rotating speed conditioned signal whether in OK range and control DAC output reference voltage sizes.
See Fig. 6, the adaptive adjustment circuits of DSP include the digital circuit such as Fig. 6, and the 4th of the U126 in hysteresis comparator circuit the
Foot exports square-wave signal and is then adjusted according to the signal automatic decision input signal of input to the input terminal of digital circuit, digital circuit
The whole reference voltage exported to DAC, to achieve the purpose that adaptively to adjust.
A kind of adaptive range rotating speed Opsonizing method is also disclosed in the utility model, includes the following steps：
One signal input adaptive adjustment circuit occurs for S1, signal generating circuit；
S2, carry out first step partial pressure to the signal so that the voltage range that the circuit after partial pressure is handled in hysteresis comparator
It is interior；
S3, use clamp circuit so that being input to the signal of comparator in hysteresis comparator voltage encloses, if beyond
The signal input of the scope, clamp circuit can force clamper within the range；
S4, hysteresis comparator can be compared input signal and DAC output reference voltages, and the AC signal of input is whole
The square-wave signal of formation standard；
S5, FPGA receive square-wave signal, using timer calculate square-wave signal high level time and it is low level when
Between, to calculate the frequency of the square wave, to achieve the purpose that to measure key phase model；
If S6, FPGA only recognize high level, it will judge that key signal maximum is smaller than key signal, will pass through
The digital signal that the output of I2C buses reduces level-one is given to DAC, and the analog of DAC output reduction level-ones comes and enter key
Phase signals contrast, untill FPGA can recognize high level and low level in normal square wave；
If S7, FPGA only recognize low level, it will judge that the minimum value of key signal is bigger than reference signal, Jiu Huitong
Cross the output of I2C buses and put forward higher leveled digital signal to DAC, DAC, which is exported, carries higher leveled simulation ginseng ON signal and enter key
Phase signals contrast, and untill FPGA can recognize high level and low level in normal square wave, reach adaptive with this
The target of rotating speed conditioning.
Compared to the content introduced in background technology, the utility model is joined due to introducing 12BIT DAC outputs as comparator
Examine, 1/4096. introducing hysteresis comparator can be reached so that tach signal rising edge is kept away with trailing edge threshold value difference by comparing precision
Zero-cross comparator error is exempted from, due to only adapting to adjustment algorithm using DSP numerals.System can the optimal comparative level of Automatic-searching with
Tach signal is contrasted, and avoids manual regulation stall.The adaptive rotating speed modulate circuit has circuit connection succinctly, no zero passage
Error, degree of regulation is high, the remarkable advantages such as digital adaptation is adjusted.
The above is only the preferred embodiment of the utility model, rather than its limitations；It should be pointed out that although with reference to upper
Each embodiment is stated the utility model is described in detail, it will be understood by those of ordinary skill in the art that, it still can be with
Modify to the technical solution described in the various embodiments described above, or which part or all technical characteristic are equally replaced
Change；And these modifications and replacement, the essence of corresponding technical solution is departed from various embodiments of the utility model technical solution
Scope.
Claims (7)
1. adaptive range rotating speed modulate circuit, it is characterised in that including signal generating circuit, circuit for signal conditioning, DAC outputs
Reference circuits and DSP digital adaptation adjustment circuits：
The signal generating circuit is connected to signal conditioning circuit input terminal, and the signal conditioning circuit is by resistance by partial pressure electricity
Road, input protection circuit and hysteresis comparator circuit composition, the partial pressure that bleeder circuit obtains are connected to input protection circuit, Jin Erlian
The negative-going signal input terminal for the comparator circuit being connected in hysteresis comparator circuit；Hysteresis comparator circuit inputs the negative terminal of comparator
The anode voltage reference signal of signal and comparator is contrasted, and then hysteresis comparator is electric greatly for negative terminal signal voltage Amplitude Ration anode
Road exports low level signal, otherwise exports high level signal；The adaptive adjustment circuits of DSP are realized by programmable FPGA device, are somebody's turn to do
Circuit includes clock signal input all the way, one group of 12BIT digital signals output, and signal input detecting circuit all the way, by FPGA
Neglect the DAC digital input ends of 12BIT digital signals access；DAC output terminal output reference voltages, DAC output voltage is with reference to electricity
The forward signal input terminal of comparator circuit in road connection hysteresis comparator circuit, provides sluggish more electric for hysteresis comparator circuit
Pressure reference；Clock reference circuit inputs to FPGA all the way, and clock reference is provided to digital circuit；Hysteresis comparator circuit exports all the way
Square-wave signal, is connected to FPGA signals input detecting circuit.
2. adaptive range rotating speed modulate circuit according to claim 1, it is characterised in that the signal generating circuit with
The voltage signal output speed signal of approach switch sensor generation；
Approach switch sensor signal circuit includes：24V voltage source circuits are connected to probe power supply port all the way, sensing
Device signal output port, current loop and port are provided for power supply with reference to 0 current potential.
3. adaptive range rotating speed modulate circuit according to claim 1, it is characterised in that the signal conditioning circuit
Bleeder circuit include 1 foot of resistance R683 and resistance R685, R683 and be connected to the signal output port of signal generating circuit,
1 foot of the 2 feet connection R685 of R683,2 feet of R685 are connected to 0V；Input protection circuit includes 1 foot of double diode D75, D75
0V is connected to, 2 feet are connected to power supply, and 3 feet are connected to 1 foot of R685；Hysteresis comparator circuit includes voltage-stablizer U126, resistance
R684, R678, R679, R680,1 foot of the 1 foot connection R685 of R684,2 feet of R684 are connected to 3 feet of U126,1 foot of U126
Connect 2 feet of R678, the 1 foot connection reference voltage of R678,2 feet of the 1 foot connection R678 of R679, the 2 feet connection U126 of R679
4 feet composition hysteresis comparator circuit.
4. adaptive range rotating speed modulate circuit according to claim 3, it is characterised in that the comparator chip model
For LMV331M5.
5. adaptive range rotating speed modulate circuit according to claim 1, it is characterised in that the DAC output voltage ginseng
It is I2C clock signals to examine circuit to include I2C data communication bus and the 2nd foot of DAC, DAC, and the 3rd foot of DAC is the DATA of I2C
Signal connects FPGA, FPGA output digital reference signals, the 6th pin output analog voltage reference signal of DAC.
6. adaptive range rotating speed modulate circuit according to claim 5, it is characterised in that the DAC models
AD5622BKSZ-2REEL7。
7. adaptive range rotating speed modulate circuit according to claim 1, it is characterised in that the DSP is adaptively adjusted
The FPGA models XC7020 of circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720772083.5U CN207352481U (en) | 2017-06-29 | 2017-06-29 | Adaptive range rotating speed modulate circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720772083.5U CN207352481U (en) | 2017-06-29 | 2017-06-29 | Adaptive range rotating speed modulate circuit |
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| CN207352481U true CN207352481U (en) | 2018-05-11 |
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| CN201720772083.5U Withdrawn - After Issue CN207352481U (en) | 2017-06-29 | 2017-06-29 | Adaptive range rotating speed modulate circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107632633A (en) * | 2017-06-29 | 2018-01-26 | 深圳前海慧联科技发展有限公司 | A kind of adaptive range rotating speed modulate circuit and Opsonizing method |
| CN109738015A (en) * | 2019-01-11 | 2019-05-10 | 清华大学 | Signal processing apparatus |
-
2017
- 2017-06-29 CN CN201720772083.5U patent/CN207352481U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107632633A (en) * | 2017-06-29 | 2018-01-26 | 深圳前海慧联科技发展有限公司 | A kind of adaptive range rotating speed modulate circuit and Opsonizing method |
| CN107632633B (en) * | 2017-06-29 | 2019-01-08 | 深圳前海慧联科技发展有限公司 | A kind of adaptive range revolving speed conditioning circuit and Opsonizing method |
| CN109738015A (en) * | 2019-01-11 | 2019-05-10 | 清华大学 | Signal processing apparatus |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CB03 | Change of inventor or designer information |
Inventor after: Zheng Feihong Inventor after: Cao Lei Inventor after: Li Guimin Inventor before: Zheng Feihong |
|
| CB03 | Change of inventor or designer information | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20180511 Effective date of abandoning: 20190108 |
|
| AV01 | Patent right actively abandoned |