The content of the invention
Power supply is trimmed it cannot be guaranteed that the time of output rising edge of a pulse is less than 100ns for existing, it is impossible to tool is effectively ensured
The integrated circuit for having polysilicon fuse disposably trims success, and this trims the low level voltage of power supply output, high level electricity
Pressure, the width of pulse and frequency are not easy to regulation, so that the technical problem for bringing extra production cost is produced to integrated circuit,
The present invention provides a kind of new nanosecond rising edge pulse power supply.
To achieve these goals, the present invention is adopted the following technical scheme that:
A kind of nanosecond rising edge pulse power supply, including instruction generation unit, communication unit, central control unit, NMOS
Driver element, NMOS tube, diode, pulse output unit, 5~15V of DC adjustable elements and DC 1.2~5V adjustable elements;Its
In,
Generation unit is instructed, is produced for controlling the control signal of NMOS tube break-make to instruct;
Communication unit, receives the control signal instruction from instruction generation unit, and control signal instruction is compiled
Code, produces the control signal code stream that can be recognized by central control unit;
Central control unit, receives the control signal code stream from communication unit, and according to internal algorithm parsing control letter
The concrete meaning of number stream, produces corresponding pulse control signal;
NMOS driver elements, receive the pulse control signal that central control unit is sent, when pulse control signal is high electricity
The first driving voltage is usually produced, the second driving voltage is produced when pulse control signal is low level;
NMOS tube, receives the first driving voltage from NMOS driver elements and turns on, and makes diode operation in cut-off shape
State, it is the voltage that DC5~15V adjustable elements are exported to control pulse output unit output high level voltage;And
Receive the second driving voltage from NMOS driver elements and turn off, make diode operation in conducting state, control
Pulse output unit output low level voltage is the voltage that 1.2~5V of DC adjustable elements are exported.
In the nanosecond rising edge pulse power supply that the present invention is provided, include NMOS tube, the NMOS tube ensure that pulse
The pulse voltage rising time of power supply output is less than 100ns, so as to be effectively ensured to the integrated circuit of polysilicon fuse
Success rate is once trimmed, and the pulse width and pulse frequency of pulse power output can be by central control units
Algorithms are adjusted, meanwhile, the high-level DC voltage and low-level DC voltage of pulse power output pulse can roots
The characteristics of factually border trims integrated circuit carries out a range of regulation, and then optimizes integrated circuit and trim device, so that
Reduce the production cost of high-precision integrated circuit.
Further, the instruction generation unit is PC, embedded device or board.
Further, the communication unit is RS-232 interface, RS-485 interfaces, RS-422 interfaces or USB interface.
Further, the central control unit is single-chip microcomputer, ARM, CPLD or FPGA.
Further, internal algorithm parsing module is provided with the central control unit, the internal algorithm parsing module is used
In the concrete meaning of parsing control signal code stream, corresponding pulse control signal is produced.
Further, the MOSFET grids for the model MAX627 that the NMOS driver elements are produced from U.S.'s Maxim
Driver.
Further, the N-channel field effect transistor for the model IRF7413 that the NMOS tube is produced from IR companies of the U.S.
Pipe.
Further, the pulse output unit is a SMA adapter connector.
Further, 1.2~5V of DC adjustable elements include the first low pressure difference linear voltage regulator, the first potentiometer, first
Inductor, the first capacitor and the second capacitor, adjustable side and the first potentiometer of first low pressure difference linear voltage regulator
One end is connected, the other end ground connection of the first potentiometer, output end and the first inductor of first low pressure difference linear voltage regulator
One end and the first capacitor one end connection, the sun of one end and diode of the other end of the first inductor and the second capacitor
Pole is connected, and the other end of the other end of the first capacitor and the second capacitor is connected and is grounded.
Further, 5~15V of DC adjustable elements include the second low pressure difference linear voltage regulator, the second potentiometer, second
Inductor, the 3rd capacitor and the 4th capacitor, adjustable side and the second potentiometer of second low pressure difference linear voltage regulator
One end is connected, the other end ground connection of the second potentiometer, output end and the second inductor of second low pressure difference linear voltage regulator
One end and the 4th capacitor one end connection, the leakage of one end and NMOS tube of the other end of the second inductor and the 3rd capacitor
Pole is connected, and the other end of the 3rd capacitor and the other end of the 4th capacitor are connected and be grounded.
Embodiment
In order that technological means, creation characteristic, reached purpose and effect that the present invention is realized are easy to understand, tie below
Conjunction is specifically illustrating, and the present invention is expanded on further.
It refer to shown in Fig. 1, the present invention provides a kind of nanosecond rising edge pulse power supply, including instructs generation unit 1, leads to
Interrogating unit 2, central control unit 3, NMOS driver elements 4, NMOS tube 5, diode 6, pulse output unit 7,5~15V of DC can
Adjust unit 8 and 1.2~5V of DC adjustable elements 9;Wherein,
Generation unit 1 is instructed, is produced for controlling the control signal of NMOS tube break-make to instruct;
Communication unit 2, receives the control signal instruction from instruction generation unit 1, and instruct progress to the control signal
Coding, produces the control signal code stream that can be recognized by central control unit 3;
Central control unit 3, receives the control signal code stream from communication unit 2, and parse control according to internal algorithm
The concrete meaning of signal code stream, produces corresponding pulse control signal;
NMOS driver elements 4, receive the pulse control signal that central control unit 3 is sent, when pulse control signal is height
The first driving voltage is produced during level, the second driving voltage is produced when pulse control signal is low level;
NMOS tube 5, receives the first driving voltage from NMOS driver elements 4 and turns on, diode 6 is operated in cut-off
State, it is the voltage that 5~15V of DC adjustable elements 8 are exported to control the output high level voltage of pulse output unit 7;And
Receive the second driving voltage from NMOS driver elements 4 and turn off, diode 6 is operated in conducting state, control
The output of pulse output unit 7 low level voltage processed is the voltage that 1.2~5V of DC adjustable elements 9 are exported.
In the nanosecond rising edge pulse power supply that the present invention is provided, include NMOS tube, the NMOS tube ensure that pulse
The pulse voltage rising time of power supply output is less than 100ns, so as to be effectively ensured to the integrated circuit of polysilicon fuse
Success rate is once trimmed, and the pulse width and pulse frequency of pulse power output can be by central control units
Algorithms are adjusted, meanwhile, the high-level DC voltage and low-level DC voltage of pulse power output pulse can roots
The characteristics of factually border trims integrated circuit carries out a range of regulation, and then optimizes integrated circuit and trim device, so that
Reduce the production cost of high-precision integrated circuit.
As specific embodiment, circuit theory diagrams of the invention are as shown in Fig. 2 the instruction generation unit 1, communication unit
2nd, central control unit 3 and NMOS driver elements 4 are linked in sequence successively, output end and the NMOS tube 5 of the NMOS driver elements 4
Grid be attached, drain electrode and 5~15V of the DC adjustable elements 8 of the NMOS tube 5 are attached, the source of the NMOS tube 5
Level and the negative electrode and pulse output unit 7 of diode 6 are attached, anode and the adjustable lists of 1.2~5V of DC of the diode 6
Member 9 is attached.
As specific embodiment, the instruction generation unit 1 is PC, embedded device or board, is produced for controlling
The control signal instruction of the break-make of NMOS tube 5;Preferably, the instruction generation unit 1 is PC, and the PC is individual calculus
Machine, can be attached by the RS-232 cables of standard with the communication unit 2.
As specific embodiment, the communication unit 2 connects for RS-232 interface, RS-485 interfaces, RS-422 interfaces or USB
Mouthful;Preferably, the communication unit 2 is rs-232 standard serial communication interface, specifically can be public from U.S.'s U.S.'s letter (MAXIM)
Take charge of the model MAX232 single supply electrical level transferring chips of production.
As specific embodiment, the central control unit 3 is single-chip microcomputer, ARM, CPLD (Complex
Programmable Logic Device, CPLD) or FPGA (Field-Programmable Gate
Array, field programmable gate array);Preferably, the central control unit 3 is single-chip microcomputer, can specifically select the U.S.
The model Atmega128 of atmel corp's production single-chip microcomputer, the single-chip microcomputer has programmable serial USART interfaces, can compiled
The EEPROM of In-System Programmable Flash and the 4k byte of journey I/O interfaces and 128k bytes, supports jtag interface programming;Its
In, the communication unit 2 and central control unit 3 can be attached by the serial USART interfaces, by may be programmed I/
The input of NMOS driver elements 4 can be attached by O Interface with central control unit 3.
As specific embodiment, internal algorithm parsing module, the internal algorithm solution are provided with the central control unit 3
Analysis module is used for the concrete meaning for parsing control signal code stream, produces corresponding pulse control signal;The internal algorithm is
The method of byte-by-byte parsing communications protocol, the specific process of analysis of internal algorithm parsing module refer to shown in Fig. 3.Specifically
Ground, the byte transmission of data is about set to asynchronous communication, and baud rate is 9600,1 start bit, and 8 data bit, 1 bit check position is (strange
Verification), 1 stop position.Communications protocol content is as follows:
Parameter setting data Frame Protocol form:
ADDR |
CTRL |
LNG |
FREQ_H |
FREQ_L |
HDC_H |
HDC_L |
CRC-1 |
CRC-2 |
EXT |
SF |
Output control command frame protocol format:
The meaning of the byte representation of each in protocol format is as follows:
ADDR:The address of the pulse power is represented, scope is 00H-1FH.
CTRL:Represent to send command type, 01H is parameter setting data frame, and 02H is output control command frame.
LNG:Represent the length of parameter byte.
FREQ_H:Represent the high byte of the pulse frequency of pulse power output.
FREQ_L:Represent the low byte of the pulse frequency of pulse power output.
HDC_H:Represent the pulse positive pulse width high byte of pulse power output.
HDC_L:Represent the pulse positive pulse width low byte of pulse power output.
Parameter setting data frame is verified using the CRC-16 of standard, and calculating is terminated to HDC_L bytes since ADDR bytes
Crc value, is initialized as zero.
CRC-1:The low byte of CRC-16 verifications.
CRC_2:The high byte of CRC-16 verifications.
EXT and SF:The end of data frame is represented, EXT is 06H, and SF is FFH.
Process of analysis figure shown in Fig. 3 is the process of analysis of internal algorithm parsing module, when central control unit is received
After recognizable control signal code stream, internal algorithm starts, and starts to receive the first byte data ADDR, judges the first byte data
Whether the machine address is equal to, if unequal just terminate internal algorithm flow;If equal, the second byte data is continued to
CTRL.Then the command type of the second byte representation is judged, when for 02H, it is output control command frame to represent the order, then sends out
Output control signal is sent, then terminates internal algorithm flow;When for 01H, then the number that follow-up length is LNG bytes is received successively
According to, then successively receive data CRC-1 and CRC-2, and data frame end byte EXT and SF, then with standard
CRC-16 verifications provides to calculate the crc value for receiving data according to agreement, and the low byte of crc value that calculates of judgement whether with
The CRC-1 values received in data are identical, and whether the high byte of crc value is identical with receiving the value of the CRC-2 in data, if
Differ, then terminate internal algorithm flow;If high byte and low byte are all identical, pulse frequency parameter and Zheng Mai are extracted
Width parameter is rushed, and gives pulse control signal variable, central control unit can just produce corresponding according to the parameter information of renewal
Pulse control signal, then internal algorithm terminate.
As specific embodiment, the NMOS driver elements 4 are a kind of MOSFET gate drivers, specifically can be from U.S.
The model MAX627 of state's Maxim production MOSFET gate drivers.
The model IRF7413 produced as specific embodiment, the NMOS tube 5 from IR companies of the U.S. N-channel
Effect transistor, the transistor is in the case where VGS is 5V, and conducting resistance maximum is 0.018 Ω, and it is 13A to continue drain current;
VDS is 15V, and drain electrode follow current is under conditions of 7.3A, turn on delay time representative value is 8.6ns, rise time representative value
For 50ns, turn-off delay time representative value is 52ns, and fall time representative value is 46ns.Wherein, the pulse voltage of the pulse power
Rising time mainly determines by the turn on delay time of NMOS tube and rise time, and the turn on delay time of the NMOS tube+
Rise time is less than 100ns, therefore the pulse voltage rising time of the nanosecond rising edge pulse power supply of the invention provided can
Ensure to be less than 100ns.
As specific embodiment, the diode 6, due to one-way conduction, when the NMOS tube 5 is turned on, institute
The voltage of pulse output unit 7 is stated higher than 1.2~5V of DC adjustable elements output voltages, i.e., the positive terminal voltage of described diode 6
Less than negative terminal voltage, the diode 6 ends, and the output high level voltage of pulse output unit 7 can for the 5~15V of DC
The voltage for adjusting unit 8 to export;When the NMOS tube 5 is turned off, the voltage of pulse output unit 7 is less than the 1.2~5V of DC
Adjustable elements output voltage, i.e., the positive terminal voltage of described diode 6 is higher than negative terminal voltage, and the diode 6 is turned on, the pulse
The output low level voltage of output unit 7 is the voltage that 1.2~5V of DC adjustable elements 9 are exported.Thus, the diode 6 can
To remain that the pulse output unit 7 exports low level voltage as DC 1.2-5V adjustable elements output voltages.
As specific embodiment, the pulse output unit 7 is a SMA adapter connector, one kind that the present invention is provided
Nanosecond rising edge pulse power supply is attached by the joint and load.
As specific embodiment, it refer to shown in Fig. 2,1.2~5V of DC adjustable elements 9 include the first low voltage difference line
Property voltage-stablizer (LDO) U1, the first potentiometer R1, the first inductor L1, the first capacitor C1 and the second capacitor C2, described first
Low pressure difference linear voltage regulator U1 adjustable side is connected with the first potentiometer R1 one end, the first potentiometer R1 other end ground connection
GND, the output end of the first low pressure difference linear voltage regulator U1 and the first inductor L1 one end and the one of the first capacitor C1
End connection, the first inductor L1 other end is connected with the second capacitor C2 one end and the anode of diode 6, the first capacitor
The C1 other end and the second capacitor C2 other end connect and are grounded GND.In the present embodiment, the first capacitor C1,
First inductor L1 and the second capacitor C2 constitute pi type filter, while can be come by adjusting the first potentiometer R1 resistance
Change the DC voltage of 1.2~5V of DC adjustable elements output.
As specific embodiment, it refer to shown in Fig. 2,5~15V of DC adjustable elements 8 include the second low pressure difference linearity
Voltage-stablizer (LDO) U2, the second potentiometer R2, the second inductor L2, the 3rd capacitor C3 and the 4th capacitor C4, described second is low
Pressure difference linear voltage regulator U2 adjustable side is connected with the second potentiometer R2 one end, the second potentiometer R2 other end ground connection GND,
The output end of the second low pressure difference linear voltage regulator U2 connects with the second inductor L2 one end and the 4th capacitor C4 one end
Connect, the second inductor L2 other end is connected with the drain electrode of the 3rd capacitor C3 one end and NMOS tube 5, the 3rd capacitor C3's
The other end and the 4th capacitor the C4 other end connect and are grounded GND.In the present embodiment, the 3rd capacitor C3, second
Inductor L2 and the 4th capacitor C4 constitute pi type filter, while can be by adjusting the second potentiometer R2 resistance, to change
The DC voltage of 5~15V of DC adjustable elements output.
The output test curve for the nanosecond rising edge pulse power supply that the present invention is provided is as shown in figure 4, the figure shows negative
The pulse curve of output captured during for 1000mA by Agilent oscillograph is carried, pulse can be seen that by the test curve
Output high-level DC voltage is 10.95V, and pulse output low-level DC voltage is 3.33V, and pulse output rising time is
30ns (is less than 100ns).
Embodiments of the present invention are these are only, are not intended to limit the scope of the invention, it is every to utilize the present invention
The equivalent structure that specification and accompanying drawing content are made, is directly or indirectly used in other related technical fields, similarly at this
Within the scope of patent protection of invention.