CN112165240B

CN112165240B - Nanosecond high-voltage pulse switch driving circuit

Info

Publication number: CN112165240B
Application number: CN202010878276.5A
Authority: CN
Inventors: 裴崇雷; 金东东; 纪春恒; 孙磊
Original assignee: Shandong Institute of Space Electronic Technology
Current assignee: Shandong Institute of Space Electronic Technology
Priority date: 2020-08-27
Filing date: 2020-08-27
Publication date: 2022-05-13
Anticipated expiration: 2040-08-27
Also published as: CN112165240A

Abstract

The invention discloses a nanosecond high-voltage pulse switch driving circuit, and provides a nanosecond high-speed pulse voltage driving circuit to realize nanosecond high-speed shutter control in detector flight time gating. The nanosecond high-voltage pulse switch driving circuit comprises a signal edge latch extraction circuit, a positive-negative high-voltage conversion circuit (comprising a-200V conversion circuit and a +50V conversion circuit), a control signal reverse enhancement circuit and an MOSFET switch circuit.

Description

Nanosecond high-voltage pulse switch driving circuit

Technical Field

The invention relates to a nanosecond high-voltage pulse switch driving circuit for controlling an image intensifier, belonging to the field of integrated circuit design.

Background

With the rapid development of domestic microelectronic and chip process design technologies, the application range of high-speed high-frequency systems is more and more extensive. The range-gated laser imaging is an active imaging technology, and the high-speed on-off state of a detector is controlled by calculating the flight time of photons, so that the attenuation effect of a medium on light is effectively reduced, the back scattering noise is shielded, and the imaging of a long-distance target under complex environmental conditions such as rain, fog or underwater is realized.

In the prior art, the switching state of the detector is usually realized by using a high-speed gating pulse control circuit. At present, the range gate imaging control field needs to carry out nanosecond-level shutter control on a detector, and the shutter switch of the detector is realized by positive and negative high-voltage pulses of a front-end photocathode, which are generally +50V and-200 pulse signals, so that nanosecond-level high-voltage pulse driving is needed.

The pulse width of the existing high-speed gating circuit is up to hundred nanoseconds, the repetition frequency is dozens of kHz, and the requirement of the control precision can not be met obviously. In addition, the existing high-speed gating circuit has the defects of slow triggering edge, long delay time and the like, and cannot meet the nanosecond triggering technical requirement of the detector.

In view of this, the present patent application is specifically proposed.

Disclosure of Invention

The application discloses a nanosecond high-voltage pulse switch driving circuit, which aims to solve the problems in the prior art and provides the nanosecond high-speed pulse voltage driving circuit so as to realize nanosecond high-speed shutter control in detector flight time gating.

In order to achieve the design purpose, the nanosecond-level high-voltage pulse switch driving circuit comprises a signal edge latching and extracting circuit, a positive-negative high-voltage conversion circuit (comprising a-200V conversion circuit and a +50V conversion circuit), a control signal reverse enhancement circuit and an MOSFET switch circuit.

The signal edge latch extraction circuit is used for extracting the pulse width of an input signal, namely, an input TTL signal is subjected to edge extraction by selecting a high-speed trigger logic device (the input signal can be nanosecond-level in the narrowest pulse width). The trigger collects and latches the rising edge and the falling edge of the input signal, and the rising edge and the falling edge are processed by the logic circuit to obtain positive and negative pulse signals with equal input signal width time difference to be used as a trigger signal and a control signal of the back-end circuit. Meanwhile, the partial circuit also plays a role in isolating and denoising signals.

The positive and negative high voltage switching circuit is used for carrying out following control, positive and negative pulse signals with a certain time difference are used as clock signals and control signals of a following control chip, and two paths of pulse signals with certain width are obtained after passing through the processor. Meanwhile, the pulse signals have certain driving capability, and the time difference between the rising edge and the falling edge of the two paths of pulses is still kept as the pulse width of the input TTL signals.

The control signal reverse enhancement circuit adopts a plurality of high-speed inverters to carry out edge acquisition on two paths of pulse signals with certain width so as to obtain a plurality of paths of pulse signals. The driving capability of the output signal is improved, and meanwhile, the purpose of quick edge triggering is achieved.

The MOSFET switch circuit selects a high-speed MOSFET switch tube. Under the control of the driving signal, the MOSFET switching tube can realize nanosecond on-off operation, and finally outputs nanosecond positive and negative high-voltage pulse signals.

In summary, the nanosecond high-voltage pulse switch driving circuit described in the present application has the following advantages:

1. the method can be applied to high-speed and high-frequency systems such as laser radar flight time gating control and the like, the shutter control achieves a nanosecond level, the control precision is high, the response speed is high, and output signals are in the nanosecond level on both the rising edge and the falling edge;

2. the TTL signal can be input according to any pulse width, and positive and negative high-voltage pulses with any pulse width can be output simultaneously;

3. the method has the characteristic of low time delay, and the output inherent time delay is not more than 50 nanoseconds;

4. the response frequency range is large, the highest input signal frequency can reach 300kHz, and the narrowest pulse width can reach 3 nanoseconds.

Drawings

The following drawings are illustrative of specific embodiments of the present application.

FIG. 1 is a block diagram of a nanosecond high voltage pulse switch driver circuit as described herein;

fig. 2 is a control timing diagram of the nanosecond high-voltage pulse switch driving circuit;

FIG. 3 is a signal edge latch extraction circuit diagram of a nanosecond high-voltage pulse switch driver circuit;

FIG. 4 is a circuit diagram of positive and negative high voltage switching of a nanosecond high voltage pulse switch driver circuit;

FIG. 5 is a reverse boost circuit diagram of a nanosecond high voltage pulse switch driver circuit;

FIG. 6 is a MOSFET switch circuit diagram of a nanosecond high voltage pulse switch driver circuit;

fig. 7 is a waveform diagram of a measured signal to which the driving circuit of the present invention is applied.

Detailed Description

Embodiments of the present application are further described below with reference to the accompanying drawings.

Embodiment 1, as shown in fig. 1, a nanosecond-level high-voltage pulse switch driving circuit according to the present application includes a signal edge latch extraction circuit, a positive-negative high-voltage conversion circuit (including two parts, a-200V conversion circuit and a +50V conversion circuit), a control signal reverse enhancement circuit, and a MOSFET switch circuit.

As shown in fig. 3, in the signal edge latch and extraction circuit, one end of each of the capacitor C1, the resistor R1, the resistor R2, the resistor R3 and the resistor R4 is connected to the TTL input signal and the 9 end of the flip-flop U2, and the other end of each of the above components is connected to the GND end; one end of the capacitor C2 is connected with the 10 end of the trigger U2 and +5VCC, and the other end is connected with a GND end; one end of the resistor R10 is connected with the

ends

11, 12 and 13 of the trigger U2, the other end of the resistor R10 is connected with the ends 3 of the capacitor C11 and the trigger U5, and the other end of the capacitor C11 is connected with the GND end; the

ends

1 and 14 of the trigger U2 are connected with +5VCC, and the end 7 is connected with the GND end; the resistor R10, the resistor R7, the resistor R8 and the positive end of the diode D14 are connected with the 6 end of the trigger U2, the other end of the resistor R10 is a control B end, the other end of the resistor R7 is connected with the negative end of the diode D14 and the diode C5, the other end of the capacitor C5 is connected with a GND end, and the other end of the resistor R8 is connected with the base electrode of the triode M11; the emitter of the triode M11 is connected with +5VCC, and the collector is the control A end; one end of the capacitor C3 and the 2, 4, 13 and 14 ends of the trigger U3 are connected to +5VCC, and the other end is connected to a GND end; a capacitor C4, a resistor R5 and the negative end of a diode D12 are connected with the 10 end of a trigger U3, the other end of the capacitor C4 is connected with a GND end, the other end of the resistor R5 is connected with the positive end of the diode D12 and the 3 end and the 9 end of the trigger U3, the 7 end of the trigger U3 is connected with the GND end, the 1 end and the 6 end of the trigger U3 are connected with the 12 end of the trigger U2, and the 11 end of the trigger U3 is connected with the 2 end and the 8 end of the trigger U2; the negative end of the resistor R9 and the negative end of the diode D13 are connected with the 3 end, the 4 end and the 5 end of the trigger U2 and the 2 end of the trigger U5, and the other end of the resistor R9, the positive end of the diode D13 and the capacitor C6 are connected with the 3 end of the trigger U4; the other end of the capacitor C6 is connected with a GND end, one end of the capacitor C7 is connected with the 2 end, the 4 end, the 10 end, the 12 end and the 14 end of the trigger U4 to +5VCC, and the other end of the capacitor C7 is connected with the GND end; one end of the capacitor C8 is connected with GND, and the other end of the capacitor C8 is connected with the 1 end and the 6 end of the trigger U4 to form a signal SIG _ B end; one end of the capacitor C9 is connected with GND, and the other end of the capacitor C9 is connected with the 8 end, the 11 end and the 13 end of the trigger U4; the 9 end of the trigger U4 is a signal SIG _ A end, and the 7 end of the trigger U4 is connected with a GND end; one end of the capacitor C12 is connected with the 4 end and the 5 end of the trigger U5, and the other end of the capacitor C12 is connected with the GND end; one end of the capacitor C10 and the

ends

1, 10, 12 and 14 of the trigger U5 are connected to +5VCC, and the other end is connected to a GND end; one end of the capacitor C13 is connected with a GND end, and the other end of the capacitor C13 is connected with the 8 end, the 11 end and the 13 end of the trigger U5 to form a signal SIG _ C end; the 7 terminal of the flip-flop U5 is connected to the GND terminal, and the 6 terminal of the flip-flop U5 is the SIG _ D terminal.

As shown in fig. 4, the positive and negative high voltage converting circuit uses the positive and negative pulse signals as the clock signal and control signal of the following control chip, and the pulse width is determined by the pF stage pull-down capacitor of the processor. the-200V conversion circuit at the lower part of the figure comprises a capacitor C19, a resistor R16 and a power supply conversion module U10. One end of the capacitor C19 is connected with the ends 22 and 23 of the power conversion module U10 to the +12V power supply end, one end of the resistor R16 is connected with the ends 16 and 17 of the power conversion module U10, the other end of the resistor R16 is connected with the end 15 of the power conversion module U10 to the end 200V output end, the end 8 and the end 9 of the power conversion module U10 are connected, and the

ends

2, 3, 12 and 13 of the power conversion module U10 are connected with the GND end. The +50V conversion circuit at the upper part of the figure comprises a capacitor C18, a resistor R15 and a voltage conversion module U9. One end of the capacitor C18 and the ends 22 and 23 of the voltage conversion module U9 are connected to a +12V power supply end, one end of the resistor R15 is connected to the end 16 of the voltage conversion module U9, the other end of the resistor R15 and the

ends

8, 10, 15 and 17 of the voltage conversion module U9 are connected to a GND end, the ends 2 and 3 of the voltage conversion module U9 are connected to a GND end, and the end 13 of the voltage conversion module U9 is an end outputting + 50V.

As shown in fig. 5, the control signal reverse enhancement circuit adopts 4 high-speed inverters to perform edge acquisition on two paths of pulse signals with a certain width to obtain 4 paths of pulse signals, namely, a reverse a, a reverse B, a reverse C and a reverse D (see fig. 3). The 6 logic gates of each phase inverter are connected together to serve as a 6-in-one phase inverter, so that the driving capability of output signals can be improved, and the purpose of fastest edge triggering can be realized. Specifically, one end of the capacitor C21 is connected to the GND terminal, and the other end is connected to the +7VDC terminal together with the 14 terminal of the inverter U12; the 1 end, the 3 end, the 5 end, the 9 end, the 11 end and the 13 end of the inverter U12 are connected with the input signal SIG _ A end, and the 2 end, the 4 end, the 6 end, the 8 end, the 10 end and the 12 end of the inverter U12 are connected with the output end in a reverse direction A; one end of the capacitor C22 is connected with the GND terminal, and the other end of the capacitor C22 and the 14 terminal of the inverter U13 are connected to the +7VDC terminal; the 1 end, the 3 end, the 5 end, the 9 end, the 11 end and the 13 end of the inverter U13 are connected with the input signal SIG _ B end, and the 2 end, the 4 end, the 6 end, the 8 end, the 10 end and the 12 end of the inverter U13 are reversely connected with the output end B; one end of the capacitor C23 is connected with the GND terminal, and the other end of the capacitor C23 and the 14 terminal of the inverter U14 are connected to the +7VDC terminal; the 1 end, the 3 end, the 5 end, the 9 end, the 11 end and the 13 end of the inverter U14 are connected with the input signal SIG _ C end, and the 2 end, the 4 end, the 6 end, the 8 end, the 10 end and the 12 end of the inverter U14 are reversely connected with the output end C; one end of the capacitor C24 is connected with the GND terminal, and the other end of the capacitor C24 and the 14 terminal of the inverter U15 are connected to the +7VDC terminal; the 1, 3, 5, 9, 11 and 13 terminals of the inverter U15 are connected to the input signal SIG _ D terminal, and the 2, 4, 6, 8, 10 and 12 terminals of the inverter U15 are connected to the output terminal in the reverse direction D.

As shown in fig. 6, the MOSFET switch circuit employs a high-speed MOSFET switch tube to implement nanosecond on-off operation under the control of a driving signal. Wherein reverse a and reverse B drive control the MOSFET switch state of +50V and reverse C and reverse D drive control the MOSFET switch state of-200V. Specifically, one end of the capacitor C26 is connected to the input inverting terminal a, and the other end is connected to the resistor R20 and the base of the switching tube M15; the other end of the resistor R20 is connected with the positive end of the capacitor C20 and the emitter of the switch tube M15 to the +50V end; the negative end of the capacitor C27 is connected with a GND end, the collector of the switch tube M15 and the collector of the switch tube M19 are connected with one end of the capacitor C28, the base of the switch tube M19 is connected with an input reverse B end, the emitter of the switch tube M19 is connected with the GND end, and the other end of the capacitor C28 is connected with the collector of the switch tube M16 and the base of the switch tube M17; the base electrode of the switch tube M16 is connected with the control end A, and the emitter electrode of the switch tube M16 is connected with the +50V end; the collector of the switch tube M17 and the collector of the switch tube M14 are connected to the output SMA end, the positive ends of a capacitor C29, a resistor R21 and a voltage regulator tube KZ6 are connected with the emitter of the switch tube M17, the other end of the capacitor C29 and the other end of the resistor R21 are connected to the GND end, and the negative end of the voltage regulator tube KZ6 is connected with the +50V end; one end of the capacitor C30 is connected with the input reverse C end, and the other end of the capacitor C30 is connected with the resistor R22 and the base electrode of the switch tube M18; the other end of the resistor R22 is connected with the positive end of the capacitor C31 and the emitter of the switch tube M18 to the +50V end, the negative end of the capacitor C31 is connected with the GND end, and the collector of the switch tube M18 and the collector of the switch tube M12 are connected with one end of the capacitor C32; the base electrode of the switch tube M12 is connected with the input reverse D end, the emitter electrode of the switch tube M12 is connected with the GND end, the other end of the capacitor C32 is connected with the collector electrode of the switch tube M13 and the base electrode of the switch tube M14, the other end of the capacitor C32 is connected with the collector electrode of the switch tube M13 and the base electrode of the switch tube M14, the base electrode of the switch tube M13 is connected with the input control B end, and the emitter electrode of the switch tube M13 is connected with the-200V end; the negative end of a resistor R23, a capacitor C33 and a voltage regulator tube KZ5 is connected with the emitter of a switch tube M14, the other end of a resistor R23 is connected with the other end of a capacitor C33 to form a GND end, and the positive end of the voltage regulator tube KZ5 is connected with a-200V end.

Based on the application of the nanosecond high-voltage pulse switch driving circuit, the application also provides the following nanosecond high-voltage pulse switch driving method, which comprises the following implementation steps:

1. input signal edge latch extraction

As shown in fig. 2, the input TTL signal has a period T0 and a variable pulse width, which is illustrated as a0 and a1 and an amplitude of 5V. As shown in fig. 3, when a nanosecond TTL signal is input, the dual-path high-speed flip-flop U2 collects edge information of a TTL input signal, and latches a rising edge and a falling edge of the signal by the high-speed latch U3, after buffering by the U2, the rising edge is used to drive the switching tube M11 to obtain a control a signal for increasing a +50V output switching level, and the falling edge is buffered by the R6 to obtain a control B for pulling down a switching level of-200V output. Meanwhile, the U4 and the U5 flip-flops convert edge information of a signal acquired by the U2 into weak driving signals SIG _ A, SIG _ B, SIG _ C and SIG _ D respectively, wherein the SIG _ A and the SIG _ B are reversely enhanced to be used for driving and controlling the on-off of a +50V MOSFET switching tube M17, and the SIG _ C and the SIG _ D are reversely enhanced to be used for driving and controlling the on-off of a-200V MOSFET switching tube M14.

2. Signal following and enhancement

SIG _ A and SIG _ B are a pair of positive and negative spikes, SIG _ C and SIG _ D are a pair of positive and negative spikes, and in FIG. 2, the time difference between the two pairs of spikes, i.e., the signal, follows the width of pulse a0, the width of the spikes being determined by Cx in FIG. 1. In fig. 3, the capacitor C9 and the capacitor C13 are typically 22pF capacitors to ground. SIG _ A, SIG _ B, SIG _ C and SIG _ D are weak in driving capability and are respectively subjected to reverse processing through inverters U12, U13, U14 and U15, six single inverters are connected in parallel to enhance reverse driving capability, and reverse A, reverse B, reverse C and reverse D signals in the diagram of fig. 5 are obtained respectively and are used for driving a rear-end MOSFET nanosecond switching circuit.

3. High voltage switching and MOSFET switch on-off

As shown in fig. 4, a voltage of +12V is input, and is converted into +50V by the high voltage module U9, and is converted into-200V by the high voltage module U10, and the two paths of high voltages of +50V and-200V provide voltage references for high voltage output, as shown in fig. 6. The driving signal reversely controls the switch tube M15 to be switched on by A, reversely controls the switch tube M19 to be switched off and switched off by B, simultaneously controls the switch tube M16 to be switched on and pull up the starting voltage of the MOSFET switch tube M17, the switch tube M17 to be switched on and output +50V, simultaneously controls the switch tube M18 to be switched off by C and the switch tube M12 to be switched on by D, thereby forming a discharge loop, controls the switch tube B to pull up the starting voltage of the MOSFET switch tube M14, switches the switch tube M14 to be switched off and switched off, and stops output at-200V; similarly, M15 and M16 are controlled to be turned off, M19 is controlled to be turned on, M17 is controlled to be turned off, +50V stops outputting, M18 and M13 are controlled to be turned on, M12 is controlled to be turned off, M14 is controlled to be turned on, and-200V is output.

4. Positive and negative high voltage pulse formation

In fig. 6, the MOSFET switch transistors M17 and M14 for controlling the +50V and-200V high voltage outputs are a PN pair type nanosecond high-speed switch transistor, and exhibit an alternate conduction state. The reverse A, the reverse B and the control A jointly control the M17 to be switched on, meanwhile, the reverse C, the reverse D and the control B jointly control the M14 to be switched off, and the nanosecond output signal ns _ signal outputs a +50V high-voltage pulse; the reverse A, the reverse B and the control A jointly control the M17 to be turned off, meanwhile, the reverse C, the reverse D and the control B jointly control the M14 to be turned on, the nanosecond output signal ns _ signal outputs-200V high-voltage pulses, the PN pair type MOSFET tubes M17 and M14 are periodically and alternately turned on, positive and negative high-voltage pulse output signals ns _ signal of +50V and-200V are formed, the pulse width of the output signal ns _ signal and the pulse width of the input signal are kept consistent to be a0, the period is kept consistent to be T0, and B0 is inherent processing delay of a circuit, as shown in a control timing diagram of FIG. 2.

As shown in fig. 7, the detector adopts a micro photo diode MCP as a nanosecond electronic switching gate, a voltage of-200V is input to ensure that the micro photo diode MCP is completely turned on, effective distance gated imaging is performed, and a voltage of +50V is input to ensure that the MCP electronic switching gate is strictly turned off. As shown in fig. 3, when the positive and negative high voltage pulses are output, the MOSFET switch tube and the high voltage conversion output module are turned on simultaneously. The +50V and +200V voltages are obtained by converting two input +12V high-voltage modules, the conversion output is controlled by two control ends, wherein the A end is controlled to control the conversion output of the +50V high-voltage module, and the B end is controlled to control the conversion output of the-200V high-voltage module. And the MOSFET tube with the voltage of +50V and-200V and the control end are alternately opened and closed, and positive and negative high-voltage pulse output is formed.

In summary, the embodiments presented in connection with the figures are only preferred. Those skilled in the art can derive other alternative structures according to the design concept of the present invention, and the alternative structures should also fall within the scope of the solution of the present invention.

Claims

1. A nanosecond-level high-voltage pulse switch driving circuit is characterized in that: the device comprises a signal edge latching and extracting circuit, a positive and negative high-voltage conversion circuit, a control signal reverse enhancement circuit and an MOSFET switch circuit;

the signal edge latching extraction circuit is used for extracting the pulse width of an input signal, a high-speed trigger logic device is selected for carrying out edge extraction on the input TTL signal, and the narrowest pulse width of the input signal is nanosecond;

the positive and negative high voltage conversion circuit is used for carrying out following control, and positive and negative pulse signals with a certain time difference are used as clock signals and control signals of the following control chip;

the control signal reverse enhancement circuit adopts a plurality of high-speed inverters to carry out edge acquisition on two paths of pulse signals with certain width so as to obtain a plurality of paths of pulse signals;

the MOSFET switching circuit selects a high-speed MOSFET switching tube, and the MOSFET switching tube realizes nanosecond on-off operation under the control of a driving signal so as to output nanosecond positive and negative high-voltage pulse signals;

in the signal edge latch extraction circuit, one ends of a capacitor C1, a resistor R1, a resistor R2, a resistor R3 and a resistor R4 are all connected with a TTL input signal and the 9 end of a trigger U2, and the other ends of the capacitor C1, the resistor R1, the resistor R2, the resistor R3 and the resistor R4 are all connected with a GND end; one end of the capacitor C2 is connected with the 10 end of the trigger U2 and +5VCC, and the other end is connected with a GND end; one end of the resistor R10 is connected with the ends 11, 12 and 13 of the trigger U2, the other end of the resistor R10 is connected with the ends 3 of the capacitor C11 and the trigger U5, and the other end of the capacitor C11 is connected with the GND end; the ends 1 and 14 of the trigger U2 are connected with +5VCC, and the end 7 is connected with the GND end; the resistor R6, the resistor R7, the resistor R8 and the positive end of the diode D14 are connected with the 6 end of the trigger U2, the other end of the resistor R6 is a control B end, the other end of the resistor R7 is connected with the negative end of the diode D14 and the capacitor C5, the other end of the capacitor C5 is connected with a GND end, and the other end of the resistor R8 is connected with the base electrode of the triode M11; the emitter of the triode M11 is connected with +5VCC, and the collector is the control A end; one end of the capacitor C3 and the 2, 4, 13 and 14 ends of the trigger U3 are connected to +5VCC, and the other end is connected to a GND end; a capacitor C4, a resistor R5 and the negative end of a diode D12 are connected with the 10 end of a trigger U3, the other end of the capacitor C4 is connected with a GND end, the other end of the resistor R5 is connected with the positive end of the diode D12 and the 3 end and the 9 end of the trigger U3, the 7 end of the trigger U3 is connected with the GND end, the 1 end and the 6 end of the trigger U3 are connected with the 12 end of the trigger U2, and the 11 end of the trigger U3 is connected with the 2 end and the 8 end of the trigger U2; the negative end of the resistor R9 and the negative end of the diode D13 are connected with the 3 end, the 4 end and the 5 end of the trigger U2 and the 2 end of the trigger U5, and the other end of the resistor R9, the positive end of the diode D13 and the capacitor C6 are connected with the 3 end of the trigger U4; the other end of the capacitor C6 is connected with a GND end, one end of the capacitor C7 and the 2, 4, 10, 12 and 14 ends of the trigger U4 are connected to +5VCC, and the other end of the capacitor C7 is connected with the GND end; one end of the capacitor C8 is connected with GND, and the other end of the capacitor C8 is connected with the 1 end and the 6 end of the trigger U4 to form a signal SIG _ B end; one end of the capacitor C9 is connected with GND, and the other end of the capacitor C9 is connected with the 8 end, the 11 end and the 13 end of the trigger U4; the 9 end of the trigger U4 is a signal SIG _ A end, and the 7 end of the trigger U4 is connected with a GND end; one end of the capacitor C12 is connected with the 4 end and the 5 end of the trigger U5, and the other end of the capacitor C12 is connected with the GND end; one end of the capacitor C10 and the ends 1, 10, 12 and 14 of the trigger U5 are connected to +5VCC, and the other end is connected to a GND end; one end of the capacitor C13 is connected with a GND end, and the other end of the capacitor C13 is connected with the 8 end, the 11 end and the 13 end of the trigger U5 to form a signal SIG _ C end; the 7 end of the trigger U5 is connected with the GND end, and the 6 end of the trigger U5 is the signal SIG _ D end;

the cycle of inputting a TTL signal is T0, the pulse width is variable, when a nanosecond TTL signal is input, a double-circuit high-speed trigger U2 collects edge information of the TTL input signal, a high-speed latch U3 latches the rising edge and the falling edge of the signal, after the rising edge is buffered by U2, the rising edge is used for driving a switch tube M11 to obtain a control A signal which is used for boosting a +50V output switch level, and the falling edge is buffered by R6 to obtain a control B which is used for pulling down the switch level output by-200V; meanwhile, the edge information of the signal acquired by the U2 is converted into weak driving signals SIG _ A, SIG _ B, SIG _ C and SIG _ D by the U4 and U5 triggers respectively, wherein SIG _ A and SIG _ B are used for driving and controlling the on-off of a +50V MOSFET switching tube M17 after being reversely enhanced, and SIG _ C and SIG _ D are used for driving and controlling the on-off of a-200V MOSFET switching tube M14 after being reversely enhanced;

in the positive and negative high-voltage conversion circuit, one end of a capacitor C19 is connected with the ends 22 and 23 of a power conversion module U10 to be connected with a +12V power supply end, one end of a resistor R16 is connected with the ends 16 and 17 of a power conversion module U10, the other end of a resistor R16 is connected with the end 15 of a power conversion module U10 to be connected with an end 200V output end, the end 8 of the power conversion module U10 is connected with the end 9, and the ends 2, 3, 12 and 13 of the power conversion module U10 are connected with a GND end; one end of the capacitor C18 and the ends 22 and 23 of the voltage conversion module U9 are connected to a +12V power supply end, one end of the resistor R15 is connected to the end 16 of the voltage conversion module U9, the other end of the resistor R15 and the ends 8, 10, 15 and 17 of the voltage conversion module U9 are connected to a GND end, the ends 2 and 3 of the voltage conversion module U9 are connected to the GND end, and the end 13 of the voltage conversion module U9 is an end outputting + 50V;

in the control signal reverse enhancement circuit, one end of a capacitor C21 is connected with a GND end, and the other end of the capacitor C21 and the 14 end of an inverter U12 are connected to a +7VDC end; the 1 end, the 3 end, the 5 end, the 9 end, the 11 end and the 13 end of the inverter U12 are connected with the input signal SIG _ A end, and the 2 end, the 4 end, the 6 end, the 8 end, the 10 end and the 12 end of the inverter U12 are connected with the output end in a reverse direction A; one end of the capacitor C22 is connected with the GND terminal, and the other end of the capacitor C22 and the 14 terminal of the inverter U13 are connected to the +7VDC terminal; the 1 end, the 3 end, the 5 end, the 9 end, the 11 end and the 13 end of the inverter U13 are connected with the input signal SIG _ B end, and the 2 end, the 4 end, the 6 end, the 8 end, the 10 end and the 12 end of the inverter U13 are reversely connected with the output end B; one end of the capacitor C23 is connected with the GND terminal, and the other end of the capacitor C23 and the 14 terminal of the inverter U14 are connected to the +7VDC terminal; the 1 end, the 3 end, the 5 end, the 9 end, the 11 end and the 13 end of the inverter U14 are connected with the input signal SIG _ C end, and the 2 end, the 4 end, the 6 end, the 8 end, the 10 end and the 12 end of the inverter U14 are reversely connected with the output end C; one end of the capacitor C24 is connected with the GND terminal, and the other end of the capacitor C24 and the 14 terminal of the inverter U15 are connected to the +7VDC terminal; the 1 end, the 3 end, the 5 end, the 9 end, the 11 end and the 13 end of the inverter U15 are connected with an input signal SIG _ D end, and the 2 end, the 4 end, the 6 end, the 8 end, the 10 end and the 12 end of the inverter U15 are reversely connected with an output end D;

in the MOSFET switch circuit, one end of a capacitor C26 is connected with the input reverse A end, and the other end of the capacitor C26 is connected with a resistor R20 and the base electrode of a switch tube M15; the other end of the resistor R20 is connected with the positive end of the capacitor C27 and the emitter of the switch tube M15 to the +50V end; the negative end of the capacitor C27 is connected with a GND end, the collector of the switch tube M15 and the collector of the switch tube M19 are connected with one end of the capacitor C28, the base of the switch tube M19 is connected with an input reverse B end, the emitter of the switch tube M19 is connected with the GND end, and the other end of the capacitor C28 is connected with the collector of the switch tube M16 and the base of the switch tube M17; the base electrode of the switch tube M16 is connected with the control end A, and the emitter electrode of the switch tube M16 is connected with the +50V end; the collector of a switch tube M17 and the collector of a switch tube M14 are connected to an output SMA end, the positive ends of a capacitor C29, a resistor R21 and a voltage-regulator tube KZ6 are connected with the emitter of the switch tube M17, the other end of the capacitor C29 and the other end of the resistor R21 are connected to a GND end, and the negative end of the voltage-regulator tube KZ6 is connected with a +50V end; one end of the capacitor C30 is connected with the input reverse C end, and the other end of the capacitor C30 is connected with the resistor R22 and the base electrode of the switch tube M18; the other end of the resistor R22 is connected with the positive end of the capacitor C31 and the emitter of the switch tube M18 to the +50V end, the negative end of the capacitor C31 is connected with the GND end, and the collector of the switch tube M18 and the collector of the switch tube M12 are connected with one end of the capacitor C32; the base electrode of the switching tube M12 is connected with the input reverse D end, the emitter electrode of the switching tube M12 is connected with the GND end, the other end of the capacitor C32 is connected with the collector electrode of the switching tube M13 and the base electrode of the switching tube M14, the other end of the capacitor C32 is connected with the collector electrode of the switching tube M13 and the base electrode of the switching tube M14, the base electrode of the switching tube M13 is connected with the input control B end, and the emitter electrode of the switching tube M13 is connected with the-200V end; the negative end of a resistor R23, a capacitor C33 and a voltage regulator tube KZ5 is connected with the emitter of a switch tube M14, the other end of a resistor R23 and the other end of a capacitor C33 are connected to a GND end, and the positive end of the voltage regulator tube KZ5 is connected with a-200V end.