CN111338414B - Low-power consumption monostable circuit capable of being triggered repeatedly - Google Patents
Low-power consumption monostable circuit capable of being triggered repeatedly Download PDFInfo
- Publication number
- CN111338414B CN111338414B CN202010158133.7A CN202010158133A CN111338414B CN 111338414 B CN111338414 B CN 111338414B CN 202010158133 A CN202010158133 A CN 202010158133A CN 111338414 B CN111338414 B CN 111338414B
- Authority
- CN
- China
- Prior art keywords
- circuit
- electrically connected
- input end
- gate
- output end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Logic Circuits (AREA)
Abstract
The invention provides a low-power consumption monostable circuit capable of being triggered repeatedly, which comprises: the circuit comprises a first logic circuit, a second logic circuit, an RC circuit, a switch circuit, a bias circuit and a threshold circuit; the output end of the first logic circuit is electrically connected with the input end of the RC circuit, the output end of the RC circuit is electrically connected with the input end of the second logic circuit, the second output end of the second logic circuit is electrically connected with the input end of the switch circuit, the output end of the switch circuit is electrically connected with the input end of the bias circuit, the output end of the bias circuit is electrically connected with the input end of the threshold circuit, the first output end of the second logic circuit is electrically connected with the input end of the threshold circuit, the output end of the threshold circuit is electrically connected with the input end of the second logic circuit, and the input end of the first logic circuit is used for receiving an enable signal and a trigger signal.
Description
Technical Field
The invention relates to a monostable circuit, in particular to a low-power consumption monostable circuit capable of being triggered repeatedly.
Background
In the existing monostable circuit, in order to obtain longer monostable time, a larger capacitance resistor is adopted in specific design, and two implementation modes are generally adopted in the traditional design, wherein one mode is an off-chip external RC mode matched with an internal comparison module, and the other mode is a mode that a resistance capacitor is integrated on a chip and matched with the internal comparison module. The former needs to increase pin, and PCB design also can increase cost in addition, and the consumption also can not be very little, and the latter because manufacturing process, temperature, mains voltage, output signal monostable time can produce great change, and the area is bigger moreover, also can increase certain area cost.
Disclosure of Invention
The invention discloses a low-power consumption monostable circuit capable of being triggered repeatedly, and aims to provide a monostable circuit which is small in area, low in power consumption and stable in monostable time.
The embodiment of the invention provides a low-power consumption monostable circuit capable of being triggered repeatedly, which is characterized by comprising the following components: the circuit comprises a first logic circuit, a second logic circuit, an RC circuit, a switch circuit, a bias circuit and a threshold circuit;
the output end of the first logic circuit is electrically connected with the input end of the RC circuit, the output end of the RC circuit is electrically connected with the input end of the second logic circuit, the second output end of the second logic circuit is electrically connected with the input end of the switch circuit, the output end of the switch circuit is electrically connected with the input end of the bias circuit, the output end of the bias circuit is electrically connected with the input end of the threshold circuit, the first output end of the second logic circuit is electrically connected with the input end of the threshold circuit, the output end of the threshold circuit is electrically connected with the input end of the second logic circuit, and the input end of the first logic circuit is used for receiving an enable signal and a trigger signal.
Preferably, the first logic circuit includes: the circuit comprises a first buffer, a delayer, a first inverter, a first NOR gate and an AND gate;
the input end of the first buffer is used for receiving the trigger signal, the output end of the first buffer is electrically connected with the input end of the delayer, the output end of the delayer is electrically connected with the input end of the first phase inverter, the output end of the first phase inverter is electrically connected with the first end input end of the first nor gate, the second input end of the nor gate is electrically connected with the output end of the first buffer, the output end of the nor gate is electrically connected with the first input end of the and gate, the second input end of the and gate is used for receiving the enable signal, and the output end of the and gate is electrically connected with the input end of the RC circuit.
Preferably, the second logic circuit includes: a second nor gate second inverter;
the first input end of the second NOR gate is electrically connected with the output end of the RC circuit, the second input end of the NOR gate is electrically connected with the output end of the threshold circuit, the output end of the second NOR gate is electrically connected with the input end of the second phase inverter, and the output end of the second phase inverter is electrically connected with the input end of the switch circuit.
Preferably, the method further comprises the following steps: a reset circuit;
and the output end of the second NOR gate is electrically connected with the input end of the threshold circuit through the reset circuit.
Preferably, the reset circuit includes: a first capacitor and a first field effect transistor;
the first end of the first capacitor is electrically connected with the output end of the second NOR gate, the second end of the first capacitor is electrically connected with the first input end of the threshold circuit, the output end of the second NOR gate is electrically connected with the second input end of the threshold circuit, the grid electrode of the first field effect transistor is electrically connected with the output end of the RC circuit, the drain electrode of the first field effect transistor is electrically connected with the second end of the first capacitor, and the drain electrode of the first field effect transistor is grounded.
Preferably, the threshold circuit includes: an auxiliary loop and a comparison loop;
the first input end of the comparison loop is electrically connected with the output end of the bias circuit, the second input end of the comparison loop is used for receiving a reference voltage, the input end of the auxiliary loop is electrically connected with the second end of the first capacitor, the auxiliary loop is arranged on the output end of the comparison loop, the input end of the auxiliary loop is electrically connected with the output end of the second NOR gate, and the output end of the auxiliary loop is electrically connected with the second input end of the second NOR gate.
Preferably, the comparison circuit comprises: a third logic circuit, a flip circuit, a feedback circuit and a latch circuit;
the input end of the latch circuit, the first input end of the flip circuit and the input end of the feedback circuit are electrically connected with the output end of the second NOR gate, the second input end of the flip circuit is electrically connected with the second end of the first capacitor, the output end of the latch circuit, the output end of the flip circuit and the output end of the feedback circuit are electrically connected with the input end of a third logic circuit, and the output end of the third logic circuit is electrically connected with the second input end of the second NOR gate.
Preferably, the latch circuit includes: a third inverter and a second field effect transistor;
the output end of the second NOR gate is electrically connected with the grid electrode of the second field effect transistor through the third phase inverter, the source electrode of the second field effect transistor is used for being connected with a power supply, and the drain electrode of the second field effect transistor is electrically connected with the input end of the third logic circuit.
Preferably, the roll-over circuit comprises: the resistor, the second capacitor, the third field effect transistor, the fourth field effect transistor and the fifth field effect transistor;
the first end of the second capacitor is connected to a power supply through the resistor, the second end of the second capacitor is electrically connected with the output end of the second NOR gate, the first end of the second capacitor is electrically connected with the grid electrode of the third field effect transistor, the source electrode of the third field effect transistor is used for being connected with the power supply, the drain electrode of the third field effect transistor is electrically connected with the drain electrode of the fourth field, the source electrode of the fourth field effect transistor is grounded, the grid electrode of the fourth field effect transistor is electrically connected with the second end of the first capacitor, the grid electrode of the fifth field effect transistor is electrically connected with the source electrode of the fourth field effect transistor, the drain electrode of the fifth field effect transistor is electrically connected with the input end of the third logic circuit, and the source electrode of the fifth field effect transistor is grounded.
Preferably, the feedback circuit comprises a sixth field effect transistor and a seventh field effect transistor, and the third logic circuit comprises a fourth inverter and a second buffer;
the source electrode of the sixth field effect transistor is connected with a power supply, the grid electrode of the sixth field effect transistor is electrically connected with the output end of the second NOR gate, the drain electrode of the sixth field effect transistor is electrically connected with the source electrode of the seventh field effect transistor, the drain electrode of the seventh field effect transistor is electrically connected with the input end of the fourth phase inverter, the output end of the fourth phase inverter is electrically connected with the second input end of the second NOR gate through the second buffer, and the output end of the fourth phase inverter is electrically connected with the grid electrode of the seventh field effect transistor.
Based on the low-power consumption monostable circuit capable of being triggered repeatedly provided by the invention, a first logic circuit receives an enable signal and a trigger signal to generate a short pulse to an RC circuit and a second logic circuit, the pulse is directly output to vin2 of a threshold circuit from a first path of an NOR gate of the second logic circuit, the second path of the pulse is output to vin of the threshold circuit through a first capacitor, the third path of the pulse is output to a switch circuit through a second inverter to enable a bias circuit to enter a bias state, the bias circuit provides bias current for the threshold circuit and charges the first capacitor to a reference voltage to enable the output of the threshold circuit to be pulled down, the bias circuit stops working, the whole circuit is in a 0-power consumption state and locks the high level of vin, meanwhile, the damage of the threshold circuit caused by the rapid rise of the first capacitor is prevented, and the consistency of monostable time is ensured through a reset circuit, the stability of the monostable time of the monostable circuit and low power consumption are ensured.
Drawings
FIG. 1 is a schematic diagram of a top-level circuit structure of a low-power consumption monostable circuit capable of repeatedly triggering according to the present invention;
FIG. 2 is a schematic diagram of a threshold circuit structure provided by the present invention;
FIG. 3 is a schematic diagram of an input waveform of a threshold circuit provided by the present invention;
FIG. 4 is a schematic diagram of the input and output of the overall waveform of a low-power consumption monostable with repetitive triggering according to the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
The following detailed description of specific embodiments of the invention refers to the accompanying drawings.
The invention discloses a low-power consumption monostable circuit capable of being triggered repeatedly, and aims to provide a monostable circuit which is small in area, low in power consumption and stable in monostable time.
Referring to fig. 1, an embodiment of the invention provides a low-power consumption monostable circuit capable of being triggered repeatedly, including: a first logic circuit 1, a second logic circuit 2, an RC circuit 2, a switch circuit 41, a bias circuit 4 and a threshold circuit 5;
the output end of the first logic circuit 1 is electrically connected to the input end of the RC circuit 2, the output end of the RC circuit 2 is electrically connected to the input end of the second logic circuit 2, the second output end of the second logic circuit 2 is electrically connected to the input end of the switch circuit 41, the output end of the switch circuit 41 is electrically connected to the input end of the bias circuit 4, the output end of the bias circuit 4 is electrically connected to the input end of the threshold circuit 5, the first output end of the second logic circuit 2 is electrically connected to the input end of the threshold circuit 5, the output end of the threshold circuit 5 is electrically connected to the input end of the second logic circuit 2, and the input end of the first logic circuit 1 is configured to receive an enable signal and a trigger signal.
It should be noted that, the first logic circuit 1 is configured to receive an enable signal and a trigger signal, generate a short pulse to the RC circuit 2 (configured to filter the short pulse, so as to avoid noise from interfering with a circuit behind the RC circuit) and the second logic circuit 2, after the second logic circuit 2 processes the short pulse, output a signal to the switch circuit 41 and the threshold circuit 5, where the switch circuit 41 receives a high level conduction to make the bias circuit 4 enter a bias state, and charge the reset circuit 6, and when the reset circuit 6 reaches the reference voltage, the threshold circuit 5 outputs an electrical signal to the second logic circuit 2, so that the high level output to the switch circuit 41 is inverted, so that the bias circuit 4 stops working, the circuit is in a zero power consumption state, and the bias circuit 4 locks the high level at the input end of the threshold circuit 5, the stability of the monostable time of the monostable circuit and low power consumption are ensured.
Preferably, the first logic circuit 1 includes: a first buffer 11, a delay 12, a first inverter 13, a first nor gate 14, and an and gate 15;
the input end of the first buffer 11 is configured to receive the trigger signal, the output end of the first buffer 11 is electrically connected to the input end of the delay 12, the output end of the delay 12 is electrically connected to the input end of the first phase inverter 13, the output end of the first phase inverter 13 is electrically connected to the first end input end of the first nor gate 14, the second input end of the nor gate is electrically connected to the output end of the first buffer 11, the output end of the nor gate is electrically connected to the first input end of the and gate 15, the second input end of the and gate 15 is configured to receive the enable signal, and the output end of the and gate 15 is electrically connected to the input end of the RC circuit 2.
In this embodiment, the enable signal is set to high level, and the trigger signal goes into the first buffer 11, the delay 12 and the first inverter 13 in sequence, and the nor gate receives a high or low level due to the first buffer 11. Thus, the output is definitely low, the trigger signal of the input reaches the nor gate all the way through a first buffer 11, so that the inputs of the nor gate of a time is all low, and a high level is output, but the duration of the high level is not long, because the other way of the trigger signal passes through a delay 12 and a first inverter 13 and also reaches a first nor gate 14, so that the nor gate is pulled to a low level. At the output of the first nor gate 14 a short pulse is obtained which, together with the enable input signal, enters the and gate 15, the and gate 15 output likewise being a short pulse which in turn connects a resistor R via a capacitor to ground.
Preferably, the second logic circuit 2 includes: a second nor gate 31 and a second inverter 32;
a first input terminal of the second nor gate 31 is electrically connected to the output terminal of the RC circuit 2, a second input terminal of the second nor gate 31 is electrically connected to the output terminal of the threshold circuit 5, an output terminal of the second nor gate 31 is electrically connected to an input terminal of the second inverter 32, and an output terminal of the second inverter 32 is electrically connected to an input terminal of the switching circuit 41.
In this embodiment, the signal a output from the and gate 15 is led to the second nor gate 31 all the way, so that the o1 signal output from the second nor gate 31 becomes low level at one time, the o1 signal is divided into three ways, one way outputs a high level through the second inverter 32, one way outputs a high level through the first capacitor C1 or vin input to the threshold circuit 5, and the last way directly inputs vin2, vin and vin2 of the threshold circuit 5 through the action of some devices, the output of the threshold circuit 5 is pulled high rapidly, if the speed is faster than the signal a, so that the o1 is kept at low level and the output out is kept at high level, and if the speed is slower than the signal a, the o1 will become high level, the output of the threshold circuit 5 cannot reach high level and the output will return to low level.
Assuming that o1 passes through the threshold circuit 5 and then reaches the nor gate faster than a changes from high to low, the circuit works normally, the second logic circuit 2 outputs high, 411 and 412 of the switch circuit 41 are turned on, the bias circuit 4 enters a normal bias state, the threshold circuit 5 also starts working, the signal at the input vin of the threshold circuit 5 is rc net, a first capacitor C1 is connected with o1 at one end, rc is connected with rc, rc is charged by the current source formed by 44 and 43 of the bias circuit 4 (i.e. the first capacitor C1 is charged), when the charging voltage reaches the reference voltage vref of the threshold circuit 5, the output of the threshold circuit 5 is pulled down, after passing through the second nor gate 31, the signal o1 changes to high, the pulling up of vin and vin2 of the threshold circuit 5 is accelerated, the output out is pulled down, so that the switch circuit 41 is turned on no longer, the bias circuit 4 is not working, and the whole circuit is in a state of quasi-0 power consumption.
The bias circuit 4 is provided with a protection circuit consisting of a tube 42 and a diode D, the tube 42 functions to lock vin to a high level when the output of the second logic circuit 2 goes to a low level (i.e. when the switch circuit 41 is turned off), and functions together with the diode D to prevent the rc network from rising rapidly due to a rapid rise of the o1 signal, so that the voltage of the rc network (i.e. the voltage of the first capacitor C1) rises rapidly, which leads to the rc network rising to a high vdd and causes the input tube of the threshold circuit 5 to be damaged.
Preferably, the method further comprises the following steps: a reset circuit 6;
the output of the second nor gate 31 is electrically connected to the input of the threshold circuit 5 via the reset circuit 6.
Preferably, the reset circuit 6 includes: a first capacitor C1 and a first fet 61;
a first terminal of the first capacitor C1 is electrically connected to the output terminal of the nor gate, a second terminal of the first capacitor C1 is electrically connected to the input terminal of the threshold circuit 5, the output terminal of the nor gate is electrically connected to the input terminal of the threshold circuit 5, the gate of the first fet 61 is electrically connected to the output terminal of the RC circuit 2, the source of the first fet 61 is electrically connected to the second terminal of the first capacitor C1, and the drain of the first fet 61 is grounded.
It should be noted that the trigger signal triggers again to generate a falling edge at a time when we have not completely completed monostable, then the signal a generates a narrow pulse again, the signal a releases the charge on the first capacitor C1 through the first fet 61, when the rc net starts rising again from gnd, which is equivalent to retiming, the first fet 61 also has a function to prevent the first arrival of the trigger and the subsequent other arrivals from generating different monostable times, in the simulation, the initial values of the first trigger and the other triggers of the rc net may not be the same, if each time the first fet 61 can reset, so that the initial values of rc are the same, thus the consistency of monostable times can be ensured.
Preferably, referring to fig. 2, the threshold circuit 5 includes: an auxiliary circuit 7 and a comparison circuit 8;
a first input terminal of the comparison loop 8 is electrically connected to the output terminal of the bias circuit 4, a second input terminal of the comparison loop 8 is configured to receive a reference voltage, a third input terminal of the comparison loop 8 is electrically connected to the second terminal of the first capacitor C1, the auxiliary loop 7 is also on the output terminal of the comparison loop 8, an input terminal of the auxiliary loop 7 is electrically connected to the output terminal of the second nor gate 31, and an output terminal of the auxiliary loop is electrically connected to the second input terminal of the second nor gate 31.
It should be noted that the comparison circuit 8 is an ultra-low power consumption comparator, the output resistor R is very large, the operating speed is very low, and the operating principle is as follows: the reference voltage vref is input at the second input terminal, a signal which increases gradually from gnd is input at the third input terminal vin, and the output is inverted when the signal increases to the magnitude of the reference voltage.
Preferably, said comparison circuit 8 comprises: a third logic circuit 85, a flip circuit 83, a feedback circuit 84, and a latch circuit 81;
an input terminal of the latch circuit 81, a first input terminal of the flip circuit 83, and an input terminal of the feedback circuit 84 are electrically connected to an output terminal of the second nor gate 31, a second input terminal of the flip circuit 83 is electrically connected to a second terminal of the first capacitor C1, an output terminal of the latch circuit 81, an output terminal of the flip circuit 83, and an output terminal of the feedback circuit 84 are electrically connected to an input terminal of a third logic circuit 85, and an output terminal of the third logic circuit 85 is electrically connected to a second input terminal of the second nor gate 31.
Referring to fig. 3 and 4, it should be noted that when vin and vin2 fall simultaneously, the output of the third logic circuit 85 is pulled high rapidly, if the output is not pulled high rapidly, vin and vin2 will be pulled high rapidly due to short trigger pulse, the output will return to low level and not enter monostable normally, so the auxiliary circuit is needed because the comparison loop 8 is a comparator with ultra-low power consumption, the output resistor R is very large, the operation speed is very slow, the bias of the comparison loop 8 is controlled externally, the auxiliary circuit can operate only when the output of the third logic circuit 85 is high level, when the pulse width time of monostable reaches the requirement, the output of the third logic circuit 85 falls, and some gates are pulled high and low rapidly through the positive feedback of the feedback circuit 84, and the power consumption is reduced.
Preferably, the latch circuit 81 includes: a third inverter 811 and a second field effect transistor 812;
the output end of the nor gate is electrically connected to the gate of the second field effect transistor 812 through the third inverter 811, the source of the second field effect transistor 812 is used for connecting a power supply, and the drain of the second field effect transistor 812 is electrically connected to the input end of the third logic circuit 85.
Preferably, the overturning circuit 83 comprises: a resistor R, a second capacitor C2, a third field effect transistor 831, a fourth field effect transistor 832 and a fifth field effect transistor 833;
a first end of the second capacitor C2 is connected to a power supply through the resistor R, a second end of the second capacitor C2 is electrically connected to an output end of the second nor gate 31, a first end of the second capacitor C2 is electrically connected to a gate of the third fet 831, a source of the third fet 831 is used for connecting to the power supply, a drain of the third fet 831 is electrically connected to a drain of the fourth field, a source of the fourth fet 832 is grounded, a gate of the fourth fet 832 is electrically connected to a second end of the first capacitor C1, a gate of the fifth fet 833 is electrically connected to a source of the fourth fet 833, a drain of the fifth fet 833 is electrically connected to an input end of the third logic circuit 85, and a source of the fifth fet 833 is grounded.
Preferably, the feedback circuit 84 includes a sixth fet 841, a seventh fet 842, the third logic circuit 85 includes a fourth inverter 851 and a second buffer 852;
the source of the sixth fet 841 is connected to a power supply, the gate of the sixth fet 841 is electrically connected to the output terminal of the second nor gate 31, the drain of the sixth fet 841 is electrically connected to the source of the seventh fet 842, the drain of the seventh fet 842 is electrically connected to the input terminal of the fourth inverter 851, the output terminal of the fourth inverter 851 is electrically connected to the second input terminal of the second nor gate 31 through the second buffer 852, and the output terminal of the fourth inverter 851 is electrically connected to the gate of the seventh fet 842.
It should be noted that when vin and vin2 drop from vdd to gnd at the same time, vin2 pulls down the gate of third fet 831 through first capacitor C1, and third fet 831 is turned on quickly, so that the gate of fifth fet 833 is pulled high, fifth fet 833 is turned on, and the output of comparison circuit 8 is pulled low forcibly, and the output resistance R of comparison circuit 8 is large, and it is easy to pull down the output. The output of the comparison circuit 8 is pulled high by the fourth inverter 851 and the second buffer 852. When the gate of the third fet 831 is pulled down for a short time, it will be pulled up by the resistor R immediately, but at this time, the output of the third logic circuit is pulled up, the comparison circuit 8 also starts to operate, the gate of the fourth fet 832 has a certain voltage vin, the gate of the fifth fet 833 is pulled down, the fifth fet 833 is turned off, and at this time, the output of the comparison circuit 8 is not acted on by the outside.
vin (i.e. the first capacitor C1) starts to be charged by the current source, the voltage increases linearly, when this voltage reaches the reference voltage vref, the output of the comparison loop 8 flips to become quasi-high, because the output resistance R of the comparison loop 8 is very large, and this rise time is very long, then the output low level is applied to the seventh fet 842 via the fourth inverter 851, since vin2 is now low, the sixth fet 841 is in the on state, so that the output of the comparison loop 8 is further pulled high via a positive feedback, the output of the third logic loop is pulled low, the comparison loop 8 is controlled to be closed by the external control, the output signal of the third logic loop via external signals pulls the inputs vin and vin2 to high level v, vin2 pulls the gate of the second fet 812 to low via the third inverter 811, the second fet 812 is turned on to further lock the output of the comparator circuit 8 to a high level, which is required to lock the output of the comparator circuit 8 since the comparator circuit 8 is already turned off and is no longer operational. Through the determination of the resistor R and the capacitor, the signal of vin2 is coupled to the third fet 831, so that the circuit enters a normal operating state.
Based on the low-power consumption monostable circuit capable of repeatedly triggering provided by the invention, an energy signal and a trigger signal are received by a first logic circuit 1, a short pulse is generated to an RC circuit 2 and a second logic circuit 2, the pulse is directly output to vin2 of a threshold circuit 5 from a first path of an NOR gate of the second logic circuit 2, a second path of the pulse is output to vin of the threshold circuit 5 through a first capacitor C1, a third path of the pulse is output to a switch circuit 41 through a second inverter 32, so that a bias circuit 4 enters a bias state, the bias circuit 4 provides a bias current for the threshold circuit 5 and charges a first capacitor C1 to a reference voltage, so that the output of the threshold circuit 5 is pulled down, the bias circuit 4 stops working, the whole circuit is in a 0-power consumption state, the high level of vin is locked, and the damage of the threshold circuit 5 caused by the rapid rise of the first capacitor C1 is prevented, the consistency of the monostable time is ensured through the reset circuit 6, and the stability and low power consumption of the monostable time of the monostable circuit are ensured.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention.
Claims (7)
1. A retriggerable low power consumption monostable circuit comprising: the circuit comprises a first logic circuit, a second logic circuit, an RC circuit, a switch circuit, a bias circuit and a threshold circuit;
the output end of the first logic circuit is electrically connected with the input end of the RC circuit, the output end of the RC circuit is electrically connected with the input end of the second logic circuit, the second output end of the second logic circuit is electrically connected with the input end of the switch circuit, the output end of the switch circuit is electrically connected with the input end of the bias circuit, the output end of the bias circuit is electrically connected with the first input end of the threshold circuit, the first output end of the second logic circuit is electrically connected with the second input end of the threshold circuit, the output end of the threshold circuit is electrically connected with the input end of the second logic circuit, and the input end of the first logic circuit is used for receiving an enable signal and a trigger signal;
wherein the first logic circuit comprises: the circuit comprises a first buffer, a delayer, a first inverter, a first NOR gate and an AND gate;
the input end of the first buffer is used for receiving the trigger signal, the output end of the first buffer is electrically connected with the input end of the delayer, the output end of the delayer is electrically connected with the input end of the first phase inverter, the output end of the first phase inverter is electrically connected with the first input end of the first nor gate, the second input end of the first nor gate is electrically connected with the output end of the first buffer, the output end of the first nor gate is electrically connected with the first input end of the and gate, the second input end of the and gate is used for receiving the enable signal, and the output end of the and gate is electrically connected with the input end of the RC circuit;
further comprising: a reset circuit;
the output end of a second NOR gate of the second logic circuit is electrically connected with the third input end of the threshold circuit through the reset circuit;
wherein the reset circuit comprises: a first capacitor and a first field effect transistor;
the first end of the first capacitor is electrically connected with the output end of the second NOR gate, the second end of the first capacitor is electrically connected with the first input end of the threshold circuit, the output end of the second NOR gate is electrically connected with the second input end of the threshold circuit, the grid electrode of the first field effect transistor is electrically connected with the output end of the RC circuit, the drain electrode of the first field effect transistor is electrically connected with the second end of the first capacitor, and the source electrode of the first field effect transistor is grounded.
2. The retriggerable low-power consumption monostable according to claim 1, wherein the second logic circuit comprises: a second NOR gate and a second inverter;
the first input end of the second NOR gate is electrically connected with the output end of the RC circuit, the second input end of the second NOR gate is electrically connected with the output end of the threshold circuit, the output end of the second NOR gate is electrically connected with the input end of the second phase inverter, and the output end of the second phase inverter is electrically connected with the input end of the switch circuit.
3. A retriggerable low-power consumption monostable according to claim 2, wherein the threshold circuit comprises: an auxiliary loop and a comparison loop;
the first input end of the comparison loop is electrically connected with the output end of the bias circuit, the second input end of the comparison loop is used for receiving a reference voltage, the first input end of the auxiliary loop is electrically connected with the second end of the first capacitor, the auxiliary loop is arranged on the output end of the comparison loop, the second input end of the auxiliary loop is electrically connected with the output end of the second NOR gate, and the output end of the auxiliary loop is electrically connected with the second input end of the second NOR gate.
4. A retriggerable low-power consumption monostable according to claim 3, wherein the auxiliary loop comprises: a third logic circuit, a flip circuit, a feedback circuit and a latch circuit;
the input end of the latch circuit, the first input end of the flip circuit and the input end of the feedback circuit are electrically connected with the output end of the second NOR gate, the second input end of the flip circuit is electrically connected with the second end of the first capacitor, the output end of the latch circuit, the output end of the flip circuit and the output end of the feedback circuit are electrically connected with the input end of a third logic circuit, and the output end of the third logic circuit is electrically connected with the second input end of the second NOR gate.
5. A retriggerable low-power consumption monostable according to claim 4, wherein the latch circuit includes: a third inverter and a second field effect transistor;
the output end of the second NOR gate is electrically connected with the grid electrode of the second field effect transistor through the third phase inverter, the source electrode of the second field effect transistor is used for being connected with a power supply, and the drain electrode of the second field effect transistor is electrically connected with the input end of the third logic circuit.
6. The retriggerable low-power consumption monostable according to claim 5, wherein the flip loop comprises: the resistor, the second capacitor, the third field effect transistor, the fourth field effect transistor and the fifth field effect transistor;
the first end of the second capacitor is connected to a power supply through the resistor, the second end of the second capacitor is electrically connected with the output end of the second NOR gate, the first end of the second capacitor is electrically connected with the grid electrode of the third field effect transistor, the source electrode of the third field effect transistor is used for being connected with the power supply, the drain electrode of the third field effect transistor is electrically connected with the drain electrode of the fourth field effect transistor, the source electrode of the fourth field effect transistor is grounded, the grid electrode of the fourth field effect transistor is electrically connected with the second end of the first capacitor, the grid electrode of the fifth field effect transistor is electrically connected with the drain electrode of the fourth field effect transistor, the drain electrode of the fifth field effect transistor is electrically connected with the input end of the third logic circuit, and the source electrode of the fifth field effect transistor is grounded.
7. The retriggerable low-power consumption monostable according to claim 5, wherein the feedback circuit includes a sixth fet, a seventh fet, and the third logic circuit includes a fourth inverter and a second buffer;
the source electrode of the sixth field effect transistor is connected with a power supply, the grid electrode of the sixth field effect transistor is electrically connected with the output end of the second NOR gate, the drain electrode of the sixth field effect transistor is electrically connected with the source electrode of the seventh field effect transistor, the drain electrode of the seventh field effect transistor is electrically connected with the input end of the fourth phase inverter, the output end of the fourth phase inverter is electrically connected with the second input end of the second NOR gate through the second buffer, and the output end of the fourth phase inverter is electrically connected with the grid electrode of the seventh field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010158133.7A CN111338414B (en) | 2020-03-09 | 2020-03-09 | Low-power consumption monostable circuit capable of being triggered repeatedly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010158133.7A CN111338414B (en) | 2020-03-09 | 2020-03-09 | Low-power consumption monostable circuit capable of being triggered repeatedly |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111338414A CN111338414A (en) | 2020-06-26 |
| CN111338414B true CN111338414B (en) | 2022-02-11 |
Family
ID=71182289
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010158133.7A Active CN111338414B (en) | 2020-03-09 | 2020-03-09 | Low-power consumption monostable circuit capable of being triggered repeatedly |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111338414B (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0590910A (en) * | 1991-09-27 | 1993-04-09 | Fujitsu Ltd | Monostable multivibrator |
| CN201774508U (en) * | 2010-08-27 | 2011-03-23 | 上海贝岭股份有限公司 | Monostable circuit |
| CN106026982B (en) * | 2016-07-11 | 2018-09-25 | 湖北大学 | A kind of monostable flipflop |
| CN106374886B (en) * | 2016-10-19 | 2023-05-05 | 加驰（厦门）微电子股份有限公司 | Non-repeatable triggering CMOS integrated monostable circuit |
| CN211478984U (en) * | 2020-03-09 | 2020-09-11 | 厦门润积集成电路技术有限公司 | Low-power consumption monostable circuit capable of being triggered repeatedly |
-
2020
- 2020-03-09 CN CN202010158133.7A patent/CN111338414B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN111338414A (en) | 2020-06-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102761322B (en) | Electrification reset circuit and repositioning method thereof | |
| US6181173B1 (en) | Power-on reset circuit | |
| CN103646945A (en) | Integrated circuit power supply esd protection circuit | |
| CN100539417C (en) | Electrify restoration circuit | |
| CN110545095B (en) | Rapid power-down signal detection circuit and power-on reset device for detecting power supply voltage jitter | |
| CN102709883A (en) | Under-voltage protection circuit of switch power source | |
| CN103684374A (en) | Zero or ultra-low dc current consumption power-on and brown-out detector | |
| JPH04253368A (en) | Substrate bias circuit | |
| CN211478984U (en) | Low-power consumption monostable circuit capable of being triggered repeatedly | |
| CN105991119A (en) | Power-on reset circuit | |
| CN101582681B (en) | Power amplifying circuit for eliminating turn-off noise | |
| US10620676B1 (en) | Wake-up control circuit for power-gated integrated circuits | |
| CN111338414B (en) | Low-power consumption monostable circuit capable of being triggered repeatedly | |
| CN110957713A (en) | Electrostatic discharge clamping circuit | |
| CN112134262B (en) | Protection circuit and circuit protection method for power device | |
| EP1034619A1 (en) | Zero power power-on-reset circuit | |
| CN105182833A (en) | Double-power-supply power supply and power-off sequential control device and method | |
| CN212135942U (en) | Buzzer driving circuit with electromagnetic coil detection function | |
| CN106374886B (en) | Non-repeatable triggering CMOS integrated monostable circuit | |
| CN213879789U (en) | Switch holding circuit with high integration level | |
| CN204068684U (en) | For the current foldback circuit of power device | |
| CN114448237A (en) | Direct-current switching power supply and rapid transient response circuit thereof | |
| CN102468839B (en) | Circuit applied to integrated circuit to realize multifunctional pin and method | |
| CN203840306U (en) | Power source start-up reset circuit | |
| CN109522148A (en) | A kind of low-power consumption watchdog circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |