CN106026982B - A kind of monostable flipflop - Google Patents
A kind of monostable flipflop Download PDFInfo
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- CN106026982B CN106026982B CN201610540981.8A CN201610540981A CN106026982B CN 106026982 B CN106026982 B CN 106026982B CN 201610540981 A CN201610540981 A CN 201610540981A CN 106026982 B CN106026982 B CN 106026982B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0232—Monostable circuits
Abstract
The present invention discloses a kind of monostable flipflop, is the monostable flipflop circuit based on phase inverter time delay chain, including substantially monostable trigger module, time-delay reset module；Substantially monostable trigger module is pulsewidth current adjustment monostable trigger circuit；Substantially monostable trigger module and time-delay reset block combiner constitute pulsewidth current adjustment and the monostable trigger circuit of repeatable triggering；Substantially monostable trigger module includes trigger DFF1, time delay chain 1 and time delay chain 2, NAND gate, phase inverter；Time-delay reset module includes trigger DFF2, time delay chain 3 and digital logic gate.Each trigger is the d type flip flop with reset function.Time delay chain, trigger and the digital logic gate that circuit of the present invention is only made of phase inverter are constituted, non-resistance, capacitance, amplifier and comparator, and compatibility standard digital technology and design cycle, easily realize monostable pulsewidth controlled current flow and repeatable triggering, compared to existing monostable flipflop, have many advantages, such as that low cost, low-power consumption, compatibility are strong and versatile.
Description
Technical field
The present invention relates to a kind of monostable flipflops, and in particular to a kind of adjustable pulse width based on time delay chain and repeatable
The monostable flipflop circuit of triggering, can be widely applied in shaping pulse, delay and timing circuit, belong to IC design skill
Art field.
Background technology
Monostable flipflop or triggering timer are for providing triggered by input clock, the fixed pulse letter of pulsewidth
Number, it is mainly used for the fields such as shaping pulse, delay and timing, in communication system, digital display circuit and signal processing system
Extensive application is that modern integrated circuits design indispensable circuit module.
Traditional monostable flipflop is based on capacitance, resistance timing circuit, when applying input trigger signal, using by fixed
When resistance determine charging current charge to timing capacitor, when the voltage at timing capacitor both ends reaches threshold value, comparator
Output change, and then trigger digital trigger or switch so that its state is changed, export positive or negative arteries and veins
Rush signal.Traditional monostable flipflop includes the devices such as passive resistance, capacitance, active comparator, exports the arteries and veins of single steady signal
Width is rushed directly to be determined by the RC time constants of timing resistor, capacitance.
Attached drawing 1 show traditional monostable flipflop schematic diagram based on resistance, capacitance timing, in Fig. 1, when input is touched
When signalling CLK_IN is without input trigger pulse, circuit is in the lock state, and A is logically high, and B is logic low, and M is logic low, N
It is logically high, output single steady signal CLK_OUT remains low.After input signal CLK_IN gets higher namely trigger pulse occurs,
Comparator Comp2Output B become logic low, M points become logically high, and to make N become logic low, CLK_OUT is also mutually strained
It is high；At the same time, since N is logic low, switch S1It will be switched off, power vd D fills timing capacitor C by timing resistor R
Electricity, when capacitance C both end voltages K is more than VREF1When, comparator Comp1Output A is lower, if CLK_IN returns to logic low, B at this time
Also it is logically high, thus M points are lower, N points are got higher, and output CLK_OUT is from newly returning to logic low, after N points are got higher, switch S1It leads
Logical, K points are pulled to logic low, and to make A become logically high, so, A and B are logically high, and latch, which is in, latches shape
State, output CLK_OUT remain low.As can be seen that traditional monostable flipflop output pulse width based on RC timers is：
From the above equation, we can see that：After choosing larger resistance R and capacitance C, traditional monostable flipflop is capable of providing monostable arteries and veins
Wider output pulse, on the contrary then output pulse width narrow.However shortcoming master existing for the traditional monostable flipflop of this kind
It shows：1. used passive resistance and capacitor element area are larger, and need to put using active comparator or operation
Big device, and reference voltage VREF1It needs to be provided by individual voltage generating module, circuit is complicated, and power consumption is higher；2. due to monostable
Pulsewidth is determined by RC, but R, C value can not be by adjusting current adjustment effect in circuit, therefore traditional monostable flipflop can not
Realize the function of monostable pulsewidth current adjustment；3. needing, using devices or modules such as comparator, resistance, capacitances, number can not be passed through
Circuit realize, therefore cannot completely compatible chip digital design flow.
In conclusion a kind of avoidable passive device and comparator larger using resistance and capacitance homalographic or putting
The higher active circuit modules of power consumptions such as big device, while realizing the current adjustment for exporting monostable pulsewidth and repeatable triggering, and it is simultaneous
Holding the monostable flipflop of Design of Digital Circuit flow becomes required.
Invention content
The present invention proposes problem for background technology, designs a kind of monostable flipflop, is based on phase inverter time delay chain
Monostable flipflop circuit, it only includes time delay chain, trigger and the corresponding digital logic gate being made of phase inverter, does not need
Resistance, capacitance, amplifier and comparator, and compatibility standard digital technology and design cycle easily realize monostable pulsewidth controlled current flow
With repeatable triggering, existing monostable flipflop is compared, has many advantages, such as that low cost, low-power consumption, compatibility are strong and versatile.
In order to achieve the above object, the present invention uses following scheme：
A kind of monostable flipflop, it is characterised in that：Including：Substantially monostable trigger module, time-delay reset module；
Substantially the monostable trigger module is the pulsewidth current adjustment monostable trigger circuit based on time delay chain；It is described basic
Monostable trigger module and time-delay reset block combiner constitute the pulsewidth current adjustment based on time delay chain and repeat the monostable of triggering
Flip-flop circuit；
Substantially the monostable trigger module includes：Trigger DFF1, time delay chain 1 and time delay chain 2, NAND gate, phase inverter；
The time-delay reset module includes：Trigger DFF2, time delay chain 3 and digital logic gate；The trigger DFF1 and
Trigger DFF2 is the d type flip flop with reset function；
Substantially in the monostable trigger module, time delay chain 1 is defeated to the trigger DFF1's that is triggered by input trigger signal TR
Go out signal Q and carries out td1Delay, obtains time delayed signal Qd1；The time delay chain 2 is to Qd1Carry out td2Delay, obtains time delayed signal Qd2；
When causing the variation of Q to be transferred to Q by input trigger signal TRd1When, trigger DFF1 is resetted, Q is made to be reset to trigger it
Preceding state, further, when the variation of the Q caused by input trigger signal TR is transferred to Qd2When, reset signal is discharged, to
It is t to obtain monostable pulsewidthd1, triggering recovery time be td2Output single steady signal；The reset signal is by Qd2Inversion signalAnd Qd1NAND operation is carried out to obtain；
In the time-delay reset module, input trigger signal TR is connected to the triggering clock end of trigger DFF2, trigger
The output signal Q of DFF2RSOutput reset signal RST, the reset signal RST prolonging by time delay chain 3 are obtained after reverse phase
When after obtain total delay time be td3Time delayed signal；The time delayed signal is carried out with the trigger DFF1 output signals Q again
AND operation, the low effective reset signal RS_RT as trigger DFF2.
A kind of monostable flipflop as described above, it is characterised in that：The time delay chain 1 or time delay chain 2 include at least two
The delay unit of concatenation, single delay unit include cascade two-stage phase inverter；By the total number or list that change delay unit
The delay value of a delay unit obtains the total delay time of different time delay chains, and then obtains different monostable pulsewidths and trigger extensive
The multiple time.
A kind of monostable flipflop as described above, it is characterised in that：Pass through the biasing to phase inverter in the delay unit
Electric current ICTRLIt is adjusted, realizes the current adjustment of phase inverter delay, and then realize the current adjustment of output single steady signal pulsewidth.
A kind of monostable flipflop as described above, it is characterised in that：Trigger signal TR is inputted within the current monostable period again
It is secondary when triggering, by obtaining Qd1Time delay chain 1 in all delay unit input signals resetted, realize monostable
The repeatable triggering of trigger；
For to Qd1Time delay chain 1 in the reset signal that is resetted of all delay unit input signals generate process
It is：The original input signal of each delay unit in reset signal RST and time delay chain 1 is subjected to AND operation, then by operation
The signal obtained afterwards is connected to each delay unit input terminal in time delay chain 1.
The beneficial effects of the invention are as follows：
Monostable flipflop circuit proposed by the present invention based on time delay chain only include the time delay chain being made of phase inverter and
Corresponding digital logic gate does not need resistance, capacitance, amplifier and comparator, compatibility standard digital technology and design cycle.Easily
Realize monostable pulsewidth current adjustment and repeatable triggering, the bias current of time delay chain need to be only adjusted can realize it is monostable
Pulsewidth current adjustment, need to only be resetted to the input signal of each delay unit can realize repeatable triggering.Compared to
Existing method has many advantages, such as low cost, low-power consumption, compatible strong, pulsewidth current adjustment and repeatable triggering.
Description of the drawings
Fig. 1 is traditional monostable flipflop schematic diagram based on RC timing circuits；
Fig. 2 is the pulsewidth current adjustment monostable flipflop circuit diagram the present invention is based on time delay chain；
Fig. 3 is a kind of monostable flipflop oscillogram of the present invention；
Fig. 4 is basic phase inverter schematic diagram；
Fig. 5 is current-steering phase inverter schematic diagram；
Fig. 6 is that the present invention is based on the pulsewidth current adjustment of time delay chain and repeatable triggering monostable flipflop circuit theories
Figure.
Specific implementation mode
A kind of monostable flipflop specific embodiment of the present invention is described further below in conjunction with attached drawing：
A kind of monostable flipflop of the present invention includes：Substantially monostable trigger module, time-delay reset module；It is described substantially monostable
Trigger module is the pulsewidth current adjustment monostable trigger circuit based on time delay chain；Substantially the monostable trigger module is multiple with delay
Position block combiner constitutes the pulsewidth current adjustment based on time delay chain and the monostable trigger circuit of repeatable triggering.Also it can be explained
For：Using technical solution of the present invention, a kind of pulsewidth current adjustment monostable flipflop based on time delay chain, another party both may make up
Face, by substantially monostable trigger module and time-delay reset block combiner, also may make up the pulsewidth current adjustment based on time delay chain and
The monostable flipflop of repeatable triggering.Two embodiments are divided to illustrate respectively below：
Embodiment one：Pulsewidth current adjustment monostable flipflop based on time delay chain
Referring to attached drawing 2, the pulsewidth current adjustment monostable flipflop proposed by the present invention based on time delay chain, is substantially monostable
Trigger module, including：One d type flip flop DFF1 with reset function, a NAND gate, a phase inverter and two are based on
The time delay chain (time delay chain 1 and time delay chain 2) of phase inverter does not include any resistance, capacitance, amplifier and comparator.With tradition list
Steady state trigger is different using RC charge timings, and the basic principle of the novel monostable flipflop is to utilize two time delay chains to D
The output signal Q of trigger DFF1 carries out td1(td1+td2) delay, respectively obtain two time delayed signal Qd1And Qd2, then pass through
To Qd1And Qd2Carry out logical operation obtain d type flip flop DFF1 reset signal RS, RS reset signal will to d type flip flop DFF1 into
Row resets, and is Q to obtain pulsewidthd1Be delayed between Q (namely td1) output monostable pulses.
The concrete principle of pulsewidth current adjustment monostable flipflop based on time delay chain shown in Fig. 2 is as follows：
D type flip flop and entire monostable flipflop are triggered by the rising edge (or failing edge) of input trigger signal TR.
In order to obtain the reset signal of d type flip flop, output Q delay t of the time delay chain 1 to d type flip flopd1Obtain Qd1Signal, time delay chain 2 are right
Qd1Be delayed td2Obtain Qd2Signal.Then, to Qd2Reverse phase is carried out to obtainQd1WithNAND operation is further carried out to obtain
Obtain reset signal RS.Fig. 3 is to correspond to TR signal waveforms, other each point Q, Q in circuit described in Fig. 2d1、Qd2, RS oscillogram,
As seen from Figure 3, when d type flip flop is that rising edge triggers, after trigger signal TR is got higher, Q is got higher immediately, and Qd1By td1
It just gets higher afterwards, using td2Afterwards, Qd2It gets higher, at this point, the output RS of NAND gate is lower, to make d type flip flop reset and Q is made to become
It is low.RS is continuously the low time as td2, then, RS is got higher, if TR rising edges arrive again, circuit repeats the above steps.Cause
This width that can be seen that number monostable flipflop output pulse is td1, currently trigger and terminate simultaneously to cross td2After time, electricity
It road can be with retriggered namely recovery time for td2, ICTRLIt is bias current.
In Fig. 2, time delay chain 1 or time delay chain 2 include at least two concatenation delay units, and single delay unit includes cascade
The schematic diagram of two-stage phase inverter, phase inverter is as shown in Figure 4.The adjustment of entire time delay chain delay time can be single by changing delay
The number of member changes the transmission delay value (that is, transmission delay value of phase inverter) of each delay unit to realize.If passing through
Electric current adjustment is carried out to the transmission delay of phase inverter, that is, uses current-steering phase inverter as shown in Figure 5, the current-steering
The monostable flipflop of phase inverter is, it can be achieved that the monostable pulsewidth current adjustment of the output of trigger, exports monostable pulsewidth and biased electrical
Flow ICTRLRelationship be：
In formula 1, K is the constant for being proportional to CVDD, and C is all parasitic capacitances of phase inverter output node OUT, td0For
Basic phase inverter (namely ICTRLFor infinity when) delay, N1Include the number of delay unit by time delay chain 1.
Embodiment two：Pulsewidth current adjustment based on time delay chain and the monostable flipflop of repeatable triggering
Referring to attached drawing 2 and attached drawing 6, resetted by the input signal to each delay unit in time delay chain in Fig. 21,
I.e. by Fig. 2 and time-delay reset block combiner, the present invention proposes that technical solution is exactly：Pulsewidth current adjustment based on time delay chain and can
The monostable flipflop of repeated trigger.In Fig. 6, for generating the time-delay reset module of negative pulse delayed reset signal RST still
It is only constituted by the d type flip flop DFF2 with reset, phase inverter, with the digital logic gates such as door and time delay chain 3, in normal condition namely nothing
When repeated trigger, trigger DFF2 output signals QRSSignal be reset to it is low, output RST signal be height, do not influence monostable trigger
Device circuit；And when the current monostable period not yet terminate and when occurring input triggering once more namely when repeated trigger occurs, QRSIt is vertical
Become high, output RST signal is low.By td3Afterwards, RS_RT also becomes low, thus by QRSBe reset to it is low, output RST again
Become high, is t this makes it possible to obtain the negative pulse durationd3Delayed reset signal RST.
In conjunction with the embodiments one and attached drawing 6, the monostable of the pulsewidth current adjustment based on time delay chain and repeatable triggering is touched
The principle of hair device is described as follows：
When within the existing monostable period input trigger signal occur again trigger signal along when, time-delay reset module will generate
Pulsewidth is the delay of time delay chain 3 td3Negative pulse reset signal RST, undersuing RST and each delay unit it is original defeated
Enter signal phase "AND", obtained signal is re-used as the new input signal of delay unit.Reset signal RST will remove previous triggering
The delay of generation still needs to make to begin from repeated trigger by td1The rising edge of period Q can just be transmitted to Qd1, because
This, export monostable pulse extension trigger twice between interval time, realize repeatable triggering.
As can be seen that compared with prior art, the monostable flipflop circuit proposed by the present invention based on time delay chain only wraps
The time delay chain being made of phase inverter and corresponding digital logic gate are included, resistance, capacitance, amplifier and comparator are not needed, it is compatible
Standard digital technique and design cycle.And easily realize monostable pulsewidth current adjustment and repeatable triggering, it only need to be to the inclined of time delay chain
Set electric current carry out control can realize monostable pulsewidth current adjustment, only the input signal of each delay unit need to be resetted
It can realize repeatable triggering.Compared to existing method, the monostable trigger utensil proposed by the present invention based on time delay chain
There are low cost, low-power consumption, compatible strong, pulsewidth current adjustment and repeatable triggering.
These are only the embodiment of the present invention, but be not intended to restrict the invention, it is all the spirit and principles in the present invention it
Interior done any modification, equivalent replacement or improvement etc., should be included within scope of the presently claimed invention.
Claims (4)
1. a kind of monostable flipflop, it is characterised in that：Including：Substantially monostable trigger module, time-delay reset module；
Substantially the monostable trigger module is the pulsewidth current adjustment monostable trigger circuit based on time delay chain；It is described substantially monostable
Trigger module and time-delay reset block combiner constitute the monostable triggering of the pulsewidth current adjustment based on time delay chain and repeatable triggering
Device circuit；
Substantially the monostable trigger module includes：Trigger DFF1, time delay chain 1 and time delay chain 2, NAND gate, phase inverter；
The time-delay reset module includes：Trigger DFF2, time delay chain 3 and digital logic gate；The trigger DFF1 and triggering
Device DFF2 is the d type flip flop with reset function；
Substantially in the monostable trigger module, time delay chain 1 believes the output of the trigger DFF1 triggered by input trigger signal TR
Number Q carries out td1Delay, obtains time delayed signal Qd1；The time delay chain 2 is to Qd1Carry out td2Delay, obtains time delayed signal Qd2；When by
Input trigger signal TR causes the variation of Q to be transferred to Qd1When, trigger DFF1 is resetted, Q is made to be reset to before triggering
State, further, when the variation of the Q caused by input trigger signal TR is transferred to Qd2When, reset signal is discharged, to obtain
Monostable pulsewidth is td1, triggering recovery time be td2Output single steady signal；The reset signal is by Qd2Inversion signalWith
Qd1NAND operation is carried out to obtain；
In the time-delay reset module, input trigger signal TR is connected to the triggering clock end of trigger DFF2, trigger DFF2
Output signal QRSOutput reset signal RST is obtained after reverse phase, the reset signal RST is after the delay of time delay chain 3
It is t to obtain total delay timed3Time delayed signal；The time delayed signal carries out "AND" with the trigger DFF1 output signals Q again
Operation, the low effective reset signal RS_RT as trigger DFF2.
2. a kind of monostable flipflop as described in claim 1, it is characterised in that：The time delay chain 1 or time delay chain 2 include at least
The delay unit of two concatenations, single delay unit includes cascade two-stage phase inverter；By the total number for changing delay unit
Or the delay value of single delay unit, the total delay time of different time delay chains is obtained, and then obtain different monostable pulsewidths and touch
Send out recovery time.
3. a kind of monostable flipflop as claimed in claim 2, it is characterised in that：By to phase inverter in the delay unit
Bias currentI CTRL It is adjusted, realizes the current adjustment of phase inverter delay, and then realize the electric current of output single steady signal pulsewidth
It is adjustable.
4. a kind of monostable flipflop as claimed in claim 1 or 2, it is characterised in that：Triggering is inputted within the current monostable period
When signal TR is triggered again, by obtaining Qd1Time delay chain 1 in all delay unit input signals resetted, it is real
The repeatable triggering of existing monostable flipflop；
For to obtaining Qd1Time delay chain 1 in the reset signal that is resetted of all delay unit input signals generate process
It is：The original input signal of each delay unit in reset signal RST and time delay chain 1 is subjected to AND operation, then by operation
The signal obtained afterwards is connected to each delay unit input terminal in time delay chain 1.
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| CN201610540981.8A CN106026982B (en) | 2016-07-11 | 2016-07-11 | A kind of monostable flipflop |
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| CN201610540981.8A CN106026982B (en) | 2016-07-11 | 2016-07-11 | A kind of monostable flipflop |
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| CN106026982B true CN106026982B (en) | 2018-09-25 |
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| CN110143178A (en) * | 2019-04-04 | 2019-08-20 | 扬州工业职业技术学院 | It is a kind of for traffic and the digital pulse signal identification device of vehicle arrangement |
| CN111338414B (en) * | 2020-03-09 | 2022-02-11 | 厦门润积集成电路技术有限公司 | Low-power consumption monostable circuit capable of being triggered repeatedly |
| CN111600581B (en) * | 2020-05-14 | 2023-07-25 | 南京信息职业技术学院 | Digitally controlled monostable trigger and control method thereof |
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|---|---|---|---|---|
| US3304437A (en) * | 1963-08-20 | 1967-02-14 | Paul K Dano | Single-shot multivibrator pulse width controlled by repetition rate |
| US6710622B1 (en) * | 2002-04-12 | 2004-03-23 | National Semiconductor Corp | Programmable digital one-shot |
| CN102394640A (en) * | 2011-09-16 | 2012-03-28 | 无锡东集电子有限责任公司 | Delay lock-loop circuit and quick lock-in algorithm |
| CN202550983U (en) * | 2012-02-29 | 2012-11-21 | 成都智利达科技有限公司 | Monostable trigger capable of long-time delay |
-
2016
- 2016-07-11 CN CN201610540981.8A patent/CN106026982B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3304437A (en) * | 1963-08-20 | 1967-02-14 | Paul K Dano | Single-shot multivibrator pulse width controlled by repetition rate |
| US6710622B1 (en) * | 2002-04-12 | 2004-03-23 | National Semiconductor Corp | Programmable digital one-shot |
| CN102394640A (en) * | 2011-09-16 | 2012-03-28 | 无锡东集电子有限责任公司 | Delay lock-loop circuit and quick lock-in algorithm |
| CN202550983U (en) * | 2012-02-29 | 2012-11-21 | 成都智利达科技有限公司 | Monostable trigger capable of long-time delay |
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