CN111600581B - Digitally controlled monostable trigger and control method thereof - Google Patents
Digitally controlled monostable trigger and control method thereof Download PDFInfo
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- CN111600581B CN111600581B CN202010406822.5A CN202010406822A CN111600581B CN 111600581 B CN111600581 B CN 111600581B CN 202010406822 A CN202010406822 A CN 202010406822A CN 111600581 B CN111600581 B CN 111600581B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/033—Monostable circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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Abstract
The invention discloses a digital control monostable trigger and a control method thereof in the technical field of integrated circuit application, and aims to solve the technical problems that in the prior art, transient time is coarsely adjusted in a way of rotating an adjusting port in a monostable trigger circuit, and accurate control is not facilitated. The monostable trigger comprises a NAND gate 1 serving as an input end, a NAND gate 2 serving as an output end, and a digital control circuit electrically connected between the NAND gate 1 and the NAND gate 2; the digital control circuit comprises a NAND gate 3 and a NAND gate 4 which are respectively and electrically connected with the NAND gate 1, wherein the NAND gate 3 is electrically connected with the NAND gate 1 through an RC circuit, and the NAND gate 4 is electrically connected with the NAND gate 1 through a counter; the NAND gate 3 and the NAND gate 4 are respectively and electrically connected with a NAND gate 5, and a JK trigger is electrically connected between the NAND gate 5 and the NAND gate 2; the clock signal input end of the counter is electrically connected with the multivibrator.
Description
Technical Field
The invention relates to a digital control monostable trigger and a control method thereof, belonging to the technical field of integrated circuit application.
Background
The monostable flip-flop outputs a low level trigger signal so that the monostable flip-flop transitions from a steady state to a transient state. In a common monostable trigger circuit, a Resistor-capacitor circuit (Resistor-Capacitance circuit, RC) is used for charging and discharging, the voltage at two ends of the capacitor and the Resistor is gradually changed, and when the voltage influence exceeds a threshold value, the state of the monostable trigger circuit is returned to a steady state from a transient state. The transient time is determined by the time constant of the RC charge-discharge circuit, and the time constant is the product of the resistance value and the capacitance value. Once the resistor and capacitor in the RC charge-discharge circuit are selected, the transient time is determined. Although the circuit can adopt an adjustable resistor and an adjustable capacitor, the resistance value and the capacitance value are changed through the adjusting port on the rotary resistor-capacitor element, the time constant is changed, and then the transient time is changed, but the transient time is coarsely adjusted through the mode of rotating the adjusting port, so that the accurate control is not facilitated.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a digital control monostable trigger and a control method thereof, so as to solve the technical problems that the transient time is coarsely adjusted in a mode of rotating an adjusting port in a monostable trigger circuit in the prior art, and the accurate control is not facilitated.
In order to solve the technical problems, the invention adopts the following technical scheme:
a digital controlled monostable trigger comprises a NAND gate 1 as an input end, a NAND gate 2 as an output end, and a digital control circuit electrically connected between the NAND gate 1 and the NAND gate 2;
the digital control circuit comprises a NAND gate 3 and a NAND gate 4 which are respectively and electrically connected with the NAND gate 1, wherein the NAND gate 3 is electrically connected with the NAND gate 1 through an RC circuit, and the NAND gate 4 is electrically connected with the NAND gate 1 through a counter; the NAND gate 3 and the NAND gate 4 are respectively and electrically connected with a NAND gate 5, and a JK trigger is electrically connected between the NAND gate 5 and the NAND gate 2; the clock signal input end of the counter is electrically connected with a multivibrator, the enabling end of the counter is electrically connected with the NAND gate 1, and the carry end of the counter is electrically connected with the NAND gate 4.
Further, the nand gate 1 and the nand gate 5 are two input nand gates, two input ends of the nand gate 5 are respectively and electrically connected with the output ends of the nand gate 3 and the nand gate 4, the output end of the nand gate 5 is electrically connected with the input end of the nand gate 2 through a JK trigger, the output end of the nand gate 2 is electrically connected with one input end of the nand gate 1, and the other input end of the nand gate 1 is connected with an access signal;
the J, K input end of the JK trigger is connected with a high level, and the output end of the JK trigger is preset to output a low level.
Further, the counter is a multi-bit integrated counter or an arbitrary counter, the carry value of the multi-bit integrated counter comprises at least any two of binary, five-system, decimal and hexadecimal, and the arbitrary counter is realized by adopting a feedback zero clearing method or/and a feedback number setting method.
In order to achieve the above purpose, the present invention also provides a control method of a digitally controlled monostable trigger, comprising the following steps:
the nand gate 1 outputs a high level signal corresponding to a trigger signal in response to a low level trigger signal;
the counter responds to the high level signal, extracts rectangular pulses generated by the multivibrator as clock signals, divides the frequency of the clock signals based on a preset advance value, and outputs pulse signals with preset time length;
the JK trigger is turned over in response to a pulse signal with preset time length, and the starting number of the JK trigger is 0;
the nand gate 2, in response to the flip-flop, causes a transition in the state in which the monostable flip-flop is in a steady state or a transient state.
Further, after the nand gate 1 outputs a high level signal corresponding to a trigger signal in response to the trigger signal, it further includes: the NAND gate 2 responds to a high level signal to enable the monostable trigger to be in a transient state;
a method of transitioning a state in which a monostable flip-flop is located, comprising: the nand gate 2 transitions the monostable flip-flop to a steady state in response to the flip-flop.
Further, the counter is a multi-bit integrated counter or an arbitrary counter, the carry value of the multi-bit integrated counter comprises at least any two of binary, five-system, decimal and hexadecimal, and the arbitrary counter is realized by adopting a feedback zero clearing method or/and a feedback number setting method.
Compared with the prior art, the invention has the beneficial effects that: the monostable trigger and the control method thereof replace the traditional RC circuit by utilizing a digital control circuit which can precisely control time and can output high and low levels, the digital control circuit comprises a counter, a multivibrator and a JK trigger, an enabling end of the counter is connected with an input end of the monostable trigger, a clock signal input end is connected with the multivibrator, a carry end is connected with the JK trigger through a NAND gate circuit, a rectangular wave generated by the multivibrator is used as a clock input of the counter, a preset carry value of the counter can be used for dividing a clock signal to output pulse signals with different time lengths, the JK trigger is turned over in response to the pulse signals, and then the output level of the output end of the monostable trigger is changed, so that the monostable trigger can be converted between transient state and steady state. Based on the monostable trigger and the control method thereof, the pulse time of the rectangular wave can be accurately controlled by setting the carry value of the counter, so that the transient time of the monostable trigger can be accurately controlled.
Drawings
FIG. 1 is a circuit diagram of a conventional monostable flip-flop referred to in an embodiment of the present invention;
fig. 2 is a circuit diagram of a monostable flip-flop embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present invention, and are not intended to limit the scope of the present invention.
At present, monostable flip-flops can be divided into monostable flip-flops composed of gates according to circuit forms, MSI integrated monostable flip-flops and monostable flip-flops composed of 555 timers, and monostable flip-flops composed of CMOS gates are divided into positive pulse triggering and negative pulse triggering. A common simple monostable flip-flop circuit, as shown in fig. 1, is a circuit diagram of a conventional monostable flip-flop mentioned in the embodiment of the present invention, and is composed of a nand gate 1, a capacitor, a resistor and a nand gate 2, and the basic working procedure is as follows: when no trigger signal exists, the circuit is in a steady state, when a low-level trigger signal is input to the NAND gate 1, the NAND gate 1 outputs a high level, and the voltage at two ends of the capacitor cannot jump; at this time, the input terminal voltage of the nand gate 2 becomes high level, and outputs low level, and at the same time, the output voltage is fed back to the input terminal of the nand gate 1, and the output high level of the nand gate 1 is maintained; along with the charging of the capacitor, the voltage at two ends of the capacitor rises according to an exponential rule, the voltage at the input end of the NAND gate 2 simultaneously drops, when the voltage is lower than the threshold value of the NAND gate 2, the output of the NAND gate 2 returns to a high-level steady state, and meanwhile, the voltage is fed back to the input end of the NAND gate 1, and the NAND gate 1 outputs a low level. In the circuit, an RC charge-discharge circuit is utilized to determine the transient time, and the mode has the technical defects of short transient time and difficult transient time adjustment.
In view of the above technical problems and drawbacks, the present invention provides a digitally controlled monostable flip-flop, which uses a digital control circuit capable of precisely controlling time and outputting high and low levels, and particularly as shown in fig. 2, is a circuit diagram of an embodiment of the monostable flip-flop of the present invention, wherein seven nand gates, namely nand gates 1 to 7 are adopted in total, wherein nand gate 1 and nand gate 5 have two input ends, and the rest is a single input end. For ease of expression, NAND gates 1-7 are identified as gates 1-7 in FIG. 2.
More specifically, the monostable flip-flop of the present invention includes a nand gate 1 as an input terminal, a nand gate 2 as an output terminal, and a digital control circuit electrically connected between the nand gate 1 and the nand gate 2; the digital control circuit comprises a NAND gate 3 and a NAND gate 4 which are respectively and electrically connected with the NAND gate 1, wherein the NAND gate 3 is electrically connected with the NAND gate 1 through an RC circuit, the NAND gate 4 is electrically connected with the NAND gate 1 through a counter, the output ends of the NAND gate 3 and the NAND gate 4 are respectively connected with two input ends of a NAND gate 5, a JK trigger is connected between the output end of the NAND gate 5 and the input end of the NAND gate 2, the input end of the NAND gate 2 is electrically connected with one input end of the NAND gate 1, and the other input end of the NAND gate 1 is provided with a trigger signal. The clock signal input end of the counter is electrically connected with a multivibrator, the enabling end of the counter is connected with the output end of the NAND gate 1, and the carry end of the counter is electrically connected with the input end of the NAND gate 4; the multivibrator comprises a NAND gate 6 and a NAND gate 7 which are connected in series, the NAND gate 6 is connected with a resistor in parallel, two ends of the NAND gate 6 and the NAND gate 7 which are connected in series are connected with a capacitor in parallel, and the NAND gate 7 is electrically connected with a clock signal input end of the counter.
Generating a rectangular wave oscillation signal by using a multivibrator as a clock input of a counter circuit; the counter is used for generating a carry signal capable of enabling the JK trigger to turn over, the J, K input end of the JK trigger is connected with a high level, the output end of the JK trigger is preset to output a low level, the starting position number of the JK trigger is 0, and when the clock control input end of the JK trigger has a rising edge signal, the JK trigger turns over. By setting the carry value of the counter, pulses with different time lengths can be output as carry signals; the JK flip-flop may flip in response to the carry signal and the nand gate 2 may change its output level in response to the flip-flop, thereby causing the monostable flip-flop to transition between the transient state and the steady state. In this embodiment, since the pulse time of the rectangular wave can be precisely controlled by the counter, the transient time of the monostable trigger can be precisely controlled. The counter can adopt a multi-bit integrated counter or an arbitrary counter, the carry value of the multi-bit integrated counter comprises at least any two of binary system, five system, decimal system and hexadecimal system, and the arbitrary counter can be realized by adopting a feedback zero clearing method or/and a feedback digit placement method. The counter can divide the frequency of the clock signal based on the set carry value and output a pulse signal with corresponding time length so as to realize more flexible control of the transient time of the monostable trigger.
The invention also provides a control method of the monostable trigger controlled by numbers, which is the control method of the monostable trigger, and the specific control process is as follows:
the NAND gate 1 outputs a high-level A signal corresponding to a trigger signal in response to the low-level trigger signal;
the NAND gate 2 responds to the high level A signal to enable the monostable trigger to be in a stable state;
the counter extracts rectangular pulses generated by the multivibrator as clock signals, divides the frequency of the clock signals based on a preset advance value and outputs pulse signals with preset time length;
the JK trigger with the initial position number of 0 is turned over in response to the pulse signal, the counter can adopt a multi-bit integrated counter or an arbitrary counter, the carry value of the multi-bit integrated counter comprises at least any two of binary, five-system, decimal and hexadecimal, and the arbitrary counter can be realized by adopting a feedback zero clearing method or/and a feedback position number method;
the nand gate 2 transitions the monostable flip-flop to a steady state in response to the flip-flop.
The process according to the invention is further illustrated below with reference to specific examples. Nand gate 1 is the input of the circuit and nand gate 2 is the output of the circuit. When the low-level trigger signal enters the input end, the output of the NAND gate 1 is a signal high level A, the signal A is transmitted to RC, the capacitor voltage cannot be suddenly changed, the input end of the NAND gate 3 instantly outputs a low level, the output level of the NAND gate 5 instantly outputs a rising edge signal from low to high, the clock control end of the trigger receives the rising edge signal, the output state is turned over, the high level is output, the NAND gate 2 outputs the low level, and the circuit enters a transient state. The low level output by the NOT gate 2 maintains the high level output by the NOT gate 1 at the same time, and the RC circuit capacitor connected with the NOT gate 3 is charged, so that the high level of the input end of the NOT gate 3 changes to the low level, the output of the NOT gate 3 changes to the high level, and the output level of the NOT gate 5 changes from the high level to the low level, so that the triggered output state is not influenced. The NAND gate 1 outputs a signal A, which is transmitted to the enabling end of the counter, allowing the counter to start working. And the NAND gate 6 and the NAND gate 7 are combined with a capacitor and a resistor to realize a multivibrator, and a rectangular wave signal is output and is used as a clock signal input of a counter. The counter is set to be any n-system, n clock signals are input, a high-level carry signal is output, the counter finishes n-system counting, the carry signal is a high-level pulse signal B, the signal B is transmitted to the NAND gate 4, the level output by the NAND gate 4 is changed from high to low, the level output by the NAND gate 5 is changed from low to high, and the rising edge signal enables the NAND gate 2 to output high level, and the circuit returns to a steady state.
The NAND gate 3, the NAND gate 4, the NAND gate 5 and the JK trigger are combined together to receive the signal A and the signal B, when the signal A or the signal B has high level, the NAND gate 3 and the NAND gate 4 can both output low level pulse signals, so that the NAND gate 5 outputs high level pulse and transmits the high level pulse to the JK trigger, the output state is inverted, and the high level is converted into the low level or the low level is converted into the high level. The signal A appears, the JK trigger turns over once, the NAND gate 2 outputs a low level, the circuit enters a transient state, the output end of the NAND gate 3 changes to a low level through the RC charging circuit, a high level is output, and the input of the NAND gate 5 is high level. The signal B appears, the JK trigger is turned over once, the NAND gate 2 outputs high level, and the circuit returns to steady state. The signal B is a high level pulse, and the nand gate 4 outputs a low level and then changes to a high level. The input of the nand gate 5 is high, and as long as there is a low signal, a rising edge is completed and the flip-flop is flipped.
The output level inversion of the nand gate 2 is completed: when a low-level trigger signal enters an input end, a high-level pulse appears in a signal A, the output level of the NAND gate 2 is changed from the high level to the low level, the monostable trigger enters a transient state, the counter starts to count, a preset output port is the low level, n-system counting is completed, a carry signal is output, the carry signal shows a high-level pulse for a signal B, the output level of the NAND gate 2 is changed from the low level to the high level, and the monostable trigger returns to a steady state.
The JK trigger is a rising edge trigger, JK is connected with high level, and when a clock signal is input, the output state is turned over. The A signal and the B signal have high level and directly enter the clock input end of the JK trigger, and the logic relationship is as follows: a+b. The NAND gate is adopted in the circuit to complete the logic relation of A+B, and the A signal and the B signal are respectively NAND and output signals and then NAND.
The n-system of the counter can be set through the counter, the setting method has the modes of zero clearing and number setting, the setting of the counter is carried out by utilizing a dial switch and a NAND gate 8, the single-chip four-bit counter can be used for completing hexadecimal at most, the two-chip four-bit counter can be used for completing sixty-four-system at most, and a plurality of counters can be connected in series to complete more system. The period of the carry signal is n times the clock signal. The setting of the counter is completely digital, and the digital control of the monostable trigger is completed by setting the counter.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (5)
1. The control method of the monostable trigger controlled digitally is characterized in that the monostable trigger comprises a NAND gate 1 serving as an input end, a NAND gate 2 serving as an output end, and a digital control circuit electrically connected between the NAND gate 1 and the NAND gate 2; the digital control circuit comprises a NAND gate 3 and a NAND gate 4 which are respectively and electrically connected with the NAND gate 1, wherein the NAND gate 3 is electrically connected with the NAND gate 1 through an RC circuit, and the NAND gate 4 is electrically connected with the NAND gate 1 through a counter; the NAND gate 3 and the NAND gate 4 are respectively and electrically connected with a NAND gate 5, and a JK trigger is electrically connected between the NAND gate 5 and the NAND gate 2; the clock signal input end of the counter is electrically connected with a multivibrator, the enabling end of the counter is electrically connected with the NAND gate 1, and the carry end of the counter is electrically connected with the NAND gate 4;
the control method comprises the following steps:
the nand gate 1 outputs a high level signal corresponding to a trigger signal in response to a low level trigger signal;
the counter responds to the high level signal, extracts rectangular pulses generated by the multivibrator as clock signals, divides the frequency of the clock signals based on a preset advance value, and outputs pulse signals with preset time length;
the JK trigger is turned over in response to a pulse signal with preset time length, and the starting number of the JK trigger is 0;
the nand gate 2, in response to the flip-flop, causes a transition in the state in which the monostable flip-flop is in a steady state or a transient state.
2. The control method of a digitally controlled monostable flip-flop according to claim 1, further comprising, after the nand gate 1 outputs a high level signal corresponding to a trigger signal in response to the trigger signal: the NAND gate 2 responds to a high level signal to enable the monostable trigger to be in a transient state;
a method of transitioning a state in which a monostable flip-flop is located, comprising: the nand gate 2 transitions the monostable flip-flop to a steady state in response to the flip-flop.
3. The method for controlling a digitally controlled monostable flip-flop according to claim 1, wherein the counter is a multi-bit integrated counter whose carry value comprises at least any two of binary, five-level, decimal, and hexadecimal, or an arbitrary counter implemented by a feedback zero clearing method or/and a feedback digit placement method.
4. The method for controlling a digitally controlled monostable flip-flop according to claim 1, wherein the nand gate 1 and the nand gate 5 are two-input nand gates, two input ends of the nand gate 5 are respectively electrically connected with output ends of the nand gate 3 and the nand gate 4, an output end of the nand gate 5 is electrically connected with an input end of the nand gate 2 through the JK flip-flop, an output end of the nand gate 2 is electrically connected with one input end of the nand gate 1, and the other input end of the nand gate 1 is connected with an access signal;
the J, K input end of the JK trigger is connected with a high level, and the output end of the JK trigger is preset to output a low level.
5. The method for controlling a digitally controlled monostable flip-flop according to claim 1, wherein the counter is a multi-bit integrated counter whose carry value comprises at least any two of binary, five-level, decimal, and hexadecimal, or an arbitrary counter implemented by a feedback zero clearing method or/and a feedback digit placement method.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1145552A (en) * | 1995-09-14 | 1997-03-19 | 明碁电脑股份有限公司 | Single steady signal generating device |
| CN104468073A (en) * | 2013-09-23 | 2015-03-25 | 西南科技大学 | 0-150 V wide-range remote control synchronous pulse generator |
| CN106026982A (en) * | 2016-07-11 | 2016-10-12 | 湖北大学 | Monostable trigger |
| CN209448731U (en) * | 2019-01-09 | 2019-09-27 | 昆明理工大学 | It is a kind of serially to set several synchronizing and set counter |
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2020
- 2020-05-14 CN CN202010406822.5A patent/CN111600581B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1145552A (en) * | 1995-09-14 | 1997-03-19 | 明碁电脑股份有限公司 | Single steady signal generating device |
| CN104468073A (en) * | 2013-09-23 | 2015-03-25 | 西南科技大学 | 0-150 V wide-range remote control synchronous pulse generator |
| CN106026982A (en) * | 2016-07-11 | 2016-10-12 | 湖北大学 | Monostable trigger |
| CN209448731U (en) * | 2019-01-09 | 2019-09-27 | 昆明理工大学 | It is a kind of serially to set several synchronizing and set counter |
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