CN111600581A - Digital control monostable trigger and control method thereof - Google Patents
Digital control monostable trigger and control method thereof Download PDFInfo
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- CN111600581A CN111600581A CN202010406822.5A CN202010406822A CN111600581A CN 111600581 A CN111600581 A CN 111600581A CN 202010406822 A CN202010406822 A CN 202010406822A CN 111600581 A CN111600581 A CN 111600581A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/033—Monostable circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
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- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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Abstract
The invention discloses a digital control monostable trigger and a control method thereof in the technical field of integrated circuit application, and aims to solve the technical problems that in the prior art, transient time is adjusted more coarsely in a monostable trigger circuit in a mode of rotating an adjusting port, and accurate control is not facilitated. The monostable flip-flop comprises a NAND gate 1 serving as an input end, a NAND gate 2 serving as an output end and a digital control circuit electrically connected between the NAND gate 1 and the NAND gate 2; the digital control circuit comprises a NAND gate 3 and a NAND gate 4 which are respectively electrically connected with a NAND gate 1, wherein the NAND gate 3 is electrically connected with the NAND gate 1 through an RC circuit, and the NAND gate 4 is electrically connected with the NAND gate 1 through a counter; the NAND gates 3 and 4 are respectively electrically connected with a NAND gate 5, and a JK trigger is electrically connected between the NAND gate 5 and the NAND gate 2; the clock signal input end of the counter is electrically connected with a multivibrator.
Description
Technical Field
The invention relates to a digital control monostable trigger and a control method thereof, belonging to the technical field of integrated circuit application.
Background
The monostable flip-flop outputs a low level trigger signal, so that the monostable flip-flop is switched from a steady state to a transient state. In a common monostable trigger circuit, a Resistor-capacitor circuit (RC) is used for charging and discharging, the voltage at two ends of a capacitor and a Resistor changes gradually, and when the NAND gate at the output port of the monostable trigger circuit is influenced by the voltage and exceeds a threshold value, the state of the monostable trigger circuit returns to a steady state from a transient state. The transient time is determined by the time constant of the RC charge-discharge circuit, which is the product of the resistance and the capacitance. Once the resistor and the capacitor in the RC charging and discharging circuit are selected, the transient time is determined. Although the circuit can adopt an adjustable resistor and an adjustable capacitor, the resistance value and the capacitance value are changed by rotating an adjusting port on the resistor-capacitor element, the time constant is changed, and the transient time is further changed, the transient time is adjusted in a mode of rotating the adjusting port, and the transient time is not easy to control accurately.
Disclosure of Invention
The invention aims to provide a digital control monostable trigger and a control method thereof, aiming at solving the technical problems that the transient time is adjusted more coarsely in a monostable trigger circuit by rotating an adjusting port and is not beneficial to accurate control in the prior art.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a digital control monostable trigger comprises a NAND gate 1 as an input end, a NAND gate 2 as an output end and a digital control circuit electrically connected between the NAND gate 1 and the NAND gate 2;
the digital control circuit comprises a NAND gate 3 and a NAND gate 4 which are respectively electrically connected with a NAND gate 1, wherein the NAND gate 3 is electrically connected with the NAND gate 1 through an RC circuit, and the NAND gate 4 is electrically connected with the NAND gate 1 through a counter; the NAND gates 3 and 4 are respectively electrically connected with a NAND gate 5, and a JK trigger is electrically connected between the NAND gate 5 and the NAND gate 2; the clock signal input end of the counter is electrically connected with the multivibrator, the enable end of the counter is electrically connected with the NAND gate 1, and the carry end of the counter is electrically connected with the NAND gate 4.
Furthermore, the nand gate 1 and the nand gate 5 are two-input-end nand gates, two input ends of the nand gate 5 are electrically connected with the output ends of the nand gate 3 and the nand gate 4 respectively, the output end of the nand gate 5 is electrically connected with the input end of the nand gate 2 through the JK trigger, the output end of the nand gate 2 is electrically connected with one input end of the nand gate 1, and the other input end of the nand gate 1 is connected with a trigger signal;
the J, K input end of the JK trigger is connected with high level, and the output end of the JK trigger is preset to output low level.
Further, the counter is a multi-bit system integrated counter or an arbitrary system counter, the carry value of the multi-bit system integrated counter includes at least any two of binary system, quinary system, decimal system and hexadecimal system, and the arbitrary system counter is implemented by a feedback zero clearing method or/and a feedback number setting method.
In order to achieve the above object, the present invention further provides a method for controlling a digitally controlled monostable flip-flop, comprising the steps of:
the NAND gate 1 responds to the low-level trigger signal and outputs a high-level signal corresponding to the trigger signal;
the counter responds to the high-level signal, extracts the rectangular pulse generated by the multivibrator as a clock signal, divides the frequency of the clock signal based on a preset carry value and outputs a pulse signal with a preset time length;
the JK trigger is turned over in response to a pulse signal with a preset time length, and the starting setting number of the JK trigger is 0;
the NAND gate 2 responds to the overturn to enable the state of the monostable flip-flop to be converted, and the state is a steady state or a transient state.
Further, after the nand gate 1 outputs a high level signal corresponding to the trigger signal in response to the trigger signal, the method further includes: the NAND gate 2 responds to a high level signal to enable the monostable trigger to be in a transient state;
the method for making the state of the monostable trigger to be changed comprises the following steps: nand gate 2 transitions the monostable flip-flop to the steady state in response to a flip-flop.
Further, the counter is a multi-bit system integrated counter or an arbitrary system counter, the carry value of the multi-bit system integrated counter includes at least any two of binary system, quinary system, decimal system and hexadecimal system, and the arbitrary system counter is implemented by a feedback zero clearing method or/and a feedback number setting method.
Compared with the prior art, the invention has the following beneficial effects: the monostable trigger and the control method thereof replace the traditional RC circuit by utilizing a digital control circuit which can accurately control time and can output high and low levels, the digital control circuit comprises a counter, a multivibrator and a JK trigger, the enable end of the counter is connected with the input end of the monostable trigger, the clock signal input end is connected with the multivibrator, the carry end is connected with the JK trigger through a NAND gate circuit, a rectangular wave generated by the multivibrator is used as the clock input of the counter, the clock signal can be divided by utilizing the carry value preset by the counter to output pulse signals with different time lengths, the JK trigger is turned over in response to the pulse signals, and the output level of the output end of the monostable trigger is further changed, so that the monostable trigger can be switched between a transient state and a steady state. Based on the monostable trigger and the control method thereof, the pulse time of the rectangular wave can be accurately controlled by setting the carry numerical value of the counter, so that the transient time of the monostable trigger can be accurately controlled.
Drawings
FIG. 1 is a circuit diagram of a conventional one-shot flip-flop according to an embodiment of the present invention;
fig. 2 is a circuit diagram of an embodiment of a monostable flip-flop of the invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
At present, the monostable flip-flop can be divided into a monostable flip-flop composed of gate circuits according to the circuit form, an MSI integrated monostable flip-flop and a monostable flip-flop composed of a 555 timer, and the monostable flip-flop composed of CMOS gate circuits is divided into positive pulse triggering and negative pulse triggering. A conventional simple monostable flip-flop circuit, as shown in fig. 1, is a circuit diagram of a conventional monostable flip-flop mentioned in the embodiment of the present invention, and is composed of a nand gate 1, a capacitor, a resistor, and a nand gate 2, and its basic operation process is as follows: when no trigger signal exists, the circuit is in a stable state, when a low-level trigger signal is input to the NAND gate 1, the NAND gate 1 outputs a high level, and the voltage at two ends of the capacitor cannot jump; at the moment, the voltage of the input end of the NAND gate 2 becomes high level, low level is output, meanwhile, the output voltage is fed back to the input end of the NAND gate 1, and the high level output by the NAND gate 1 is maintained; along with the charging of the capacitor, the voltage at two ends of the capacitor rises according to an exponential law, the voltage at the input end of the NAND gate 2 falls at the same time, when the voltage is lower than the threshold value of the NAND gate 2, the output of the NAND gate 2 returns to the stable state of high level and is fed back to the input end of the NAND gate 1 at the same time, and the NAND gate 1 outputs low level. In the circuit, an RC charge-discharge circuit is used for determining the transient time, and the method has the technical defects of short transient time and difficult transient time adjustment.
In view of the above technical problems and drawbacks, the present invention provides a digitally controlled monostable flip-flop, which utilizes a digital control circuit capable of accurately controlling time and outputting high and low levels, and is specifically a circuit diagram of an embodiment of the monostable flip-flop of the present invention as shown in fig. 2, wherein seven nand gates, that is, nand gates 1 to 7, are used, wherein the nand gate 1 and the nand gate 5 are two input ends, and the rest are single input ends. For convenience of expression, NAND gates 1-7 are identified as gates 1-7 in FIG. 2.
More specifically, the monostable flip-flop of the invention comprises a NAND gate 1 as an input end, a NAND gate 2 as an output end, and a digital control circuit electrically connected between the NAND gate 1 and the NAND gate 2; the digital control circuit comprises a NAND gate 3 and a NAND gate 4 which are respectively electrically connected with a NAND gate 1, wherein the NAND gate 3 is electrically connected with the NAND gate 1 through an RC circuit, the NAND gate 4 is electrically connected with the NAND gate 1 through a counter, the output ends of the NAND gate 3 and the NAND gate 4 are respectively connected with two input ends of a NAND gate 5, a JK trigger is connected between the output end of the NAND gate 5 and the input end of a NAND gate 2, the input end of the NAND gate 2 is electrically connected with one input end of the NAND gate 1, and the other input end of the NAND gate 1 is connected with a trigger signal. The clock signal input end of the counter is electrically connected with the multivibrator, the enable end of the counter is connected with the output end of the NAND gate 1, and the carry end of the counter is electrically connected with the input end of the NAND gate 4; the multivibrator comprises an NAND gate 6 and an NAND gate 7 which are connected in series, the NAND gate 6 is connected with a resistor in parallel, two ends of the NAND gate 6 and the NAND gate 7 which are connected in series are connected with a capacitor in parallel, and the NAND gate 7 is electrically connected with a clock signal input end of a counter.
Generating a rectangular wave oscillation signal by using a multivibrator as the clock input of a counter circuit; the counter is used for generating a carry signal which can enable the JK trigger to be turned over, the J, K input end of the JK trigger is connected with a high level, the output end of the JK trigger is preset to output a low level, the starting setting number of the JK trigger is 0, and when a clock control input end of the JK trigger has a rising edge signal, turning over occurs. Pulses with different time lengths can be output as carry signals by setting the carry numerical value of the counter; the JK flip-flop can be turned over in response to the carry signal, and the NAND gate 2 changes the output level thereof in response to the turning over, so that the monostable flip-flop can be switched between a transient state and a steady state. In this embodiment, the pulse time of the rectangular wave can be accurately controlled by using the counter, so that the transient time of the monostable flip-flop can be accurately controlled. The counter can adopt a multi-bit system integrated counter or an arbitrary system counter, the carry value of the multi-bit system integrated counter comprises at least any two items of binary system, quinary system, decimal system and hexadecimal system, and the arbitrary system counter can be realized by adopting a feedback zero clearing method or/and a feedback setting method. The counter can divide the frequency of the clock signal based on the set carry value and output a pulse signal with a corresponding time length so as to realize more flexible control of the transient time of the monostable trigger.
The invention also provides a control method of the digital control monostable trigger, which is the control method of the monostable trigger, and the specific control process is as follows:
the NAND gate 1 responds to the low-level trigger signal and outputs a high-level A signal corresponding to the trigger signal;
the NAND gate 2 responds to a high-level A signal to enable the monostable trigger to be in a steady state;
the counter extracts a rectangular pulse generated by the multivibrator as a clock signal, divides the frequency of the clock signal based on a preset carry value and outputs a pulse signal with a preset time length;
the JK trigger with the start setting number of 0 is turned over in response to the pulse signal, the counter can adopt a multi-bit system integrated counter or an arbitrary system counter, the carry value of the multi-bit system integrated counter comprises at least any two of binary system, quinary system, decimal system and hexadecimal system, and the arbitrary system counter can be realized by adopting a feedback zero clearing method or/and a feedback setting method;
nand gate 2 transitions the monostable flip-flop to the steady state in response to a flip-flop.
The process of the invention is further illustrated below with reference to specific examples. Nand gate 1 is the input of the circuit and nand gate 2 is the output of the circuit. When a low-level trigger signal enters an input end, the output of the NAND gate 1 is a signal high level A, the signal A is transmitted to the RC, the capacitor voltage cannot be suddenly changed, the input end of the NAND gate 3 is instantly high level, the NAND gate 3 instantly outputs low level, the NAND gate 5 outputs a rising edge signal with the level changed from low to high, the clock control end of the trigger receives the rising edge signal, the output state is turned over, the high level is output, the NAND gate 2 outputs low level, and the circuit enters a transient state. The low level output by the NOT gate 2 maintains the high level output by the NAND gate 1 at the same time, and the RC circuit capacitor connected with the NAND gate 3 is charged, so that the high level of the input end of the NOT gate 3 is changed to the low level, the output of the NOT gate 3 is changed to the high level, the output level of the NAND gate 5 is changed from high to low, and the triggered output state is not influenced. The nand gate 1 outputs a signal a to the enable terminal of the counter, allowing the counter to start operating. The nand gate 6 and the nand gate 7 are combined with a capacitor and a resistor to realize a multivibrator, and output a rectangular wave signal as a clock signal input of the counter. The counter is set to be any n-system, n clock signals are input, a high-level carry signal is output, the counter finishes n-system counting, the carry signal is a high-level pulse signal B, the signal B is transmitted to the NAND gate 4, the level output by the NAND gate 4 is changed from high to low, the NAND gate 5 outputs a rising edge signal with the level changed from low to high, the NAND gate 2 outputs the high level, and the circuit returns to a stable state.
The NAND gate 3, the NAND gate 4, the NAND gate 5 and the JK flip-flop are combined together to receive the signal A and the signal B, when the signal A or the signal B has a high level, the NAND gate 3 and the NAND gate 4 can both output a low-level pulse signal, so that the NAND gate 5 can output a high-level pulse and transmit the high-level pulse to the JK flip-flop, the output state is inverted, and the high level is converted into the low level or the low level is converted into the high level. When the signal A appears, the JK trigger is turned over once, the NAND gate 2 outputs low level, the circuit enters transient state, meanwhile, the output end of the NAND gate 3 is changed to low level through the RC charging circuit, high level is output, and the input of the NAND gate 5 is high level. When the signal B appears, the JK trigger is overturned once, the NAND gate 2 outputs high level, and the circuit returns to a stable state. The signal B is a high level pulse, and the nand gate 4 outputs a low level and then changes to a high level. The input of the nand gate 5 is high level, and as long as there is a low level signal, a rising edge is completed, and the flip-flop is turned over.
And the output level of the NAND gate 2 is inverted: when a low-level trigger signal enters an input end, a high-level pulse appears on a signal A, the output level of a NAND gate 2 is changed from high level to low level, a monostable trigger enters a transient state, a counter starts counting at the same time, a preset output port is low level, n-system counting is completed, a carry signal is output, the carry signal is a signal B, the high-level pulse appears on the carry signal, the output level of the NAND gate 2 is changed from low level to high level, and the monostable trigger returns to a steady state.
The JK trigger is a rising edge trigger, JK is connected with high level, and when a clock signal is input, the output state is inverted. The signal A and the signal B have high level and directly enter the clock input end of the JK trigger, and the logic relationship is as follows: and A + B. The circuits all adopt NAND gates to complete the logic relation of A + B, the A signal and the B signal are respectively NAND, and then the output signal is NAND.
The n-system of the counter can be set through the counter, the setting method comprises a zero clearing mode and a number setting mode, the setting of the counter is carried out by utilizing the dial switch and the NAND gate 8, the single-chip four-bit counter can complete the hexadecimal system at most, the two-chip four-bit counter can complete the sixty-four system at most, and a plurality of counters can be connected in series to complete more systems. The period of the carry signal is n times the period of the clock signal. The counter is fully digitalized after being set, and the digital control of the monostable trigger is completed by setting the counter.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (6)
1. A digital control monostable trigger is characterized by comprising an NAND gate 1 serving as an input end, an NAND gate 2 serving as an output end and a digital control circuit electrically connected between the NAND gate 1 and the NAND gate 2;
the digital control circuit comprises a NAND gate 3 and a NAND gate 4 which are respectively electrically connected with a NAND gate 1, wherein the NAND gate 3 is electrically connected with the NAND gate 1 through an RC circuit, and the NAND gate 4 is electrically connected with the NAND gate 1 through a counter; the NAND gates 3 and 4 are respectively electrically connected with a NAND gate 5, and a JK trigger is electrically connected between the NAND gate 5 and the NAND gate 2; the clock signal input end of the counter is electrically connected with the multivibrator, the enable end of the counter is electrically connected with the NAND gate 1, and the carry end of the counter is electrically connected with the NAND gate 4.
2. The digitally controlled monostable flip-flop according to claim 1, wherein the nand gate 1 and the nand gate 5 are two-input nand gates, two input terminals of the nand gate 5 are electrically connected to the output terminals of the nand gate 3 and the nand gate 4, respectively, the output terminal of the nand gate 5 is electrically connected to the input terminal of the nand gate 2 through the JK flip-flop, the output terminal of the nand gate 2 is electrically connected to one input terminal of the nand gate 1, and the other input terminal of the nand gate 1 is connected to a trigger signal;
the J, K input end of the JK trigger is connected with high level, and the output end of the JK trigger is preset to output low level.
3. The digitally controlled monostable flip-flop according to claim 1, wherein the counter is a multi-bit integrated counter or an arbitrary counter, the carry value of the multi-bit integrated counter includes at least any two of binary, quinary, decimal and hexadecimal, and the arbitrary counter is implemented by a feedback zero clearing method or/and a feedback setting method.
4. A control method of a digital control monostable trigger is characterized by comprising the following steps:
the NAND gate 1 responds to the low-level trigger signal and outputs a high-level signal corresponding to the trigger signal;
the counter responds to the high-level signal, extracts the rectangular pulse generated by the multivibrator as a clock signal, divides the frequency of the clock signal based on a preset carry value and outputs a pulse signal with a preset time length;
the JK trigger is turned over in response to a pulse signal with a preset time length, and the starting setting number of the JK trigger is 0;
the NAND gate 2 responds to the overturn to enable the state of the monostable flip-flop to be converted, and the state is a steady state or a transient state.
5. The method as claimed in claim 4, further comprising, after the nand-gate 1 outputs a high level signal corresponding to the trigger signal in response to the trigger signal, the step of: the NAND gate 2 responds to a high level signal to enable the monostable trigger to be in a transient state;
the method for making the state of the monostable trigger to be changed comprises the following steps: nand gate 2 transitions the monostable flip-flop to the steady state in response to a flip-flop.
6. The method as claimed in claim 4, wherein the counter is a multi-bit integrated counter or an arbitrary counter, the carry value of the multi-bit integrated counter includes at least any two of binary, quinary, decimal and hexadecimal, and the arbitrary counter is implemented by a feedback zero clearing method or/and a feedback setting method.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112213554A (en) * | 2020-09-04 | 2021-01-12 | 中国原子能科学研究院 | Weak current measuring circuit and method based on current frequency conversion method |
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| CN1145552A (en) * | 1995-09-14 | 1997-03-19 | 明碁电脑股份有限公司 | Single steady signal generating device |
| CN104468073A (en) * | 2013-09-23 | 2015-03-25 | 西南科技大学 | 0-150 V wide-range remote control synchronous pulse generator |
| CN106026982A (en) * | 2016-07-11 | 2016-10-12 | 湖北大学 | Monostable trigger |
| CN209448731U (en) * | 2019-01-09 | 2019-09-27 | 昆明理工大学 | It is a kind of serially to set several synchronizing and set counter |
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2020
- 2020-05-14 CN CN202010406822.5A patent/CN111600581B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1145552A (en) * | 1995-09-14 | 1997-03-19 | 明碁电脑股份有限公司 | Single steady signal generating device |
| CN104468073A (en) * | 2013-09-23 | 2015-03-25 | 西南科技大学 | 0-150 V wide-range remote control synchronous pulse generator |
| CN106026982A (en) * | 2016-07-11 | 2016-10-12 | 湖北大学 | Monostable trigger |
| CN209448731U (en) * | 2019-01-09 | 2019-09-27 | 昆明理工大学 | It is a kind of serially to set several synchronizing and set counter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112213554A (en) * | 2020-09-04 | 2021-01-12 | 中国原子能科学研究院 | Weak current measuring circuit and method based on current frequency conversion method |
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