CN115276609A - Monostable trigger capable of being triggered for multiple times and control method thereof - Google Patents
Monostable trigger capable of being triggered for multiple times and control method thereof Download PDFInfo
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- 230000001960 triggered effect Effects 0.000 title abstract description 6
- 230000001052 transient effect Effects 0.000 claims abstract description 25
- 230000002035 prolonged effect Effects 0.000 claims abstract description 8
- 239000003990 capacitor Substances 0.000 claims description 20
- 230000000630 rising effect Effects 0.000 claims description 4
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/033—Monostable circuits
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Abstract
The invention discloses a monostable trigger capable of being triggered for multiple times and a control method thereof. The invention uses the digital control circuit to replace the traditional RC circuit, uses the rectangular wave generated by the multivibrator as the clock input of the counter, uses the carry value preset by the counter to divide the frequency of the clock signal and output the pulse signal with different time length, in the transient time, the counter can be reset by multiple triggering, the overturn time of the RS trigger responding to the pulse signal is prolonged, and then the output level of the output end of the monostable trigger is changed, thus the monostable trigger can be switched between the transient state and the steady state, the pulse time of the rectangular wave can be accurately controlled by setting the carry value of the counter, and the transient time of the monostable trigger can be prolonged by multiple triggering.
Description
Technical Field
The invention relates to a monostable trigger, in particular to a monostable trigger capable of being triggered for multiple times and a control method thereof.
Background
The monostable flip-flop outputs a low trigger signal, so that the monostable flip-flop is converted from a steady state to a transient state.
In a common monostable trigger circuit, a Resistor-capacitor circuit (RC) is used for charging and discharging, the voltage at two ends of a capacitor and a Resistor changes gradually, and when the NAND gate at the output port of the monostable trigger circuit is influenced by the voltage and exceeds a threshold value, the state of the monostable trigger circuit returns to a steady state from a transient state. The transient time is determined by the time constant of the RC charge-discharge circuit, which is the product of the resistance and the capacitance. Once the resistor and the capacitor in the RC charging and discharging circuit are selected, the transient time is determined. Although the circuit can adopt an adjustable resistor and an adjustable capacitor, the resistance value and the capacitance value are changed by rotating an adjusting port on the resistor-capacitor element, the time constant is changed, and the transient time is further changed, the transient time is adjusted in a mode of rotating the adjusting port, and the transient time is not easy to control accurately.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide a monostable trigger capable of being triggered for multiple times and a control method thereof, and solves the problem that the precise control of the trigger is not facilitated due to the fact that the transient time is adjusted coarsely by rotating an adjusting port.
The technical scheme is as follows: the invention relates to a monostable trigger capable of triggering for multiple times, which comprises a comparator two-phase inverting input end serving as an input end, a Q end of an RS trigger serving as an output end, a non-inverting input end of a comparator one and a digital control circuit, wherein the comparator two-phase inverting input end is connected with the comparator two-phase inverting input end;
the input end of the monostable flip-flop is electrically connected with the NAND gate 1 at the same time, rising edge signals are provided for JK flip-flops JK1 and JK2, the low level triggering times of the input end are limited through the NAND gate 2, and the counter is cleared through the NAND gate 3;
the digital control circuit comprises a multivibrator and a counter, wherein the multivibrator is electrically connected with a clock signal input end of the counter, and a carry output of the counter is electrically connected with a non-inverting input end of the first comparator;
the input end of the RS trigger is electrically connected with the inverted input end of the second comparator;
the power supply is connected with a plurality of resistors in series and is grounded, the resistance values of the resistors are equal, each resistor occupies one of the divided power supply voltages, one resistor is connected with the non-inverting input end of the second comparator, and the rest resistors are connected with the inverting input end of the first comparator.
The carry value of the counter includes binary, quinary, decimal, and hexadecimal.
The multivibrator comprises an NAND gate 4 and an NAND gate 5 which are connected in series, wherein the NAND gate 4 is connected with a resistor in parallel, the NAND gate 4 connected in series and two ends of the NAND gate 5 are connected with a capacitor in parallel, and the NAND gate 5 is electrically connected with a clock signal input end of a counter.
A control method of the multi-triggering monostable trigger comprises the following steps:
(1) The carry end of the counter is connected with the non-inverting input end of the first comparator, the 2/3V voltage division point is electrically connected with the inverting input end of the first comparator, and the carry end of the counter outputs a low level; the voltage of the non-inverting input terminal of the comparator I is lower than that of the inverting input terminal of the comparator I, and the comparator I outputs a low level; the R input end of the RS trigger is connected;
(2) The 1/3V voltage division point is connected with the non-inverting input end of the second comparator, the triggering signal input end is connected with the inverting input end of the second comparator, and the triggering signal is at a high level when stable; the voltage of the non-inverting input terminal of the comparator II is lower than that of the inverting input terminal of the comparator II, and the comparator II outputs a low level; the S input end of the RS trigger is connected;
(3) The RS trigger is set to be effective at a low level at the 0 end, when the circuit is started, the capacitor voltage connected with the 0 end is 0V, the RS trigger outputs the low level and is simultaneously connected with the enabling end of the counter, and the counter outputs the low level; the capacitor is connected with a power supply through a resistor for charging, the capacitor becomes a high level, the 0 end does not work any more, and the RS trigger works normally;
(4) The comparator I outputs a low level, and the R input end is the low level; the second comparator outputs a low level, and the S input end is the low level; the output state of the RS trigger is kept at a low level;
(5) The trigger signal inputs the level, the low level pulse appears, the voltage of the non-inverting input end of the comparator II is unchanged, the comparator II outputs the high level, the S input end of the RS trigger is changed into the high level, the level of the R input end of the RS trigger is unchanged and is the low level, the RS trigger outputs the high level, and the counter starts to count;
(6) The input level of the trigger signal is restored to be high level, the second comparator outputs low level, the S input end of the RS trigger is changed into low level, the level of the R input end of the RS trigger is not changed and is low level, and the RS trigger keeps high level output; the state of the monostable trigger is transient;
(7) The input end is electrically connected with the NAND gate 1 at the same time, rising edge signals are provided for JK triggers JK1 and JK2, the low level triggering times of the input end are limited through the NAND gate 2, the counter is cleared through the NAND gate 3, the counter counts again, and the transient time is prolonged;
(8) The counter finishes preset counting, a carry end outputs high level, the carry end of the counter is connected with a non-inverting input end of a first comparator, a 2/3V voltage division point is electrically connected with an inverting input end of the first comparator, the non-inverting input end voltage of the first comparator is higher than that of the first comparator, and the first comparator outputs high level and is connected with an R input end of an RS trigger; the output of the RS trigger is low level and is simultaneously connected with the enabling end of the counter, the counter outputs low level, the comparator outputs low level, the RS trigger keeps low level output, and the monostable trigger is in a steady state.
And (2) adopting a feedback zero clearing method and/or a feedback digit setting method for the carry value of the counter in the step (1).
Has the advantages that: compared with the prior art, the invention has the following advantages: the invention uses a digital control circuit which can accurately control time and can output high and low levels to replace the traditional RC circuit, uses a JK trigger and a NAND gate, can accept multiple triggers within the allowed limited times, clears the counter and recounts the counter; the rectangular wave generated by the multivibrator is used as the clock input of the counter, the clock signal can be divided by using a carry number value preset by the counter, pulse signals with different time lengths are output, the RS trigger is turned over in response to the pulse signals, the output level of the output end of the monostable trigger is further changed, the monostable trigger can be switched between a transient state and a steady state, the pulse time of the rectangular wave can be accurately controlled within an allowed limited number of times by setting the carry number value of the counter, and multiple times of triggering can be accepted, so that the transient time of the monostable trigger can be prolonged.
Drawings
Fig. 1 is a schematic circuit diagram of a multi-shot monostable flip-flop of the invention.
Detailed Description
The technical scheme of the invention is further explained by combining the attached drawings.
Referring to fig. 1, which is a schematic circuit diagram of an embodiment of a multi-triggerable monostable flip-flop according to the present invention, the RS flip-flop is active at a low level at the 0 terminal, when the circuit is started, the capacitor voltage connected to the 0 terminal is 0v, the RS flip-flop outputs a low level, and is connected to the enable terminal of the counter, and the counter outputs a low level. The capacitor is connected with a power supply through the resistor for charging, becomes a high level, the 0 end is set to be ineffective, and the RS trigger works normally.
The carry end of the counter is connected with the non-inverting input end of the comparator 1, the 2/3V voltage division point is electrically connected with the inverting input end of the comparator 1, the carry end of the counter is output at a low level, the voltage of the non-inverting input end of the comparator 1 is lower than that of the inverting input end of the comparator 1, and the comparator 1 outputs a low level and is connected with the R input end of the RS trigger; the 1/3V voltage division point is connected with the non-inverting input end of the comparator 2, the trigger signal input end is connected with the inverting input end of the comparator 2, the trigger signal is at high level when stable, the voltage of the non-inverting input end of the comparator 2 is lower than that of the inverting input end of the comparator 2, and the comparator 2 outputs low level and is connected with the S input end of the RS trigger.
The comparator 1 outputs a low level, and the R input end is the low level; the comparator 2 outputs a low level, and the S input end is the low level; r =0, s =0, q =0, the output state of the rs flip-flop is maintained at low level.
When a low-level pulse occurs in a trigger signal input signal, the voltage at the non-inverting input terminal of the comparator 2 is unchanged, the comparator 2 outputs a high level, the S input terminal of the RS trigger becomes a high level, the level of the R input terminal of the RS trigger is unchanged and is a low level, R =0, S =1, Q =1, the RS trigger outputs a high level, and the counter starts to count.
The trigger signal inputs signals, low-level pulses appear, high-level pulses are output through the NAND gate 1, the JK trigger JK1 outputs high levels, and the JK trigger JK2 outputs low levels; JK triggers JK2 and JK1 are 01;
the trigger signal is input again, a low-level pulse appears, the low-level pulse is output through the NAND gate 1, the JK trigger JK1 outputs a low level, and the JK trigger JK2 outputs a high level; JK triggers JK2 and JK1 are 10;
the trigger signal is input again, a low-level pulse appears, the low-level pulse is output through the NAND gate 1, the JK trigger JK1 outputs a high level, and the JK trigger JK2 outputs a high level; JK triggers JK2 and JK1 are 11;
the three states of the JK triggers JK2 and JK1 clear the counter through the NAND gate, the counter counts again, and the transient time is prolonged;
when the JK triggers JK2 and JK1 are 11, outputting low level through the NAND gate 23, and limiting the low level triggering times of the input end;
the input level of the trigger signal is restored to high level, the comparator 2 outputs low level, the S input end of the RS flip-flop becomes low level, the level of the R input end of the RS flip-flop is not changed, the RS flip-flop is low level, R =0, S =0, q =1, and the RS flip-flop keeps high level output.
When a signal is input, a low-level pulse appears again, the voltage of the non-inverting input terminal of the comparator 2 is unchanged, the comparator 2 outputs a high level, the S input terminal of the RS trigger is changed into a high level, the level of the R input terminal of the RS trigger is unchanged and is a low level, R =0, S =1, Q =1, and the output of the RS trigger is still a high level;
the state of the monostable flip-flop is transient at this time.
The counter finishes preset counting, the carry end outputs high level, the carry end of the counter is connected with the non-inverting input end of the comparator 1, the 2/3V voltage division point is electrically connected with the inverting input end of the comparator 1, the voltage of the non-inverting input end of the comparator 1 is higher than that of the inverting input end of the comparator 1, and the comparator 1 outputs high level and is connected with the R input end of the RS trigger; r =1, s =0, q =0, rs flip-flop output is low. And meanwhile, the enabling end of the counter is connected, the counter outputs a low level, the comparator 1 outputs a low level, R =0, S =0, Q =0, the RS trigger keeps a low level output, and the state of the monostable trigger is a steady state.
In this embodiment, the pulse time of the rectangular wave can be accurately controlled by using the counter, so that the transient time of the monostable flip-flop can be accurately controlled. The carry value of the counter comprises at least any one of binary, quinary, decimal and hexadecimal, the counter can divide the frequency of a clock signal based on the set carry value, outputs a pulse signal with corresponding time length, utilizes multi-time triggering to clear the counter, prolongs the overturning time of the RS trigger responding to the pulse signal, and can also utilize a feedback clearing method or a feedback numbering method to construct a counter with any system, so as to realize more flexible control of the transient time of the monostable trigger.
A control method of a monostable trigger capable of being triggered for multiple times comprises the following specific control processes:
when the circuit is started, the 0 end of the RS trigger is set to be at low level, and the RS trigger outputs the low level. The capacitor connected with the 0 end is connected with a power supply through a resistor for charging, the capacitor becomes a high level, the 0 end does not work any more, and the RS trigger works normally;
the low level output of the carry terminal of the counter is connected with the non-inverting terminal of the comparator 1, the 2/3V voltage division point is electrically connected with the inverting input terminal of the comparator 1, the low level output of the comparator 1 is connected with the R input terminal of the RS trigger,
the trigger signal is input with high level and is connected with the inverting input end of the comparator 2, the 1/3V voltage division point is electrically connected with the non-inverting input end of the comparator 2, the comparator 2 outputs low level, and the output of the RS trigger keeps low level.
When a trigger signal is input into a level, a low-level pulse appears, the voltage of the in-phase input end of the comparator 2 is unchanged, the comparator 2 outputs a high level, the S input end of the RS trigger is changed into a high level, the level of the R input end of the RS trigger is unchanged and is a low level, the RS trigger outputs a high level, and the counter starts to count;
the trigger signal inputs signals, low-level pulses appear, high-level pulses are output through the NAND gate 1, the JK trigger JK1 outputs high levels, and the JK trigger JK2 outputs signals keeping low levels unchanged; JK triggers JK2 and JK1 are 01;
the trigger signal is input again, a low-level pulse appears, the low-level pulse is output through the NAND gate 1, the JK trigger JK1 outputs a low level, and the JK trigger JK2 outputs a high level; JK triggers JK2 and JK1 are 10;
the trigger signal is input again, a low-level pulse appears, the low-level pulse is output through the NAND gate 1, the JK trigger JK1 outputs a high level, and the JK trigger JK2 outputs a high level; JK triggers JK2 and JK1 are 11;
the three states of the JK triggers JK2 and JK1 clear the counter through the NAND gate, the counter counts again, and the transient time is prolonged;
when the JK triggers JK2 and JK1 are 11, outputting low level through the NAND gate 23, and limiting the low level triggering times of the input end;
the input level of the trigger signal is restored to be high level, the comparator 2 outputs low level, the S input end of the RS trigger is changed into low level, the level of the R input end of the RS trigger is not changed and is low level, and the RS trigger keeps high level output. The state of the monostable flip-flop is transient at this time.
The counter finishes preset counting, the carry end outputs high level, the carry end of the counter is connected with the non-inverting input end of the comparator 1, the 2/3V voltage division point is electrically connected with the inverting input end of the comparator 1, the voltage of the non-inverting input end of the comparator 1 is higher than that of the inverting input end of the comparator 1, and the comparator 1 outputs high level and is connected with the R input end of the RS trigger; the output of the RS trigger is low level, and is simultaneously connected with the enabling end of the counter, the counter outputs low level, the comparator 1 outputs low level, the RS trigger keeps low level output, and at the moment, the monostable trigger is in a stable state. The process of the invention is further illustrated below with reference to specific examples.
The RS trigger is set to be effective at the low level at the 0 end, when the circuit is started, the voltage of a capacitor connected with the 0 end is 0V, the RS trigger outputs the low level, and meanwhile, the RS trigger is connected with the enabling end of the counter, and the counter outputs the low level. The capacitor is connected with a power supply through a resistor for charging, the capacitor becomes a high level, the 0 end does not work any more, and the RS trigger works normally;
the comparator 1 outputs a low level, and the R input end is the low level; the comparator 2 outputs a low level, and the S input end is the low level; the output state of the RS trigger is kept at a low level;
when a trigger signal is input into a level, a low-level pulse appears, the voltage of the in-phase input end of the comparator 2 is unchanged, the comparator 2 outputs a high level, the S input end of the RS trigger is changed into a high level, the level of the R input end of the RS trigger is unchanged and is a low level, the RS trigger outputs a high level, and the counter starts to count;
the trigger signal inputs signals, low-level pulses appear, high-level pulses are output through the NAND gate 1, the JK trigger JK1 outputs high levels, and the JK trigger JK2 outputs low levels; JK triggers JK2 and JK1 are 01;
the trigger signal is input again, a low-level pulse appears, the low-level pulse is output through the NAND gate 1, the JK trigger JK1 outputs a low level, and the JK trigger JK2 outputs a high level; JK triggers JK2 and JK1 are 10;
the trigger signal is input again, a low-level pulse appears, a high-level pulse is output through the NAND gate 1, the JK trigger JK1 outputs a high level, and the JK trigger JK2 outputs a high level; JK triggers JK2 and JK1 are 11;
the three states of the JK triggers JK2 and JK1 clear the counter through the NAND gate, the counter counts again, and the transient time is prolonged;
when the JK triggers JK2 and JK1 are 11, outputting low level through the NAND gate 23, and limiting the low level triggering times of the input end;
the input level of the trigger signal is restored to be high level, the comparator 2 outputs low level, the S input end of the RS trigger is changed into low level, the level of the R input end of the RS trigger is not changed and is low level, and the RS trigger keeps high level output. The state of the monostable flip-flop is transient at this time.
The counter finishes preset counting, the carry end outputs high level, the carry end of the counter is connected with the non-inverting input end of the comparator 1, the 2/3V voltage division point is electrically connected with the inverting input end of the comparator 1, the voltage of the non-inverting input end of the comparator 1 is higher than that of the inverting input end of the comparator 1, and the comparator 1 outputs high level and is connected with the R input end of the RS trigger; the output of the RS trigger is low level, and is simultaneously connected with the enabling end of the counter, the counter outputs low level, the comparator 1 outputs low level, the RS trigger keeps low level output, and the state of the monostable trigger is steady state.
The n-system of the counter can be set through the counter, the setting method comprises a zero clearing mode and a number setting mode, the setting of the counter is carried out through the dial switch and the NAND gate 8, the single-chip four-bit counter can complete the hexadecimal system at most, the two pieces of four-bit counters can complete the sixty-four system at most, and the counters can be connected in series to complete more system systems. The period of the carry signal is n times the period of the clock signal. The counter is fully digitalized after being set, and the digital control of the monostable trigger is completed by setting the counter.
Claims (5)
1. A monostable trigger capable of triggering for many times is characterized by comprising a comparator two inverted phase input end serving as an input end, a Q end of an RS trigger serving as an output end, a non-inverted phase input end of a comparator one and a digital control circuit;
the input end of the monostable flip-flop is simultaneously and electrically connected with the NAND gate 1 to provide rising edge signals for the JK flip-flops JK1 and JK2, the low level triggering times of the input end are limited by the NAND gate 2, and the counter is cleared by the NAND gate 3;
the digital control circuit comprises a multivibrator and a counter, wherein the multivibrator is electrically connected with a clock signal input end of the counter, and a carry output of the counter is electrically connected with a non-inverting input end of the first comparator;
the input end of the RS trigger is electrically connected with the inverted input end of the second comparator;
the power supply is connected with a plurality of resistors in series and is grounded, the resistance values of the resistors are equal, each resistor occupies one of the divided power supply voltages, one resistor is connected with the non-inverting input end of the second comparator, and the rest resistors are connected with the inverting input end of the first comparator.
2. The flip-flop of claim 1, wherein said counter carries values comprising binary, quinary, decimal, and hexadecimal.
3. The multi-strike monostable according to claim 1, wherein the multivibrator includes nand gate 4 and nand gate 5 connected in series, the nand gate 4 is connected in parallel with a resistor, the nand gate 4 and the nand gate 5 are connected in parallel with a capacitor, and the nand gate 5 is electrically connected to the clock signal input of the counter.
4. A method of controlling a multi-triggerable monostable flip-flop according to any one of claims 1 to 3, characterised by the steps of:
(1) The carry end of the counter is connected with the non-inverting input end of the first comparator, the 2/3V voltage division point is electrically connected with the inverting input end of the first comparator, and the carry end of the counter outputs a low level; the voltage of the non-inverting input terminal of the comparator I is lower than that of the inverting input terminal of the comparator I, and the comparator I outputs a low level; the R input end of the RS trigger is connected;
(2) The 1/3V voltage division point is connected with the non-inverting input end of the second comparator, the triggering signal input end is connected with the inverting input end of the second comparator, and the triggering signal is at a high level when stable; the voltage of the non-inverting input terminal of the comparator II is lower than that of the inverting input terminal of the comparator II, and the comparator II outputs a low level; the S input end of the RS trigger is connected;
(3) The RS trigger is set to be effective at a low level at the 0 end, when the circuit is started, the voltage of a capacitor connected with the 0 end is 0V, the RS trigger outputs the low level and is simultaneously connected with the enabling end of the counter, and the counter outputs the low level; the capacitor is connected with a power supply through a resistor for charging, the capacitor becomes a high level, the 0 end does not work any more, and the RS trigger works normally;
(4) The comparator I outputs a low level, and the R input end is the low level; the second comparator outputs a low level, and the S input end is the low level; the output state of the RS trigger is kept at a low level;
(5) The trigger signal inputs the level, the low level pulse appears, the voltage of the non-inverting input end of the comparator II is unchanged, the comparator II outputs the high level, the S input end of the RS trigger is changed into the high level, the level of the R input end of the RS trigger is unchanged and is the low level, the RS trigger outputs the high level, and the counter starts to count;
(6) The input level of the trigger signal is restored to be high level, the second comparator outputs low level, the S input end of the RS trigger is changed into low level, the level of the R input end of the RS trigger is not changed and is low level, and the RS trigger keeps high level output; the state of the monostable trigger is transient;
(7) The input end is electrically connected with the NAND gate 1 at the same time, rising edge signals are provided for JK triggers JK1 and JK2, the low level triggering times of the input end are limited through the NAND gate 2, the counter is cleared through the NAND gate 3, the counter counts again, and the transient time is prolonged;
(8) The counter finishes preset counting, the carry end outputs high level, the carry end of the counter is connected with the same-phase input end of the first comparator, the 2/3V voltage division point is electrically connected with the reverse-phase input end of the first comparator, the voltage of the same-phase input end of the first comparator is higher than that of the reverse-phase input end of the first comparator, and the first comparator outputs high level and is connected with the R input end of the RS trigger; the output of the RS trigger is low level, and is simultaneously connected with the enabling end of the counter, the counter outputs low level, the comparator outputs low level, the RS trigger keeps low level output, and the monostable trigger is in a steady state.
5. The method as claimed in claim 4, wherein the carry value of the counter in step (1) is obtained by a feedback zero clearing method and/or a feedback digit setting method.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210905223.7A CN115276609A (en) | 2022-07-29 | 2022-07-29 | Monostable trigger capable of being triggered for multiple times and control method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210905223.7A CN115276609A (en) | 2022-07-29 | 2022-07-29 | Monostable trigger capable of being triggered for multiple times and control method thereof |
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| CN115276609A true CN115276609A (en) | 2022-11-01 |
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| CN202210905223.7A Withdrawn CN115276609A (en) | 2022-07-29 | 2022-07-29 | Monostable trigger capable of being triggered for multiple times and control method thereof |
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Application publication date: 20221101 |