JP2822680B2 - Signal detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal detection circuit for a dual tone multi-frequency (Dual Tone Multi-frequency) signal and the like. To a signal detection circuit.

[0002]

2. Description of the Related Art In recent years, with the development of advanced information communication networks represented by ISDN, various types of data have been exchanged via telephone lines. In recent years, tone signals (so-called push-tone signals) occupy a large number of telephone selection signals (telephone number signals) in which the dial pulse signal system has been the mainstream in the past, and dual tone multi-frequency ( Hereinafter, "DTM
The signal has been used not only as a telephone number but also as an instruction signal for, for example, home automation using a telephone. In such a background, it is required to make a signal detection circuit for a DTMF signal or the like so as to be small in size and to obtain high reliability. Of integrated circuits is increasing.

[0003] Here, the DTMF signal means that two different frequencies of a row side (low group frequency side) and a column side (high group frequency side) are simultaneously output to a telephone line or the like as shown in Table 1. Then, according to the combination of the two types of frequencies, “0” to “9”, “A”, “B”, “C”, “D”
This signal specifies the alphanumeric characters and the symbols “#” and “*”, and is used as a telephone number signal of a telephone. Normally, as shown in Table 1, four types of predetermined frequencies are used for each of the row side and the column side.

[0004]

[Table 1]

For example, a DTMF receiver that receives and detects this DTMF signal detects the input DTMF signal separately on the row side and the column side, and then detects the row side and the column side as shown in Table 1. From the frequency, a symbol corresponding to the frequency is notified and output to the outside using, for example, a 4-bit code. This DTMF
For the receiver, in order to prevent malfunction due to dropout of the received signal, etc., whether the duration of the tone signal, which is the received frequency signal, and the duration of the pause, in which the frequency signal is in the no-signal state, have reached the specified time, respectively. A circuit is provided for determining whether or not the determination is affirmative.

Hereinafter, as an example of a conventional signal detection circuit,
The determination of the tone and the pause time of the DTMF receiver shown in FIG. 3 will be described with reference to the timing chart of FIG.

In FIG. 3, when no DTMF signal is input, both the ST terminal 17 and the EST terminal 18 are at a low level. The EST terminal 18 is connected to the ST terminal 17 via the external resistor 22.
Since the external capacitor 21 is connected to the power supply VDD via the external capacitor 21, the external capacitor 21 is in a charged state. At this time, the "IRQ" terminal 19 is at the high level.
(For convenience, logical negation is replaced by ""
And "". For example, "IRQ"
Is expressed as “IRQ”. (However, in the figure, an overline is added to indicate a logical negation as in a normal example.) Next, the DTMF receiver 1 is input through the input terminal 20.
The DTMF signal input to 5 has two different frequency bands.
After being separated into a column-side high-group frequency signal and a row-side low-group frequency signal by two band-pass filters (BPFs) 23 and 24, a high-group frequency detection circuit 25 using a digital counting method or the like and a low-group frequency Detection circuit 26
Detects the presence or absence of each frequency signal. Only when frequency signals are continuously detected in both the high and low groups,
T generation circuit 27 with a delay input from a time t ₁ of the DTMF signal, the EST terminal 18 to a high level. At this time, the inputted DTMF signal is continuously and EST terminal 18 becomes a high level, the electric charge stored in the external capacitor 21 is discharged, the potential of the ST terminal 17, shown in T ₁ interval of FIG. 4 And so on. And D
If the TMF signal continues to be input for a certain period of time t ₂ ,
The potential of ST terminal 17 reaches threshold potential V _TST . This is determined by the tone / pause time determination circuit 16, and the "IRQ" terminal 19 becomes low level to notify the outside that the DTMF signal has been received for a specified time or more. The "IRQ" terminal 19 returns to the high level by the tone / pause time determination circuit 16 after a certain period from the low level. The ST terminal 17 outputs “IR” based on the output of the tone / pause time determination circuit 16.
Q "terminal 19 goes low and at the same time goes high (VDD level).

Next, if the DTMF signal is interrupted by dropout or the like after the determination of the specified time, FIG.
As shown in the T ₂ period, the potential of the EST terminal 18 becomes a low level, the potential of the ST terminal 17 is required time to charge the external capacitor 21, the potential of the ST terminal 17 V
If the DTMF signal is input again before the _TST is reached, the valid signal reception state of the previous DTMF signal is maintained and “I
RQ "terminal 19 remains at the high level. When the DTMF input signal is stopped as shown in T ₄ section of FIG. 4, EST terminal 18 becomes a low level with a delay of t ₃ from the input stop. At the initiated charge the external capacitor 21 at the same time, ST terminal 1 after a certain time t ₄
The potential of 7 reaches _VTST , and the tone / pause time determination circuit 16 recognizes the effective pause length and sets the potential of the ST terminal 17 to low level. Tone / pause time determination circuit 16
Once the effective pause is recognized, the reception of the DTMF signal through the "IRQ" terminal 19 is not notified to the outside unless the DTMF signal is input next and the potential of the ST terminal 17 reaches _VTST . In this case, the tone effective time length T _REC and the pause effective time length T _ID are represented by the following Expressions 1 and 2.

[0009]

## EQU1 ## T _REC = t ₁ + t ₂

[0010]

T _ID = t ₃ + t _{4 In} these Equations 1 and 2, t ₁ is the time required for detection after the DTMF signal is input, and t ₃ is the time required for detection after the DTMF signal is stopped. It is time, and each is almost constant, but t ₂ and t ₄ are expressed by the following Expressions 3 and 4 using the resistance value R of the external resistor 22 and the capacitance value C of the external capacitance 21. It shows that it changes by R and C.

[0011]

T ₂ = R · Cln (VDD / (VDD−V _TST ))

[0012]

T ₄ = R · Cln (VDD / V _TST ) (In Equations 3 and 4, InX represents the natural logarithm of X.)

[0013]

In the above-described conventional signal detection circuit, a capacitor and a resistor are connected outside the signal detection circuit to determine the time of the received tone and pause, and the time for charging and discharging them is determined. Therefore, when the signal detection circuit is configured by an integrated circuit, an external terminal and a resistor and a capacitor connected to the outside are required. For this reason, the conventional signal detection circuit has a disadvantage that the number of terminals increases and the cost of external components increases. In this case, the determination time is determined using the external resistance value and the external capacitance value, and is determined using a so-called analog determination method. And the determination time fluctuates depending on the use environment of the signal detection circuit, for example, a change in resistance value and capacitance value due to the influence of temperature.

The present invention has been made in view of the above problems, and does not require external resistors and external capacitors, can reduce the number of terminals, can be easily integrated into a circuit, and can achieve high precision. It is another object of the present invention to provide a signal detection circuit in which the determination time does not change due to the influence of manufacturing variations and the use environment even when the circuit is integrated.

[0015]

According to the present invention, there is provided a signal detecting circuit for detecting a frequency signal, wherein a logical value is inverted when the presence of the frequency signal is detected and when the presence of the frequency signal is not detected. Means for generating a detection signal, a means for generating a pulse signal each time the logical value of the detection signal is inverted, a means for generating a reset signal each time the pulse signal is generated, and a means for resetting by the reset signal. A binary counter for counting a clock signal input from the outside; a unit for holding a count-up signal of the binary counter each time the detection signal indicates the presence of a frequency signal; and a detection signal and a count-up signal of the binary counter. A logic gate for calculating the logical product of the count-up signal and the signal held by the count-up signal; There by changing the output which varies,
Means for notifying the outside that the frequency signal has been detected.

[0016]

In the signal detection circuit of the present invention, a binary counter for digitally counting clocks is used to determine the tone time length and pause time length of the DTMF input signal. When configuring, external resistors and external capacitors are unnecessary,
The number of terminals can also be reduced. Further, since the judgment time of the tone time length and the pause time length is determined by the frequency of the input clock signal of the binary counter and the number of stages of the binary counter, it can be set very accurately, and the influence of manufacturing variations. Also, the determination time does not change due to the influence of the use environment.

[0017]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a configuration of a tone / pause time determination circuit of a DTMF receiver configured using a signal detection circuit according to one embodiment of the present invention. The judgment circuit shown in FIG. 1 includes the tone / pause time judgment circuit 16 shown in FIG.
And used in place of the external resistor 22.

The decision circuit shown in FIG.
D-flip-flops 2 to 5, AND gates 6, 10,
It has NOR gates 7 and 9 and an OR gate 8.
The binary counter 1 counts the tone and pause time length. However, at this time, the clock input CK of the binary counter 1 is the clock signal 12 and the binary counter 1
Is connected to the output of the OR gate 8 to which the count-up signal output from the CRY terminal is input. The D-flip-flop 2 receives the EST signal 11 as the data input D.
And the clock signal 12 is input as the clock input CK. The AND gate 6 outputs the EST signal 1
1 and the "Q" output of the D-flip-flop 2 are input, and a pulse (hereinafter referred to as "EST") at each rising edge of the EST signal.
↑ signal ”). The NOR gate 7 has E
The ST signal 11 and the "Q" output of the D-flip-flop 2 are input, and a pulse (hereinafter, referred to as "pulse") at each falling edge of the EST signal.
"EST ↓ signal"). The NOR gate 9 receives an EST # signal as a rising signal of the EST signal and an EST ↓ signal as a falling signal of the EST signal. The D-flip-flop 3 receives the output signal of the NOR gate 9 as the data input D and the clock signal 12 as the clock signal CK.
The Q output is used as the reset input "R" of the binary counter 1.
Give to. Further, the D-flip-flop 4 outputs AND signal which is a rising signal of the EST signal as the clock input CK.
The output of the gate 6 is input, the count-up signal of the binary counter 1 is input as the data input D, and Q ₁
Output a signal. The 3-input AND gate 10 has EST
Signal 11, count-up signal of binary counter 1,
The Q ₁ signal which is the Q output of the D-flip-flop 4 is input. The D-flip-flop 5 is resettable, receives the output signal of the 3-input AND gate 10 as the clock input CK, and the VDD level as the data input D, and outputs the “Q” output to the “IRQ” signal 13. And output to the outside. The reset input "R" of the D-flip-flop 5 is externally input as an "IRQ" reset signal 14. FIG. 1 does not show a DTMF signal detection unit for simplification of the description.

Next, the operation of the circuit of this embodiment will be described with reference to the timing chart shown in FIG.

In the initial state, the D flip-flop 5 is reset by the "IRQ" reset signal 14, and the "Q" output is at a high level.

When the DTMF signal is not input to the DTMF receiver, the EST signal 11 is at a low level, and the output of the AND gate 10 is at a low level.
Since the clock input CK of the D-flip-flop 5 remains at the low level, the output of the D-flip-flop 5 does not change, and the “IRQ” signal 13 is at the high level. The count-up signal from the CRY terminal of the binary counter 1 is at a high level indicating a count overflow.

Next, when a DTMF signal is input to the DTMF receiver, the DTMF signal is separated and detected on the row side and the column side, respectively, and effective frequencies are detected on both the row side and the column side. The EST signal 11 changes from the low level to the high level with a delay of t _a1 from the input of the DTMF signal. When the EST signal 11 changes to a high level, the D-flip-flop 2 and the AND gate 6
Accordingly, a rising pulse or EST ↑ signal EST signal as shown in T ₁ interval of 2 is generated. When the EST signal is generated, the output of the NOR gate 9 goes low, so that a low-level pulse is input to the reset input “R” of the binary counter 1 via the D-flip-flop 3, and the binary counter 1 Is reset and starts counting at the same time. At this time, D- flip flop 4 at the rising edge of the EST ↑ signal, so to retain the high level of CRY output of the binary counter 1, Q ₁ signal becomes high level. Then, the binary counter 1 counts up each time the clock signal 12 changes, counts up by a preset count number, and when it overflows, outputs a high level to the CRY terminal. In this case, the time t _a2 from when the binary counter 1 is reset to when the high level is output to the CRY terminal is determined by the input clock frequency of the binary counter and the number of stages of the binary counter. When 384 kHz and the number of stages of the binary counter is 8, t _a2 = 1 / 16.384 kHz ×
2 ⁸ = 15.625 ms.

When the CRY terminal goes high, EST
Signal, since the Q ₁ signal is already high, AN
The output of the D gate 10 changes from the low level to the high level, the “Q” output of the D-flip-flop 5 changes from the high level to the low level, and the DTMF signal is input via the “IRQ” signal 13 for a specified time or more. They are notified of what has been done. After that, the D-flip-flop 5 is reset by the "IRQ" reset signal 14, and the "IRQ" signal 13 is kept at a high level. The tone effective time length T _{REC at} this time is T _REC = t _a1 + t
_a2 .

Next, when the DTMF signal is less than the prescribed time is input, as shown in T ₅ section of FIG. 2, D
After the input of the TMF signal, the EST signal changes from the low level to the high level, and at the same time, the binary counter 1 is reset and starts counting. However, DTM
The input of the F signal is stopped before the binary counter 1 overflows.
Since the Y terminal remains at the low level and the AND gate 10 maintains the low level, the clock input CK of the D-flip-flop 5 does not change, and as a result, the "IRQ" signal remains at the high level.

Next, the determination of the pause time will be described.

When the continuously input DTMF signal stops, as shown in the section T _{4 in} FIG.
Changes from the high level to the low level with a delay of t _b1 from the stop of the input of the DTMF signal. At the same time, the EST ↓ signal is generated by the D-flip-flop 2 and the NOR gate 7, and the output of the NOR gate 9 becomes low level, so that the reset signal is input to the binary counter 1 via the D-flip-flop 3. Then, the binary counter 1 starts counting as soon as it is reset.

Then, the binary counter 1 sequentially counts up the clock signal 12 and counts it by a preset count number. When an overflow occurs, a high level is output to the CRY terminal. In this case, the time t _b2 from when the binary counter 1 is reset to when the high level is output to the CRY terminal is the same as the time t _a2 . If the CRY terminal of the binary counter 1 outputs a high level, the pause time is valid, and the valid time length T _ID of the pause is T _ID = t _b1 + t _b2 .

[0029] At this time, as shown in T ₅ or T ₇ section of FIG. 2, EST signal 11 is input following DTMF signal is changed from low level to high level, the EST ↑ signal is generated, D -The flip-flop 4 holds the high level at the same time as the rise of the EST # signal. Therefore, when the DTMF signal is input for more than the specified time (t _a1 + t _a2 ) and the CRY terminal of the binary counter 1 goes high as in the section T ₇ , the “IRQ” signal 13 of the D-flip-flop 5 goes low. Level and DTM
The input of the F signal is notified to the outside again.

[0030] Finally, if the pause time is less than the specified time, simultaneously with the input stop of DTMF signals as shown in T ₂ section of FIG. 2, by EST signal 11 changes from the high level to the low level , D-flip-flop 2 and NOR gate 7 generate an EST ↓ signal, and a reset signal is input to binary counter 1 through NOR gate 9 and D-flip-flop 3.
For this reason, the binary counter 1 is reset and starts counting again. However, if the pause time is shorter than the time t _b2 , the CRY terminal of the binary counter 1 remains at the low level, so that T _{3 in} FIG. As shown in the section, when the next DTMF signal is input and the EST signal 11 changes from the low level to the high level, and the EST signal is generated, the D-flip-flop 4 outputs the EST signal at the same time as the rise of the EST signal. The low level will be maintained. Therefore, even if the DTMF signal is input for more than the specified time (t _a1 + t _a2 ) and the CRY terminal of the binary counter 1 is at the high level, the output of the AND gate 10 remains at the low level. the output of flop 5 does not change, "IRQ" signal 13 will be maintained at a high level, the T ₂ period pose 2 will have been determined to be invalid.

Although the DTMF receiver has been described in this embodiment, it is apparent that the present invention can be applied to other signal detection circuits in substantially the same manner.

As described above, in the signal detection circuit, D
Since a binary counter that counts digitally is used to determine the tone time length and the pause time length of the TMF input signal, it has been conventionally required even when a signal detection circuit is configured by an integrated circuit. This eliminates the need for external resistors and external capacitors, and reduces the number of terminals, making it very easy to configure this chip including this determination circuit on a single chip. As a result, the signal detection circuit and external components This has the effect of reducing the cost. Further, since the determination time of the tone time length and the pause time length is determined by the frequency of the input clock signal of the binary counter and the number of stages of the binary counter, it can be set very accurately. , The determination time does not change under the influence of manufacturing variations or the use environment.

[0033]

As described above, according to the present invention, an external resistor and an external capacitor are not required, the number of terminals can be reduced, and an integrated circuit can be easily formed with high precision. In addition, it is possible to provide a signal detection circuit in which the determination time does not change due to the influence of manufacturing variations and the use environment even when integrated.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a tone / pause time determination circuit of a DTMF receiver configured using a signal detection circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of an example of a conventional DTMF receiver.

FIG. 4 is a timing chart for explaining the operation of the circuit of FIG. 3;

[Explanation of symbols]

 1; binary counters 2 to 5; D-flip-flops 6 and 10; AND gates 7 and 9; NOR gates 8; OR gates 11, 12, and 14;

Claims (1)

(57) [Claims] 1. A signal detection circuit for detecting a frequency signal, comprising: means for generating a detection signal whose logical value is inverted when the presence of the frequency signal is detected and when the presence of the frequency signal is not detected, and Means for generating a pulse signal each time a logical value is inverted; means for generating a reset signal each time the pulse signal is generated; and a binary counter for counting a clock signal reset by the reset signal and input from the outside. Means for holding a count-up signal of the binary counter each time the detection signal indicates the presence of a frequency signal; and logic of the detection signal, the count-up signal of the binary counter, and the signal held by the count-up signal. A logic gate that takes a product, and changing the output every time the output of the logic gate changes, Means for notifying the outside that a signal has been detected.