JPH0537573A - Data interruption detection circuit - Google Patents

Abstract

PURPOSE:To set a data interruption detection time of the data interruption detection circuit to a desired time by setting the data interruption detection time by a digital circuit. CONSTITUTION:When a data (a) is inputted from a data input terminal 1, an output (b) of a comparator 3 goes to H. Then an output (d) of a circuit 4 is logical H because the output (b) of the comparator 3 is a set signal. When the output (d) of the counter circuit 4 goes to logical H, an AND circuit 5 outputs a clock signal inputted from a clock input terminal 2 to the counter circuit 4. While the data (a) is inputted, since the set signal is always inputted to the counter circuit 4, the output (d) of the counter circuit 4 keeps an H level. When the data (a) is lost, the output of the comparator 3 goes to L and no set signal is inputted to the counter circuit 4, then the set clock number is counted to set the output to L and the data interruption is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data break detection circuit realized by a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a receiving circuit of a digital data transmission apparatus, there are cases where a function of detecting the presence or absence of received data and outputting a data break detection signal, or fixing various output signals is required. As a method of determining the presence or absence of data, a method of determining that the data is broken when the data is not identified within a fixed time is widely used.

FIG. 4 shows an example of a conventional data loss detection circuit. The conventional data loss detection circuit has a resistor 7 and a capacitor 8
From the reference voltage generating circuit 6, the voltage comparator 3 for comparing the voltage of the reference voltage generating circuit 6 with the voltage of the input data signal, and the voltage comparator 33 for comparing the output of the integrator 70. It is configured.

Next, the operation will be described. For the sake of explanation, the transmission code is assumed to be a CMI code. In FIG.
When the data a is input from the data input terminal 1 and the voltage of the data input becomes higher than the reference voltage 6, the voltage comparator 3
Output b becomes high level. When the voltage of the reference voltage 6 is set slightly higher than the intermediate level, the data reception signal is as shown in FIG.
As shown in (b), a high level signal for a certain period or more is output within a certain period, but it is fixed at a low level when data is disconnected. When the output signal b of the voltage comparator 3 shown in FIG. 5B is integrated by the integrator 70, a waveform c as shown in FIG. 2C is obtained. That is, at the time of the data signal, the voltage higher than the voltage of the reference voltage source 66 is always maintained, and after the data disconnection, it changes to the voltage lower than the voltage of the reference voltage source 66.
The time constant to of this voltage change is determined by the time constant of the integrator 70.

The output d of the voltage comparator 33 outputs a high level when data is received, and a low level when data is disconnected.

[0006]

In the above-mentioned conventional data loss detection circuit, the data loss detection time is set by the time constant of the integrator composed of the resistor and the capacitor. However, there is a drawback that the data loss detection time changes due to the change of, or the layout area becomes large when the resistors and capacitors are realized by the semiconductor integrated circuit.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a novel data loss detection circuit capable of solving the above-mentioned drawbacks inherent in the prior art. To do.

[0008]

In order to achieve the above object, a data break detection circuit according to the present invention comprises a reference voltage generation circuit and a voltage comparison circuit for comparing an output voltage of the reference voltage generation circuit with an input data signal. A, a counter circuit having the output of the voltage comparator as a set input, and the logical product of the output of the counter circuit and the clock signal from the clock input terminal A
And an ND circuit, the output of the AND circuit is connected to the clock input of the counter circuit, and the output of the counter circuit is used as a data disconnection detection signal output.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings, which is a preferred embodiment thereof.

FIG. 1 is a block diagram showing an embodiment of a data break detection circuit according to the present invention.

Referring to FIG. 1, one embodiment of the present invention is
A reference voltage generation circuit 6 for generating a reference voltage, a voltage comparator 3 for comparing the output voltage of the reference voltage generation circuit 6 with the input data signal a, a counter circuit 4 for setting and inputting the output of the voltage comparator 3, and a counter. The AND circuit 5 is configured to AND the output of the circuit 4 and the clock signal from the clock input terminal. The output of the AND circuit 5 is connected to the clock input of the counter circuit 4, and the output of the counter circuit 4 is The feature is that the data disconnection detection signal is output.

When the data a is input from the data input terminal 1, the output b of the comparator 3 becomes "H". At the same time, the output d of the counter circuit 4 outputs "H" because the output b of the comparator 3 becomes a set signal. When the output d of the counter circuit 4 becomes “H”, the AND circuit 5 outputs the clock signal c input from the clock input terminal 2 to the counter circuit 4 as the clock signal e. Since the set signal is always input to the counter circuit 4 while the data a is being input, the output d of the counter circuit 4 holds "H". When the data signal a disappears, the output b of the comparator 3 becomes "L", and the set signal is not input to the counter circuit 4,
The counter circuit 4 counts the set number of clocks, sets the output d to "L", and detects the data disconnection.

FIG. 2 is a block diagram showing a concrete configuration example of the counter circuit 4 according to the present invention shown in FIG.

Referring to FIG. 2, in the present embodiment, the counter circuit 4 is a D-FF (flip-flop) circuit 4.
A divide-by-8 frequency down counter circuit composed of 4, 45 and 46 is used.

Next, the circuit operation will be described with reference to FIG. When the data a is input from the data input terminal 1, since the input voltage level of the data a is higher than the voltage level of the reference voltage 6, the output b of the comparator 3 becomes “H” and the counter circuit 4 is set. To be done. When the counter circuit 4 is set, its output d becomes "H" and one input terminal of the AND circuit 5 becomes "H". Therefore, the output e is the clock signal c from the clock input terminal 2 as the clock signal e. Output. Since the set signal is always input to the counter circuit 4 while the data a is being input, the counter output d is "H" because the setting is prioritized in the counter circuit 4 including the D-FF. Hold. When the data a is no longer input, the output b of the comparator 3 becomes "L", the setting is released, and the counter circuit 4 starts down counting. When the final stage counter 46 becomes "L", the output e of the AND circuit 5 becomes "L", and the first stage counter 44 stops counting.

In this embodiment, after the data signal a is disconnected, the data disconnection signal becomes "L" at the fourth clock signal e.
Becomes In the present embodiment, the number of stages n of the counter circuit is 3
Although the case has been shown, a desired data disconnection time can be set by increasing or decreasing the number of stages n of the counter.

FIG. 3 is a timing chart of the embodiment shown in FIG. 2. The solid line in FIG. 3A is the input data signal a, and the broken line is the output voltage of the reference voltage generating circuit 6. Figure 3
In (a), “0” and “1” indicate CMI codes. (B) is the output b of the comparator 3, and the counter circuit 4
Of the input data a as shown in (a).
Is higher than the output voltage of the reference voltage generation circuit 6, "H"
Is output. (C) is a clock signal c, and (d)
Is the output d of the counter circuit 4, and outputs "L" at the fourth clock signal after the set signal of (c) is no longer input to detect data break. Also, (e) is
It is the output e of the AND circuit 5, and outputs the clock signal only when the output of the counter circuit 4 is "H" as shown in (d).

[0018]

As described above, according to the data break detection circuit of the present invention, the data break detection time is set in the digital circuit and the resistor and the capacitor are not used in the circuit, so that the layout area can be reduced. It is possible to obtain the effect that the data disconnection detection time can be made constant regardless of the element deviation of the resistor or the capacitor.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data break detection circuit according to the present invention.

FIG. 2 is a block diagram showing details of a counter circuit in the embodiment of the present invention shown in FIG.

FIG. 3 is an operation timing chart of the embodiment according to the present invention.

FIG. 4 is a block diagram of a conventional data loss detection circuit.

FIG. 5 is a timing chart of a conventional data disconnection detection circuit.

[Explanation of symbols]

1 ... Data input terminal 2 ... Clock input terminal 3, 33 ... Comparator 4 ... Counter circuit 44, 45, 46 ... D-FF circuit 5 ... AND circuit 6, 66 ... Reference voltage generator 7 ... resistance 70 ... integrator 8 ... Capacitor

Claims (2)

[Claims] 1. A reference voltage generating circuit, a voltage comparator for comparing an output voltage of the reference voltage generating circuit with an input data signal, a counter circuit having a set input of the output of the voltage comparator, and a counter circuit of the counter circuit. An AND circuit that takes a logical product of the output and the clock signal from the clock input terminal, the output of the AND circuit is connected to the clock input of the counter circuit, and the output of the counter circuit is used as the data loss detection signal output. A data loss detection circuit characterized by: 2. The counter circuit is composed of n D-type flip-flops, and the number of stages of the flip-flops is n.
The data break detection circuit according to claim 1, further characterized by setting the data break time by.