JPH0595379A - Tone signal detection circuit - Google Patents

Abstract

PURPOSE:To detect a tone signal by low power consumption in accordance with a simple circuitry, regarding a tone signal detection circuit for detecting the tone signal constituted by the repeating of 2N times high level value and the subsequent 2N times low level value. CONSTITUTION:This circuit is provided with a counter circuit 1 counting a clock signal and an exclusive OR circuit 3 calculating the exclusive OR of 2N bit output of this counter circuit 1 and a binarized tone signal. By applying a constitution that the enable state of the counter circuit 1 is controlled and the setting of the initialization value of a count value is controlled in accordance with the output value of this exclusive OR, the detection result of a tone signal is outputted by the output mode of 2N<+1> bit output of the counter circuit 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention provides a high-level value of 2 ^N times relates the tone signal detecting circuit for detecting a tone signal composed of 2 ^N iterations of the low-level value that follows, in particular, The present invention relates to a tone signal detection circuit that can detect a tone signal with low power consumption according to a simple circuit configuration.

In a training sequence using the American standard 2B1Q code, eight symbols of 80 kbps (+
3, +3, +3, +3, -3, -3, -3, -3) is defined as a tone signal, and a training start is notified to the other party using this tone signal. It is necessary to realize such tone signal detection with a simple circuit configuration, and since it must function to detect the notification of training start even before the start of training. It is necessary to realize it with a circuit configuration that can reduce power consumption.

[0003]

2. Description of the Related Art Conventionally, such tone signal detection is
A method using a bandpass filter has been adopted. That is, a method of extracting and detecting a tone signal by using an analog bandpass filter and a method of extracting and detecting a tone signal by using a digital bandpass filter have been used.

[0004]

However, in the method of extracting and detecting the tone signal by using the analog bandpass filter, a high precision analog filter is required and the circuit configuration becomes complicated. was there.
Further, the method of extracting and detecting a tone signal by using a digital bandpass filter has a problem that the circuit configuration becomes complicated because an A / D converter and a digital filter are required, and it is low. There is a problem that power consumption cannot be realized.

[0005] The present invention was made in view of such circumstances, the high level value of 2 ^N times, the tone signal formed by repeating the subsequent 2 ^N times the low-level value, a simple circuit structure Accordingly, it is an object of the present invention to provide a new tone signal detection circuit that enables detection with low power consumption.

[0006]

FIG. 1 illustrates the principle configuration of the present invention. In the figure, the counter circuit 1 which counts the clock signal, 2 is an analog comparator, binarizes the tone signal formed by 2 ^N times high value and 2 ^N iterations of the low-level value followed by What to do, 3
Is an exclusive OR circuit, and is an analog comparator 2
Is calculated and the exclusive OR value of the 2 ^N- bit output value of the counter circuit 1 is calculated and input to the enable terminal and the load terminal of the counter circuit 1.

The counter circuit 1 has an enable terminal (E
When a high level value is input to N), the clock signal is counted, and the output value of the 2 ^J- bit output terminal (0 ≦ J ≦ N + M + 1) is determined and output according to the counted value.
Then, when the low level value is input to the load terminal (XL), the zero value designated by the data input terminals (D _{0 to DN + M + 1} ) set to the low level value is initialized to the initial value. Read as a value.

[0008]

In the present invention, the analog comparator 2 binarizes the tone signal into a high level value and a low level value by comparing it with a preset judgment level. The binarization, tone signal, 2 a high-level value corresponding to the ^N clock signals fraction, the signal sequence constituted by repeating the low-level value corresponding to 2 ^N clock signal component followed by Will be converted. On the other hand, when the counter circuit 1 starts counting from a zero value and counts 2 ^N clock signals, it changes the output value of the 2 ^N- bit output terminal from a low level value to a high level value, and then 2 ^N
When the number of clock signals is counted, the output value of the 2 ^N- bit output terminal is changed from the high level value to the low level value, and subsequently, when 2 ^N clock signals are counted, the output value of the 2 ^N- bit output terminal is changed. The output process of changing from the low level value to the high level value is repeated.

When a tone signal to be detected is input, the analog comparator 2 first outputs a high level value corresponding to 2 ^N clock signals.
At the time of starting the output, the counter circuit 1 counts the zero value which is the initial value as the count value, and therefore outputs the low level value to the 2 ^N- bit output terminal. In response to these output processes, the exclusive OR circuit 3 outputs a high level value, and in response to this output process, the counter circuit 1 is set to the enabled state and starts counting clock signals, and ^{When the N} clock signals are counted, the output value of the 2 ^N- bit output terminal shifts from the low level value to the high level value.

At the time when the output value of the 2 ^N- bit output terminal changes to a high level value, the analog comparator 2
Starts to output a low level value corresponding to 2 ^N clock signals by binarizing the tone signal, so that the exclusive OR circuit 3 receives the output processing and outputs a high level signal. When the counter circuit 1 continues to output the value and receives the output processing and continues to count the clock signals to count 2 ^N clock signals, the output value of the 2 ^N- bit output terminal changes from the high level value to the low level value. While turning to a value, a high level value is output to the 2 ^{N + 1} bit output terminal.

In this way, the counter circuit 1 is 2 ^N
By outputting the high level value to the 2 ^{N + 1} bit output terminal at the end point of the input of the first tone signal unit composed of the high level value of 2 times and the low level value of 2 ^N times thereafter, The processing is performed so that the detection result for each tone signal is output.

Then, the counter circuit 1 outputs a high level value to the 2 ^{N + M + 1} bit output terminals at the end of inputting the tone signal unit 2 ^M times, thereby
^The processing is performed so that the detection result for each tone signal unit that continues ^M times is output.

As described above, in the present invention, the counter circuit 1
According to a simple circuit configuration consisting of an analog comparator 2 functioning as a 1-bit A / D converter, and an exclusive OR circuit 3, 2 ^N high level values and 2 ^N subsequent low level values It becomes possible to detect a tone signal formed by repeating the above. Then, according to this circuit configuration, the tone signal can be detected with low power consumption.

[0014]

The present invention will be described in detail below with reference to examples. FIG. 2 shows a tone signal used in a transmission device using the American standard 2B1Q code, that is, 8 Kbps.
Symbol (+3, +3, +3, +3, -3, -3,-
3 illustrates an embodiment of the present invention for detecting a tone signal defined by repetition of 3-3).

In the figure, as described with reference to FIG. 1, 1 is a counter circuit, 2 is an analog comparator, and 3 is an exclusive OR circuit. In this analog comparator 2, the 2B1Q code input at the analog level is "+3".
When a level value of 3 is displayed, a high level digital value is output, and when a level value of "-3" is displayed, a low level digital value is output. The exclusive OR circuit 3 calculates an exclusive OR value of the output value of the analog comparator 2 and the output value of the Q ₂ bit output terminal of the counter circuit 1 and inputs it to the enable terminal and the load terminal of the counter circuit 1. It works as it does. When a high-level value is input to the enable terminal (EN), the counter circuit 1 counts and counts up the clock signal at the rising edge of the clock signal input to the clock terminal (CK), It operates to determine and output the output value of the Q _j bit output value (0 ≦ j ≦ 4) according to the count value. Then, when a low level value is input to the load terminal (XL), the zero value designated by the data input terminals (D _{0 to} D ₄ ) set to the low level value is read as the initial value of the count value. Operate.

Next, with reference to the time chart shown in FIG. 3, the operation of the embodiment of FIG. 2 thus constructed will be described. Here, in the time chart of FIG.
The output value of the analog comparator 2 is shown, is the output value of the Q ₂ bit output terminal of the counter circuit 1, and is
The output value of the exclusive OR circuit 3 is shown.

When an analog level tone signal is input, the analog comparator 2 binarizes the tone signal by comparing it with a preset determination level. By this binarization processing, as shown in the time chart of FIG. 3, the tone signal has a high-level value corresponding to four clock signals and a low-level value corresponding to four subsequent clock signals. Will be converted into a signal sequence formed by repeating. On the other hand, the counter circuit 1 starts counting from a zero value and counts four clock signals, as shown in the time chart of FIG. 3, and outputs the output value of the Q ₂ bit output terminal from the low level value to the high level value. When the level value is changed, and then four clock signals are counted, the output value of the Q ₂ bit output terminal is changed from the high level value to the low level value, and subsequently, the four clock signals are counted, The output process of changing the output value of the Q ₂ bit output terminal from the low level value to the high level value is repeated.

When a tone signal to be detected is input, the analog comparator 2 first outputs a high level value corresponding to four clock signals. At the time of starting the output, as shown in the time chart of FIG. 3, the counter circuit 1 counts a zero value which is an initial value as a count value, and therefore outputs a low level value to the Q ₂ bit output terminal. There is. In response to these output processes, the exclusive OR circuit 3 outputs a high level value, and in response to this output process, the counter circuit 1 is set to the enabled state and starts counting clock signals. As shown in the time chart of 3, when counting four clock signals,
The output value of the Q ₂ bit output terminal is changed from a low level value to a high level value.

At the time when the output value of the Q ₂ bit output terminal changes to a high level value, the analog comparator 2
As shown in the time chart of FIG. 3, by binarizing the tone signal, the low level values corresponding to the four clock signals are started to be output. The exclusive OR circuit 3 continues to output a high level value, and in response to this output processing, the counter circuit 1 continues to count clock signals, and when four clock signals are counted, the output from the Q ₂ bit output terminal The value shifts from the high level value to the low level value, and at the same time, the high level value is output to the Q ₃ bit output terminal.

Then, at the time when the output value of the Q ₂ bit output terminal changes to a low level value, the analog comparator 2 binarizes the tone signal as shown in the time chart of FIG. Since the output of the high level value corresponding to the number of clock signals is started, the exclusive OR circuit 3 continues to output the high level value in response to these output processes, and receives the output process. The counter circuit 1 continues counting the clock signals, and when counting the four clock signals, the output value of the Q ₂ bit output terminal shifts from the low level value to the high level value. And this Q ₂
At the time when the output value of the bit output terminal shifts to a high level value, the analog comparator 2 converts the tone signal into a binary signal as shown in the time chart of FIG.
Since the output of the low level value corresponding to the number of clock signals is started, the exclusive OR circuit 3 continues to output the high level value in response to these output processes, and in response to this output process, The counter circuit 1 continues counting the clock signals, and when counting four clock signals, the output value of the Q ₂ bit output terminal shifts from the high level value to the low level value, and the Q ₄ bit output terminal goes high. Output the level value.

In this way, (+3, +3, +3, +
(3, -3, -3, -3, -3) is input twice, the counter circuit 1 outputs a high level value to the Q ₄ bit output terminal to output the tone signal. It operates so that the detection of the signal is displayed externally.

In the time chart of FIG. 3, the exclusive OR circuit 3 is shown as temporarily outputting a low level value because of the timing. However, as shown in FIG. If the output falls within the rising period of the two clock signals, the operation will be as described above.

On the other hand, when the output of the low level value does not fall within the rising section of the two clock signals,
The counter circuit 1 resets the count value so far,
The zero value designated by the data input terminals (D _{0 to} D ₄ ) is read as the initial value of the count value. If such a reset process is executed at the high level value of the tone signal, the output value of the Q ₂ bit output terminal remains at the low level value even when the tone signal next changes to the low level value. Therefore, the reset process is executed again. Then, in response to the output value of the Q ₂ bit output terminal remaining at the low level value, the counter circuit 1 does not start counting operation while the tone signal is at the low level value, When the shifts to the high level value, the above normal counting operation is started. Further, if such a reset process is executed when the tone signal has a low level value, the output value of the Q ₂ bit output terminal becomes a low level value, and the tone signal is kept at a low level value. Does not enter into the counting operation, but enters into the above-mentioned normal counting operation when the tone signal next shifts to the high level value.

In this way, the tone signal can be accurately detected even if the exclusive OR circuit 3 temporarily outputs a low level value due to noise or the like.

[0025]

As described above, according to the present invention,
As described above, according to a simple circuit configuration including the counter circuit, the analog comparator functioning as a 1-bit A / D converter, and the exclusive OR circuit, 2 ^N high-level values and 2 ^N subsequent high-level values are used. It becomes possible to detect the tone signal formed by repeating the low level value of.
Then, according to this circuit configuration, the tone signal can be detected with low power consumption.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an example of the present invention.

FIG. 3 is a time chart of the embodiment of FIG.

[Explanation of symbols]

 1 counter circuit 2 analog comparator 3 exclusive OR circuit

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04Q 1/45 B 9076-5K

Claims (2)

[Claims] 1. A high level value 2 ^N times, followed by 2 high level values.
A tone signal detection circuit for detecting a tone signal formed by repeating a low level value ^N times, the counter circuit (1) counting a clock signal, and a 2 ^N- bit output of the counter circuit (1) And an exclusive OR circuit for calculating an exclusive OR value of the binarized tone signal
(3) and adopting a configuration for controlling the enable state of the counter circuit (1) and controlling the setting of the initial value of the count value according to the output value of the exclusive OR circuit (3), A tone signal detection circuit characterized by being configured to output a detection result of a tone signal according to an output mode of 2 ^{N + 1} bit output of a counter circuit (1). 2. The tone signal detection circuit according to claim 1, wherein the counter circuit (1) does not output the detection result of the tone signal according to the output mode of 2 ^{N + 1} bit output of the counter circuit (1). A tone signal detection circuit characterized in that it is configured to output the detection result of the tone signal according to the output mode of 2 ^{N + M + 1} bits output.