JP2002267726A - Method of determining level of signal, and device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that a level is determined erroneously when a noise is superposed on a signal. SOLUTION: The signal is compared with a reference value by a comparator to generate a binary signal for expressing a relation between their levels, the binary signal is compared plural times with an expected value within a prescribed period, and the level of the signal is determined as not brought within a prescribed range only when a frequency in which the both values thereof are not consistent is a prescribed frequency or more. Erroneous determination is precluded thereby from being generated even when the noise is superposed on the signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for judging a signal level, and more particularly to a signal level judging method and an apparatus suitable for use in a digital function test of an IC inspection apparatus.

[0002]

2. Description of the Related Art In a digital function test of an IC, a driving clock or data is applied to a device under test from a pin driver of the IC testing device, an output of the device under test is taken into the IC testing device by a pin comparator, and an expected value is obtained. Testing is done in comparison with

FIG. 3 shows a level determining apparatus used in such an IC inspection apparatus. In FIG. 3, the device under test (DU)
The output of T) 2 is input to pin comparators 31 and 32. The pin comparator 31 also has V
OH is input, and VOL is input to the pin comparator 32 as a reference value.

A pin comparator 31 determines whether or not the output of the device under test 2 is a high-level signal correctly. The pin comparator 31 compares the output of the device under test 2 with VOH. And a low-level signal when the signal is small. Similarly, the pin comparator 32 determines whether the output of the device under test 2 is correctly outputting a low-level signal. The pin comparator 32 compares the output of the device under test 2 with VOL, and the output is smaller than VOL. And a high level signal is output.

The output of the pin comparator 31 is input to the IN1 terminal of a digital comparator (CMP) 41.
The digital signal EXH is input to the IN2 terminal. Similarly, the output of the pin comparator 32 is input to the IN1 terminal of the digital comparator (CMP) 42,
The digital signal EXL is input to the IN2 terminal. A strobe signal (STRB) is also input to both digital comparators 41 and 42. Digital comparator 4
The outputs of 1, 42 are input to the OR gate 5, and the output becomes a FAIL signal as a determination result.

An expected value is set in EXH and EXL input to the digital comparators 41 and 42. The expected value is described for each rate (RATE) of the test pattern. The expected value is represented by H at a high level, L at a low level, and Z at an intermediate value. The expected values H, L, and Z are represented by 2 bits, and (1, 0), (0, 1),
Take the value of (0,0) and change that value to (EXH,
EXL), if the output of the device under test 2 does not match the expected value, the FAIL signal goes high.

Next, the operation of the level determination device will be described with reference to the time chart of FIG. FIG. 4 shows the rate signal, the output of the device under test 2, the output of the pin comparator 31, the output of the pin comparator 32, the expected value, and the digital comparator 41 from the top.
, The set value EXL, the strobe signal, and the FAIL signal output from the OR gate 5.

The rate signal is a signal that goes high for a short time at the beginning of each rate section. The expected value, EXH,
The set value of EXL changes for each rate. The digital comparators 41 and 42 output 2 at the rising edge of the strobe signal.
The two inputs IN1 and IN2 are compared. The number given to the rate signal is a rate number.

At times t1 and t2, the pin comparator 3
Since the outputs of 1, 32 match the expected value, FAIL
The signal goes low. At time t3, the expected value is H, but the outputs of the pin comparators 31 and 32 are Z.
The IL signal goes high. At time t4, the expected value and the outputs of pin comparators 31 and 32 again match, so that F
The AIL signal goes low. Thus, the output of the device under test 2 can be determined for each rate.

[0010]

However, such a signal level judging device has the following problems.

If noise is superimposed on the output of the device under test 2 for any reason, its level cannot be determined correctly. Since noise is superimposed on the output of the device under test 2 at the rate 6 in FIG. 4, the output of the pin comparator 31 is at a high level during that time. At this time (time t5), since the strobe signal has risen, if there is no noise, the output that should be Z is determined to be H, and the FAIL signal is at the high level. As described above, when the strobe signal rises while the noise is superimposed, there is a problem that an erroneous determination is made.

Further, in order to accurately determine that the output voltage of the device under test is within a certain range, VOH and VOL may be set to close values. There is also a problem that the possibility of erroneous determination is high.

Further, it is conceivable to lower the frequency characteristics of the pin comparators 31 and 32 in order to reduce the influence of noise, but it takes time to stabilize the output signal.
Another problem is that the test time increases when used in an IC test apparatus.

Therefore, the problem to be solved by the present invention is:
It is an object of the present invention to provide a signal level determination method and a signal level determination method that do not make a mistake in determining the level even when noise is superimposed on a signal.

[0015]

In order to solve such a problem, the invention according to claim 1 of the present invention compares a signal level with a reference value and expresses a magnitude relation between the signal level and a reference value.
A signal level determination method for generating a value signal, comparing an expected value with a binary signal in a predetermined cycle, and determining a level of the signal, wherein the expected value and the binary signal are compared at least twice within a predetermined cycle.
The signal level is compared with the value signal, and it is determined that the signal level does not satisfy the predetermined criterion only when the number of mismatches is equal to or greater than a predetermined number. Even if noise is superimposed on the signal, no mistake is made in the determination.

According to a second aspect of the present invention, in the first aspect of the present invention, one or both of the number of times the expected value is compared with the binary signal and the number of times that the criterion is not satisfied within a predetermined period are determined. , Etc., depending on the condition of the signal. Processing according to the situation can be performed.

According to a third aspect of the present invention, there is provided a comparator for comparing a signal with a reference value to generate a binary signal representing a magnitude relationship between the signal and the reference value, a digital comparator for comparing an output of the comparator with an expected value, A majority decision determiner to which the output of the digital comparator is input, the digital comparator compares the expected value with the output of the comparator at least twice within a predetermined time,
The majority decision unit compares the number of times that the comparison result does not match with a predetermined value, and determines that the signal does not satisfy the predetermined criterion only when the number of times that the match does not match is greater. It was made. Even if noise is superimposed on the signal, the determination is not erroneous.

According to a fourth aspect of the present invention, in the third aspect of the present invention, one or both of the number of times the expected value is compared with the output of the comparator within a predetermined time and / or the value determined to be non-matching Is changed according to the state of the signal or the like. Processing according to the situation can be performed.

According to a fifth aspect of the present invention, in the third or fourth aspect, the majority decision unit includes a counter for counting the number of times the expected value and the output of the comparator do not match, and a count of this counter. A digital comparator that compares the value with a predetermined value and outputs the result of the comparison is configured. The majority decision unit can be configured with a simple configuration.

According to a sixth aspect of the present invention, in accordance with the third to fifth aspects of the present invention, there are provided at least two comparators each for comparing a signal with a reference value and a digital comparator for comparing an output of the comparator with an expected value. Used to determine three or more levels of the signal. Complex level determination can be performed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a digital signal level determining apparatus according to the present invention. Note that FIG.
The same elements as those described above are denoted by the same reference numerals, and description thereof is omitted. Figure 1
In the above, 1 is a majority decision unit, and AND gate 1
It comprises a 1, m-bit up counter 12 and an m-bit digital comparator 13.

The output of the OR gate 5 and the strobe 1 signal (STRB1) are input to the AND gate 11.
The output of the AND gate 11 is input to the clock input terminal of the up counter 12. Up counter 1
2, a rate signal (RATE) is input to the reset input terminal (RESET), and the up counter 12 is reset at the beginning of the rate section.

The m-bit count output Qm of the up counter 12 is input to one input terminal Am of the digital comparator 13 and the other input terminal Bm is connected to the m-bit N output terminal.
FAIL is input. Further, the rate signal is input to the clock terminal of the digital comparator 13. The digital comparator 13 outputs the output of the up counter 12 and the NFAI at the rising of the rate signal input to the clock terminal.
L is compared and output as a FAIL1 signal. FAIL
One signal is that the output Qm of the up counter 12 is NFAIL
This is a signal that goes high when it is larger.

Next, the operation of this embodiment will be described with reference to the time chart of FIG. The same elements as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted. Strobe 1 signal (S
TRB1) is a pulse signal that changes for a plurality of periods (five periods in FIG. 2) in each rate section. The digital comparators 41 and 42 compare the two inputs IN1 and IN2 at the rise of the strobe 1 signal. That is, IN1 and IN2 are compared a plurality of times in one rate section. In addition,
It is assumed that NFAIL is fixed at 3.

As described above, the output of the OR gate 5 goes low when the expected value and the output of the pin comparators 31 and 32 match, and goes high when they do not match. In the rate sections 1 to 3, the expected value and the outputs of the pin comparators 31 and 32 match, so the output of the OR gate 5 becomes low level, and the output of the AND gate 11 also remains at low level. Accordingly, the output Qm of the up counter 12 becomes 0, and the output FAIL
One signal also becomes low level, and it is determined that the expected value matches the output of the device under test 2.

In the rate section 4, the expected value does not match the output of the pin comparators 31 and 32, and the output of the OR gate 5 becomes high level. Therefore, the AND gate 11 passes the strobe 1 signal. The up counter 12 counts this signal, and at the end of this rate interval its output Q
m becomes 5. The digital comparator 13 compares the count value 5 with NFAIL 3 and outputs the output FAIL
Set 1 to high level. That is, it is determined that the expected value and the output of the device under test 2 do not match.

In the rate section 6, noise is superimposed on the output of the device under test 2, and the output of the pin comparator 31 is at a high level only during the period in which the noise is superimposed. Therefore, the expected value and the output of the device under test 2 do not match for that period, the output of the OR gate 5 becomes high level, and the AND gate 11 passes the strobe 1 signal.

In FIG. 2, during this period, 1 of strobe 1 signal is used.
About the cycle, and the count value Qm of the up counter 12
Stops at 1. Since this value is smaller than 3 of NFAIL, the output FAIL1 of the digital comparator 13 becomes low level. That is, even if noise is superimposed on the output of the device under test 2, the determination is not erroneous.

In this embodiment, three types of judgments of H, L and Z are made by using two pin comparators. However, only judgment of H and L is made by using one pin comparator. May be configured.

Although the number of pulses of one strobe signal in one rate section is set to 5, it is not limited to this value and may be set to an arbitrary value. Also, the value of NFAIL is
Other values than 3 may be set. Furthermore, by devising the configuration, the value of NFAIL and the number of pulses of the strobe 1 signal can be changed for each rate section.

Further, in this embodiment, the majority decision circuit 1
Is composed of an AND gate, an up counter, and a digital comparator, but other configurations may be used.

[0032]

As is apparent from the above description,
According to the present invention, the following effects can be expected. According to the first aspect of the present invention, the signal level is compared with a reference value to generate a binary signal representing the magnitude relationship between the signal and the expected value and the binary signal at a predetermined cycle. A level determination method for a signal for determining a level, wherein an expected value and a binary signal are compared at least twice within a predetermined period, and only when the number of mismatches is equal to or greater than a predetermined number, It was determined that the level did not meet the predetermined criteria.

Even if noise is superimposed on the signal, there is an effect that accurate level determination can be performed. Also,
Since there is no need to limit the frequency characteristics of the comparator, there is also an effect that the inspection time does not become long even when used in an IC inspection device.

According to a second aspect of the present invention, in the first aspect of the present invention, one or both of the number of times that the expected value is compared with the binary signal and the number of times that the criterion is not satisfied within a predetermined period are determined. , Depending on the signal conditions, etc. There is an effect that optimal processing can be performed according to the state of noise or the state of a signal.

According to a third aspect of the present invention, there is provided a comparator for comparing a signal with a reference value to generate a binary signal representing a magnitude relationship between the signal and the reference value, a digital comparator for comparing an output of the comparator with an expected value, A majority decision determiner to which the output of the digital comparator is input, the digital comparator compares the expected value with the output of the comparator at least twice within a predetermined time, and the majority decision determiner determines that the comparison result matches The number of times of non-coincidence is compared with a predetermined value, and only when the number of times of non-coincidence is greater, it is determined that the signal does not satisfy a predetermined criterion.

There is an effect that accurate level determination can be performed even if noise is superimposed on a signal. Also,
Since there is no need to limit the frequency characteristics of the comparator, there is also an effect that the inspection time does not become long even when used in an IC inspection device.

According to a fourth aspect of the present invention, in the third aspect of the present invention, one or both of the number of times the expected value is compared with the output of the comparator within a predetermined time and / or the value determined to be not the same. Is changed according to the condition of the signal and the like. There is an effect that optimal processing can be performed according to the state of noise or the state of a signal.

According to a fifth aspect of the present invention, in the third or fourth aspect of the present invention, the majority decision determiner includes a counter for counting the number of times the expected value does not match the output of the comparator, and a count of this counter. It is constituted by a digital comparator which compares a value with a predetermined value and outputs the comparison result. There is an effect that the majority decision unit can be configured with a simple configuration.

According to a sixth aspect of the present invention, in the third to fifth aspects of the present invention, at least two comparators for comparing a signal with a reference value and two or more digital comparators for comparing an output of the comparator with an expected value are provided. Used to determine three or more levels of the signal. There is an effect that a complicated level determination can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a time chart showing the operation of one embodiment of the present invention.

FIG. 3 is a configuration diagram of a conventional signal level determination device.

FIG. 4 is a time chart showing the operation of a conventional signal level determination device.

[Explanation of symbols]

 Reference Signs List 1 majority decision unit 11 AND gate 12 up counter 13 digital comparator 2 device under test 31, 32 pin comparator 41, 42 digital comparator VOH, VOL reference value EXH, EXL expected value STRB1 strobe 1 signal

Claims (6)

[Claims] 1. A method for comparing a level of a signal with a reference value to generate a binary signal related to a magnitude relation between the signal and a predetermined value, comparing an expected value with the binary signal at a predetermined period, and In the signal level determination method for determining a level, the expected value and the binary signal are compared at least twice within the predetermined period, and only when the number of mismatches is equal to or greater than a predetermined number of times, A method for determining a signal level, wherein the signal level does not satisfy a predetermined criterion. 2. The method according to claim 1, wherein the number of times the expected value is compared with the binary signal within a predetermined period or the number of times that the criterion is not satisfied is changed depending on the situation. Level judgment method. 3. A comparator for comparing a signal with a reference value to generate a binary signal related to a magnitude relationship between them, a digital comparator for comparing an output of the comparator with an expected value, and an output of the digital comparator. And a majority decision unit to which the expected value and the output of the comparator are compared at least twice within a predetermined time by the digital comparator. Comparing the number of non-matching times with a predetermined value, and determining that the signal does not satisfy a predetermined criterion only when the number of non-matching times is larger than the predetermined number. Judgment device. 4. The signal according to claim 3, wherein the number of times the expected value is compared with the output of the comparator within a predetermined time or the value determined to be inconsistent is changed depending on the situation. Level determination device. 5. A majority decision unit, comprising: a counter for counting the number of times the expected value and the output of the comparator do not match;
5. The signal level judging device according to claim 3, further comprising a digital comparator for comparing a count value of the counter with a predetermined value and outputting a result of the comparison. 6. A method for judging three or more levels of a signal by using two or more comparators each for comparing a signal with a reference value and a digital comparator for comparing an output of the comparator with an expected value. The signal level judging device according to claim 3, wherein