JPH0591148A - Signal interruption detection circuit - Google Patents

Signal interruption detection circuit

Info

Publication number
JPH0591148A
JPH0591148A JP27736891A JP27736891A JPH0591148A JP H0591148 A JPH0591148 A JP H0591148A JP 27736891 A JP27736891 A JP 27736891A JP 27736891 A JP27736891 A JP 27736891A JP H0591148 A JPH0591148 A JP H0591148A
Authority
JP
Japan
Prior art keywords
circuit
signal
interval
pulse
detection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27736891A
Other languages
Japanese (ja)
Inventor
Kazutomo Souma
一等 相馬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Engineering Ltd
Original Assignee
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Engineering Ltd filed Critical NEC Engineering Ltd
Priority to JP27736891A priority Critical patent/JPH0591148A/en
Publication of JPH0591148A publication Critical patent/JPH0591148A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide the signal interruption detection circuit in which large scale integration is attained and miniaturization is executed through the configuration of a digital logic circuit. CONSTITUTION:The circuit is provided with a pulse counter circuit counting an inputted monitored signal pulse S3 within a monitor interval period based on the monitor interval signal from an interval generating circuit 1 generating a signal interrupt detection interval signal S2 and with a discrimination circuit discriminating the result of count by the pulse count circuit for each monitor interval period and outputting signal interruption detection information S6, and the pulse counter circuit and the discrimination circuit are respectively made up of flip-flop circuits 2A, 3A.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、論理回路で構成できる
信号断検出回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal disconnection detection circuit which can be constituted by a logic circuit.

【0002】[0002]

【従来の技術】従来の信号断検出回路は、図4に示すよ
うに被監視信号検出回路10と識別回路11からなり、
被監視信号検出回路10は抵抗とコンデンサによる時定
数回路を用いたアナログ回路によって構成されている。
2. Description of the Related Art A conventional signal loss detection circuit comprises a monitored signal detection circuit 10 and an identification circuit 11, as shown in FIG.
The monitored signal detection circuit 10 is composed of an analog circuit using a time constant circuit composed of a resistor and a capacitor.

【0003】この信号断検出回路では、図5にタイミン
グチャートを示すように被監視信号検出回路10におい
て抵抗とコンデンサの時定数で定められる監視インター
バルの区間内に被監視信号パルスU1が無いことを検出
する。被監視信号U1が有る場合は、被監視信号検出回
路10からはハイレベル(“H“)の検出信号U2が出
力され、信号断により被監視信号U1が検出されない場
合、検出信号U2は監視インターバルの間、徐々にロー
レベル(“L“)に近付き、その後“L“を出力する。
識別回路11は、被監視信号検出回路10からの出力信
号が“L“となったことを識別し、このとき信号断を示
す“L“の信号断検出信号U3を出力する。出力信号が
“H“の正常時は、信号断検出信号U3は“H“を出力
する。
In this signal disconnection detection circuit, as shown in the timing chart of FIG. 5, it is confirmed that the monitored signal pulse U1 does not exist within the monitored interval defined by the time constants of the resistor and the capacitor in the monitored signal detection circuit 10. To detect. When the monitored signal U1 is present, the monitored signal detection circuit 10 outputs a high-level (“H”) detection signal U2, and when the monitored signal U1 is not detected due to a signal disconnection, the detection signal U2 is a monitoring interval. During this period, the voltage gradually approaches the low level (“L”), and then outputs “L”.
The discrimination circuit 11 discriminates that the output signal from the monitored signal detection circuit 10 has become “L”, and outputs the “L” signal loss detection signal U3 indicating the signal loss at this time. When the output signal is "H" normally, the signal disconnection detection signal U3 outputs "H".

【0004】[0004]

【発明が解決しようとする課題】上述した従来の信号断
検出回路は、被監視信号検出回路10が抵抗とコンデン
サを用いたアナログ回路によって構成されているので、
LSI化(大規模集積回路化)ができず、回路部品を外
付けとしなければならないことで、小型化が図れないと
いう問題点があった。
In the above-mentioned conventional signal loss detection circuit, since the monitored signal detection circuit 10 is composed of an analog circuit using a resistor and a capacitor,
There is a problem that miniaturization cannot be achieved because an LSI (large-scale integrated circuit) cannot be formed and circuit components must be externally attached.

【0005】本発明は、このような従来の技術が有する
課題を解決するために提案されたものであり、ディジタ
ル論理回路で構成することでLSI化が図れ、小型化で
きる信号断検出回路を提供することを目的とする。
The present invention has been proposed in order to solve the problems of the prior art as described above, and provides a signal loss detection circuit which can be made into an LSI and can be miniaturized by being constituted by a digital logic circuit. The purpose is to

【0006】[0006]

【課題を解決するための手段】この目的を達成するため
に本発明による信号断検出回路は、信号断検出用の監視
インターバル信号を生成するインターバル生成回路と、
このインターバル生成回路からの監視インターバル信号
に基づき、入力される被監視信号パルスを監視インター
バル区間内で計数するパルス計数回路と、このパルス計
数回路の計数結果を監視インターバル区間毎に判定し、
信号断検出情報を出力する判定回路とを備える構成とし
てあり、好もしくはパルス計数回路と判定回路とをフリ
ップフロップ回路で構成してある。
In order to achieve this object, a signal loss detection circuit according to the present invention includes an interval generation circuit for generating a monitoring interval signal for signal loss detection,
Based on the monitoring interval signal from this interval generation circuit, a pulse counting circuit that counts the input monitored signal pulses within the monitoring interval section, and the counting result of this pulse counting circuit is determined for each monitoring interval section,
The configuration includes a determination circuit that outputs signal loss detection information, and the favorable or pulse counting circuit and the determination circuit are configured by flip-flop circuits.

【0007】[0007]

【作用】上述した構成によれば、パルス計数回路で監視
インターバル区間内に被監視信号パルスが全く計数され
なかった場合に、判定回路ではパルス計数回路の計数結
果に基づき、信号断の検出情報を出力することができ
る。インターバル生成回路、パルス計数回路および判定
回路は論理回路で構成することができるので、信号断検
出回路の集積回路化が図れる。
According to the above configuration, when the pulse counting circuit does not count the monitored signal pulses at all in the monitoring interval section, the determination circuit provides the signal disconnection detection information based on the counting result of the pulse counting circuit. Can be output. Since the interval generation circuit, the pulse counting circuit, and the determination circuit can be configured by logic circuits, the signal disconnection detection circuit can be integrated.

【0008】[0008]

【実施例】以下、本発明による信号断検出回路の具体的
な実施例を図面に基づき詳細に説明する。図1のブロッ
ク図に、この信号断検出回路の基本的な構成を示す。こ
の図で、インターバル生成回路1では、入力信号S1か
ら監視インターバル信号S2を生成してパルス計数回路
2に出力するとともに、このインターバル信号S2と同
一周期の信号S5を判定回路3に出力する。パルス計数
回路2では入力される監視インターバル信号S2に基づ
いて、この監視インターバル信号間隔内の被監視信号パ
ルスS3を計数し、計数結果である検出信号S4を判定
回路3に出力する。判定回路3では、監視インターバル
区間毎にこの検出信号S4の状態を調べ、信号断検出情
報S6を出力する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the signal loss detection circuit according to the present invention will be described in detail below with reference to the drawings. The block diagram of FIG. 1 shows the basic configuration of this signal disconnection detection circuit. In the figure, the interval generation circuit 1 generates a monitoring interval signal S2 from the input signal S1 and outputs it to the pulse counting circuit 2, and also outputs a signal S5 having the same cycle as the interval signal S2 to the determination circuit 3. The pulse counting circuit 2 counts the monitored signal pulses S3 within the monitoring interval signal interval based on the input monitoring interval signal S2, and outputs a detection signal S4 as the counting result to the determination circuit 3. The determination circuit 3 checks the state of the detection signal S4 for each monitoring interval section and outputs the signal disconnection detection information S6.

【0009】つぎに、図2に示す具体的な信号断検出回
路を説明する。この信号断検出回路では、パルス計数回
路2が最も簡単なD型フリップフロップ回路2Aで構成
され、判定回路3もフリップフロップ回路3Aで構成さ
れている。この図で、インターバル生成回路1では入力
信号S1を分周して、図2のタイミングチャートに示す
ような監視インターバル信号S2を生成し、フリップフ
ロップ回路2Aに出力するとともに、このインターバル
信号S2と同一周期の判定信号S5をフリップフロップ
回路3Aに出力する。
Next, a specific signal break detection circuit shown in FIG. 2 will be described. In this signal break detection circuit, the pulse counting circuit 2 is composed of the simplest D-type flip-flop circuit 2A, and the determination circuit 3 is also composed of the flip-flop circuit 3A. In the figure, the interval generation circuit 1 divides the input signal S1 to generate a monitoring interval signal S2 as shown in the timing chart of FIG. 2 and outputs it to the flip-flop circuit 2A. The cycle determination signal S5 is output to the flip-flop circuit 3A.

【0010】パルス計数回路2を構成するフリップフロ
ップ回路2Aでは、監視インターバル信号S2の入力に
より、このインターバル信号S2が“L“のときにイン
ターバル単位で初期化を行なう。フリップフロップ回路
2Aのデータ端子には常時“H“が入力されており、初
期化後にインターバル区間内に被監視信号S3が少なく
とも1パルス入力された場合、フリップフロップ回路2
Aは、正常を示す“H“の検出信号S4を出力する。一
方、初期化後のインターバル区間内に被監視信号S3が
全く入力されなかった場合、信号断を示す“L“の検出
信号S4を出力する。
In the flip-flop circuit 2A constituting the pulse counting circuit 2, when the monitoring interval signal S2 is input, initialization is performed in intervals when the interval signal S2 is "L". "H" is always input to the data terminal of the flip-flop circuit 2A, and if at least one pulse of the monitored signal S3 is input within the interval section after initialization, the flip-flop circuit 2
A outputs a detection signal S4 of "H" indicating normality. On the other hand, when the monitored signal S3 is not input at all in the interval section after the initialization, the detection signal S4 of "L" indicating the signal disconnection is output.

【0011】判定回路3を構成するフリップフロップ回
路3Aでは、監視インターバル信号S2で初期化される
直前の検出信号S4を判定信号S5の入力により判定
し、正常であれば“H“の信号断検出情報S6を出力
し、信号断が判定された場合は、“L“の信号断検出情
報S6を出力する。
In the flip-flop circuit 3A which constitutes the judgment circuit 3, the detection signal S4 immediately before being initialized by the monitoring interval signal S2 is judged by inputting the judgment signal S5. The information S6 is output, and when the signal disconnection is determined, the "L" signal disconnection detection information S6 is output.

【0012】なお、本発明は上述した実施例に限定され
るものではなく、要旨の範囲内で種々の変形実施が可能
である。
The present invention is not limited to the above-described embodiments, but various modifications can be made within the scope of the invention.

【0013】[0013]

【発明の効果】以上説明したように本発明によれば、従
来アナログ回路で構成していた信号断検出回路を、ディ
ジタル論理回路により構成できるようにしたので、LS
I化が図れるようになり、実装回路を小型化できるよう
になった。
As described above, according to the present invention, the signal disconnection detection circuit, which was conventionally composed of an analog circuit, can be composed of a digital logic circuit.
It has become possible to implement the I-type, and the mounting circuit can be downsized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による信号断検出回路の基本的な構成を
示すブロック図である。
FIG. 1 is a block diagram showing a basic configuration of a signal loss detection circuit according to the present invention.

【図2】具体的な信号断検出回路の一実施例を示すブロ
ック図である。
FIG. 2 is a block diagram showing an example of a specific signal loss detection circuit.

【図3】図2の信号断検出回路の動作を示すタイミング
チャートである。
FIG. 3 is a timing chart showing an operation of the signal loss detection circuit of FIG.

【図4】従来の信号断検出回路を示すブロック図であ
る。
FIG. 4 is a block diagram showing a conventional signal loss detection circuit.

【図5】従来の信号断検出回路の動作を示すタイミング
チャートである。
FIG. 5 is a timing chart showing the operation of a conventional signal loss detection circuit.

【符号の説明】[Explanation of symbols]

1 インターバル生成回路 2 パルス生成回路 2A フリップフロップ回路 3 判定回路 3A フリップフロップ回路 S1 入力信号 S2 監視インターバル信号 S3 被監視信号 S4 検出信号 S5 判定信号 S6 信号断検出情報 1 Interval Generation Circuit 2 Pulse Generation Circuit 2A Flip-Flop Circuit 3 Judgment Circuit 3A Flip-Flop Circuit S1 Input Signal S2 Monitoring Interval Signal S3 Monitored Signal S4 Detection Signal S5 Judgment Signal S6 Signal Loss Detection Information

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 信号断検出用の監視インターバル信号を
生成するインターバル生成回路と、 このインターバル生成回路からの監視インターバル信号
に基づき、入力される被監視信号パルスを監視インター
バル区間内で計数するパルス計数回路と、 このパルス計数回路の計数結果を監視インターバル区間
毎に判定し、信号断検出情報を出力する判定回路とを備
えることを特徴とする信号断検出回路。
1. An interval generation circuit for generating a monitoring interval signal for signal loss detection, and a pulse counting for counting an input monitored signal pulse in a monitoring interval section based on the monitoring interval signal from the interval generation circuit. A signal loss detection circuit comprising: a circuit; and a determination circuit that determines the counting result of the pulse counting circuit for each monitoring interval section and outputs signal loss detection information.
【請求項2】 上記パルス計数回路と上記判定回路とが
フリップフロップ回路により構成されることを特徴とす
る請求項1記載の信号断判定回路。
2. The signal disconnection judging circuit according to claim 1, wherein the pulse counting circuit and the judging circuit are constituted by a flip-flop circuit.
JP27736891A 1991-09-27 1991-09-27 Signal interruption detection circuit Pending JPH0591148A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27736891A JPH0591148A (en) 1991-09-27 1991-09-27 Signal interruption detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27736891A JPH0591148A (en) 1991-09-27 1991-09-27 Signal interruption detection circuit

Publications (1)

Publication Number Publication Date
JPH0591148A true JPH0591148A (en) 1993-04-09

Family

ID=17582555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27736891A Pending JPH0591148A (en) 1991-09-27 1991-09-27 Signal interruption detection circuit

Country Status (1)

Country Link
JP (1) JPH0591148A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7257323B2 (en) 2001-11-21 2007-08-14 Nec Corporation Signal-off detection circuit and optical receiving device using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7257323B2 (en) 2001-11-21 2007-08-14 Nec Corporation Signal-off detection circuit and optical receiving device using the same

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