JPH02117246A - Pcm input disconnection detection circuit - Google Patents

Abstract

PURPOSE:To obtain a PCM input disconnection detection circuit with high accuracy in which no resistor and capacitor are required by inputting the output of two OR gates as a clock and reset for a counter, respectively, and detecting the input disconnection of a PCM by the output of the counter. CONSTITUTION:When reception PCM signals 5 and 6 are always inputted to the OR gate 2, the reset is always applied on the counter 3, and PCM input disconnection output 7 always goes to a logic L. When no reception PCM input signals 5 and 6 are inputted i.e., when no leading pulse is inputted to a reset input terminal 9, the counter 3 continues the counting of a clock. And the PCM input disconnection output 7 goes to a logic H at the x-th time, and at this time, a reception PCM is judged that it is set at an input disconnection state. Simultaneously, by connecting the output 7 to the OR gate 1, the supply of an internal clock to a clock input terminal 8 is cut off.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital logic circuit of a PCM device having a function of terminating an external clock and generating a clock internally, and particularly to a PCM input disconnection detection circuit. [Technology] Conventionally, this type of PCM input disconnection detection circuit has been realized by using a mono-multi-by-break. FIG. 2 shows such a conventional PCM input disconnection detection circuit. According to this PCM input disconnection detection circuit, the time constant based on the pulse integral action of the mono multi-vibrator 12 can be arbitrarily set using one resistor 14 and one capacitor 13, and the positive receiving PCM input 5 and sub-side receiving P CM input 6 2 inputs or The time from the rising edge of an input signal to the rising edge of the next input signal or the time from the falling edge of the input signal to the falling edge of the next input signal when T= is the output pulse width according to the time constant of the mono multi-high break 12. If the time interval does not exceed , the logic value of the output at the signal output terminal 16 of the mono multivibrator does not change, but the time from the rising edge of the input signal to the rising edge of the next input signal when 7' = or ' If the time from the falling edge of the input signal to the falling edge of the next input signal when 1'= exceeds the time interval of the output pulse width due to the time constant of the mono multi-pipe break, the logical value of the output of the mono multi-pipe break PC using the change in
M input input blade output cuff force was used to detect PCM input disconnection.

[Problem to be solved by the invention]

Since the conventional PCM input disconnection detection circuit described above uses a monomultiply pipe rake, it is necessary to externally attach a resistor and a capacitor. Therefore, it was not suitable for converting this circuit directly into a digital integrated circuit. In addition, due to component constant errors in resistors and capacitors, it is difficult to set the no-change time of the input signal that should be recognized as PCM input disconnection with high precision, and even if it can be achieved, it is expensive. It has the disadvantage that it requires a resistor and a capacitor and is economically disadvantageous.

An object of the present invention is to provide a PCM input disconnection detection circuit that eliminates such drawbacks.

[Means to solve the problem]

The PCM input disconnection detection circuit of the present invention consists of a first 2-input OR gate, a second 2-input OR gate, and a counter having a reset function, and outputs the internal clock and the counter to the second 2-input OR gate. The main side receiving PCM and the secondary side receiving PCM are connected as inputs of the second 2-input OR gate, and the output of the first 2-input OR gate is input as the clock of the counter. It is characterized in that the output of the input OR gate is input as a counter reset, and a PCM input disconnection is detected based on the output of the counter.

[Effect]

The present invention includes a first OR gate, a second OR gate,
It consists of one counter with a reset function and does not use a mono-multi-by-break, so resistors and capacitors are not required. Since the reception PCM input time interval for determining reception PCM input disconnection is set in units of bits of the internal clock, detection can be performed with higher accuracy than in conventional circuits.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention.

Connected to the inputs of the first two-input OR gate 21 is an internal clock input 4 and a PCM input input. 2nd 2 inputs O
The primary receiving PCM input 5 and secondary receiving PCM input 6 are connected to the R gate 20 input. Counter 3 with reset function
(hereinafter simply referred to as counter) clock input terminal 8
The output of the first OR gate 1 is connected to. The output of the second OR gate 2 is connected to the reset input terminal 9 of the counter 3.

The operation of this embodiment will be explained with reference to the time chart of FIG.

When the received PCM input is normal, the counter 3 receives an internal clock signal as a clock signal and an OR logic of the primary received PCM signal and the secondary received pcM signal as a reset signal. For example, if the reset operation logic of the counter 3 is logic H and the initial value of the counter output is logic logic, and the PCM input input blade cuff reset signal, which is the output of the counter 3, is always logic logic, it will generally be X times ( X
is the count value determined by the number of stages of the counter) and becomes logic 11. However, if the received PCM signals 5 and 6 are always input to the second 2-input OR gate 2, the counter 3 is always reset. Therefore, it is logical that the PCM input input blade protrusion cuff. However, if the received PCM input signal 5.6 is not input, that is, if no rising pulse is input to the reset input terminal 9, the counter 3 continues counting the clocks, and the
I, and at this time, the receiving PCM is considered to be in an input disconnected state. At the same time, due to the connection to the first two-input OR gate l, the supply of the internal clock input 4 to the clock input terminal 8 is interrupted. When the received PCM signals 5 and 6 are restored, the counter 3 is reset, the PCM input signal is turned off, and the supply of the internal clock input 4 to the clock input terminal 8 is resumed.

〔Effect of the invention〕

As explained above, the present invention does not use a resistor or capacitor compared to a conventional circuit using a mono-multi high break, so it is easier to integrate the circuit into a digital integrated circuit. It is highly effective in that it can be set in units of bit width of the internal clock by changing the frequency or the number of counter stages, and it can provide higher accuracy more economically than conventional circuits.

[Brief explanation of the drawing]

Fig. 1 is a circuit configuration diagram of an embodiment of the PCM input disconnection detection circuit of the present invention, and Fig. 2 is a circuit configuration diagram of an embodiment of the PCM input disconnection detection circuit of the present invention.
A block diagram of the M input disconnection detection circuit. FIG. 3 is a time chart showing the operation of the embodiment of FIG. 1. ■...First 2-input OR gate 2...To second 2-input OR gate 13...Counter with reset function 4...Internal clock input 5, 6・ 8 ・ 9 ・ 10 ・ 11 ・ 12 ・ 15 ・

Claims (1)

[Claims] (1) Consisting of a first 2-input OR gate, a second 2-input OR gate, and a counter with a reset function, the internal clock and the output of the counter are connected as inputs of the second 2-input OR gate, Primary receiving PCM and secondary receiving PC
Connect M as the input of the second 2-input OR gate, input the output of the first 2-input OR gate as the counter clock, input the output of the second 2-input OR gate as the counter reset, and input the output of the first 2-input OR gate as the counter reset. A PCM input disconnection detection circuit that detects a PCM input disconnection based on an output.