JPH03108013A - Clock break detecting circuit - Google Patents

Abstract

PURPOSE:To eliminate a need of circuits of resistances and capacitors to make a clock break detecting circuit into an LSI by constituting this circuit of a master clock break detecting part, a clock break detecting part, an edge detecting circuit, a delay line, an AND circuit, a counter, a monitor circuit, and an OR circuit. CONSTITUTION:A master clock (a) is inputted to a master clock break detecting part 10 and a clock break detecting part 20, and the detecting part 10 uses a monostable multivibrator, to which a time constant is preliminarily set, to detect a break of the clock (a), and an obtained detection signal (d) is inputted to an OR circuit 30. Meanwhile, the clock (a) inputted to the detecting part 20 is sent to a counter 22, and a simultaneously inputted clock (b) is inputted to an AND circuit 21B and a delay line 21A in an edge detecting circuit 21. ANDing between the clock (b) and the delayed clock (b) is operated in the circuit 21B to generate an edge pulse (c). Since the pulse (c) is not generated at the time of a break of the clock (b), the counted value of the counter 22 is monitored by a monitor circuit 23; and when a prescribed set value is obtained, a detection signal (e) of the circuit 23 is outputted to the circuit 30.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock disconnection detection circuit that detects clock disconnection.

[Conventional technology]

The clock is used in an OR circuit and the like.

Also, multiple clocks may be used.

There are times when this clock is disconnected due to an OR circuit or the like. Such a lock break is detected by a clock break detection circuit. An example of this clock disconnection detection circuit is shown in FIG.

The conventional clock disconnection detection circuit shown in FIG. 2 detects disconnection of a plurality of clocks g and outputs a clock disconnection signal. This disconnection of clock g is detected as follows.

That is, the plurality of clocks g are input to the mono multivibrator 51, respectively. The mono multivibrator 51 has a set time constant and detects interruption of the clock g.

The output signal from the mono multivibrator 51 is input to an OR circuit 52. The OR circuit 52 performs a logical OR operation on these output signals and outputs a clock cutoff signal.

In this way, the clock interruption detection circuit detects clock interruption.

[Problem to be solved by the invention]

In the conventional clock disconnection detection circuit described above, each clock is input to a mono multivibrator. These mono multivibrators have a resistor for setting the time constant.
A capacitor circuit (RC circuit) is required.

When a clock interruption detection circuit including such an RC circuit is implemented, the following problem occurs.

That is, the RC circuit occupies a large amount of mounting area. Another disadvantage is that it is almost impossible to implement on a logic LSI.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock disconnection detection circuit that can eliminate such drawbacks and reduce the number of RC circuits.

[Means to solve the problem]

The present invention is a clock disconnection detection circuit that detects a clock disconnection between a master clock and one or more clocks and outputs a clock disconnection signal, and the clock disconnection detection circuit detects a clock disconnection between a master clock and one or more clocks and outputs a clock disconnection signal. A master clock disconnection detection section that detects with a mono multivibrator and outputs a detection signal, resets the master clock count with a reset signal generated based on the clock, and outputs a detection signal when this count reaches a set value. and a logical OR operation unit that performs a logical sum operation of detection signals from the master clock failure detection unit and each of the clock failure detection units and outputs a clock failure signal. .

Further, in the present invention, the clock loss detection section includes an edge detection circuit that detects an edge of a clock signal to generate an edge pulse, and outputs this edge pulse as a reset signal, and an edge detection circuit that counts the master clock and outputs a counted value. , a counter that resets a count value by a reset signal from the edge detection circuit, and a monitoring circuit that monitors the count value from the counter and outputs a detection signal when the count reaches a set value. .

Furthermore, in the present invention, it is preferable that the edge detection circuit has delay means for delaying a clock, and AND operation means for performing an AND operation between the clock and the clock from the delay means to generate an edge pulse. It is.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram showing an embodiment of the present invention. 1st
The clock disconnection detection circuit shown in the figure is based on the master clock a.
This is to detect clock disconnection between the clocks b and the plurality of clocks b.

This clock disconnection detection circuit includes a master clock disconnection detection section l.
0, a clock disconnection detection section 2o, and an OR circuit 30.

Further, the clock interruption detection section 2o includes an edge detection circuit 21, a counter 22, and a monitoring circuit 23.

Further, the edge detection circuit 21 includes a delay line 22A and an AND circuit 21B.

In such a lock disconnection detection circuit, the master clock disconnection detection section 10 detects a clock disconnection of the master clock a and outputs a detection signal d. Detection of clock interruption is performed by a monomultivibrator equipped with an RC circuit, as in the prior art.

The edge detection circuit 21 of the clock interruption detection section 20 detects the edge of clock b. That is, delay line 21a delays clock b. Then, the AND circuit 21B performs an AND operation on the clock b and the delayed clock b, and outputs an edge pulse C.

Note that the edge detection circuit 21 is a delay line that is a delay element,
Even if it is configured with a logic inversion circuit (inverter) and an AND circuit (AND circuit), the rising edge change of clock b can be converted into a pulse.

The counter 22 counts the master clock a input to the terminal CK, and outputs the counted value from the terminal Q.

Further, the counter 22 resets the count value by the edge pulse C input to the terminal R.

The monitoring circuit 23 monitors the count from the counter 22. When a predetermined set value is detected in this count value, a detection signal e is output.

The OR circuit 30 receives the detection signal d from the master clock interruption detection section 10 and the detection signal e from each clock interruption detection section 20.
A logical AND operation is performed and a clock cutoff signal f is output.

Next, the operation of this clock disconnection detection circuit will be explained.

The master clock a has a master clock disconnection detection section 10,
The signal is input to the clock interruption detection section 20. In the master clock disconnection detection section 10, a clock disconnection of the master clock a is detected by a mono multivibrator whose time constant is set in advance. Then, the detection signal d is output from the OR circuit 30.
is input.

On the other hand, the master clock a input to the clock disconnection detection section 20 is input to the terminal CK of the counter 22 and counted. A clock b is input to the clock disconnection detection section 20. Clock b is input to the OR circuit 21B of the edge detection circuit 21 and the delay line 21A. delay line 2
1A delays clock b and sends it to OR circuit 21B. The OR circuit 21B performs an OR operation on the clock b and the delayed clock b, and generates an edge pulse C. This edge pulse C is input to terminal R of the counter 22.

As mentioned earlier, the counter 22 is connected to the master clock a.
are counting. This count is reset by edge pulse C. If clock b is cut off, edge pulse C is not generated and counter 22 is not reset. The counter 22 outputs the count value related to such counting from the terminal Q to the monitoring circuit 23. Monitoring circuit 2
3 monitors the count from the counter 22. When a predetermined set value is detected in this count value, the monitoring circuit 23 outputs a detection signal e to the OR circuit 30.

The OR circuit 30 performs a logical sum operation between the detection signal d from the master clock interruption detection circuit 10 and the detection signal e from each clock interruption detection section 20 . If even one of the master clock a and each clock b becomes disconnected, the OR circuit 30 outputs a clock disconnection signal f.

In this way, clock disconnection of the master clock and each clock can be detected.

〔Effect of the invention〕

As described above, according to the present invention, the number of resistor and capacitor circuits can be reduced, and as a result, all disconnection detection other than the clock serving as a mask can be configured with logic, and can be implemented within an LSI.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
FIG. 2 is a configuration diagram showing an example of a conventional clock disconnection detection circuit. 10... Master clock disconnection detection unit 20...
Clock loss detection unit 21... Edge detection circuit 21A... Delay line 21B... AND circuit 22... Counter 23... Monitoring circuit 30... Logic sum circuit

Claims (3)

[Claims] (1) A clock disconnection detection circuit that detects a clock disconnection between a master clock and one or more clocks and outputs a clock disconnection signal, the clock disconnection detection circuit having a time constant set in advance to detect the clock disconnection of the master clock. A master clock disconnection detection unit that detects with a multivibrator and outputs a detection signal, and resets the master clock count with a reset signal generated based on the clock, and outputs a detection signal when this count reaches a set value. A clock comprising: a clock disconnection detection section; and an OR operation section that performs a logical sum operation of detection signals from the master clock disconnection detection section and each of the clock disconnection detection sections and outputs a clock disconnection signal. disconnection detection circuit. (2) The clock loss detection section includes an edge detection circuit that detects an edge of a clock signal, generates an edge pulse, and outputs this edge pulse as a reset signal; and an edge detection circuit that counts the master clock and outputs a counted value; Claim 1, further comprising: a counter that resets a count value by a reset signal from the edge detection circuit; and a monitoring circuit that monitors the count value from the counter and outputs a detection signal when the count reaches a set value.
The clock disconnection detection circuit described. (3) The edge detection circuit comprises: delay means for delaying a clock; and AND operation means for performing an AND operation between the clock and the clock from the delay means to generate an edge pulse. Clock disconnection detection circuit.