JPH0714184B2 - Clock down detection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock down detection circuit for detecting a failure of a system synchronization clock in a digital electronic exchange.

[Conventional technology]

Conventionally, this kind of clock down detection circuit sets a predetermined time constant using a capacitor and a resistor, and when a change in the system synchronous clock is not detected within the time corresponding to the set time constant, some kind of failure occurs. It happened and it was determined that the clock was down.

[Problems to be Solved by the Invention]

In such a conventional system clock down detection circuit, since it is necessary to determine the time constant according to the clock frequency, the resistance value and the capacitance of the capacitor must be changed by the electronic exchange.

An object of the present invention is to eliminate such drawbacks and provide a clock down detection circuit capable of detecting a clock failure without setting a time constant according to a clock frequency.

[Means for Solving the Problems]

The present invention relates to a clock down detection circuit for detecting a failure of a system synchronization clock in a digital electronic exchange, a first flip-flop that inverts an output every time the system synchronization clock is input through a first line, and a first flip-flop. A first counter that is reset by the non-inverted output from the flip-flop and advances by the system synchronization clock input through the second line, and is reset by the inverted output of the first flip-flop and is input through the second line. Second counter that advances by the system synchronization clock, a second flip-flop that inverts the output every time the system synchronization clock is input through the second line, and a non-inversion output from the second flip-flop System that is reset by and is input through the first line A third counter that advances by a system synchronous clock; a fourth counter that resets by the inverted output of the second flip-flop and advances by a system synchronous clock input through the first line; Or an OR gate that takes the logical sum of the outputs of the counters of No. 4 and No. 4.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a clock down detection circuit according to the present invention.

The toggle flip-flop 3 is the second system synchronization clock.
Each time the system synchronous clock is input through the line 2, its non-inverted output and inverted output are inverted. 3-bit counters 5 and 6 are the first system synchronization clock
The counter 5 is incremented by the system synchronous clock from the line 1, the counter 5 is reset when the non-inverted output of the flip-flop 3 is input through the counter reset output line 10, and the counter 6 is the inverted output of the flip-flop 3 and the inverted counter reset output. Resets when entered on line 11.

The toggle flip-flop 4 is the first system synchronization clock.
Each time the system synchronous clock is input through the line 1, its non-inverted output and inverted output are inverted. The 3-bit counters 7 and 8 are the second system synchronization clock.
The counter 7 is advanced by the system synchronous clock from the line 2, the counter 7 is reset when the non-inverted output of the flip-flop 4 is input through the counter reset output line 12, and the counter 8 is the inverted output of the flip-flop 4 and the inverted counter reset output. Resets when entered on line 13.

The OR gate 9 takes the logical sum of the outputs of the counters 5-8,
The result is output through the clock down detection transmission line 14.

Next, the operation will be described. First, the operation when the system synchronization clock is normal will be described with reference to the timing chart shown in FIG. The system synchronization clock 15 is a line from the electronic exchange facing the electronic exchange provided with the detection circuit.
It is input through two lines of 1,2. The flip-flop 3 is triggered by the rising edge of the clock 15 and outputs the reset signals 16 and 17 to the counters 5 and 6, respectively.

The counters 5 and 6 advance at the rising edge of the clock 15 input through the line 1. However, since the reset signals 16 and 17 of logic "1" are input every other clock, the outputs of the counters 5 and 6 are logic "0". "Keep it.

Since the counters 7 and 8 also operate in the same manner as the counters 5 and 6, their outputs are logic "0". Therefore, the output of the OR gate 9 maintains the logic "0", and the clock down display device (not shown) is notified through the line 14 that the system synchronization clock is normal.

Next, the operation when the system synchronization clock becomes abnormal will be described with reference to the timing chart shown in FIG. When the system synchronous clock (first line clock) 18 input through the line 1 goes down at the time indicated by the arrow and remains at the logic "1", the flip-flop 4 stops its operation and its output, that is, the reset signal. Both 20 and 21 are constant values. If the reset signal 20 is logic "1" and the reset signal 21 is logic "0", the counter 7 is always reset and the counter 8 is always stepable. As a result, the counter 8 advances every time the clock 19 is input, and the output becomes the logic "1" when the fourth clock is input. Therefore, the OR gate 9 sends the detection signal 22 of logic "1" to the clock down display device at this time to notify the abnormality of the clock.

The operation is the same when the clock from the line 2 becomes abnormal. In that case, the output of the counter 5 or the counter 6 becomes the logic "1" and the OR gate 9 outputs the detection signal of the logic "1". It

〔The invention's effect〕

As described above, according to the present invention, in the clock down detecting circuit for detecting the failure of the system synchronization clock in the digital electronic exchange, the first output is inverted every time the system synchronization clock is input through the first line.
And a first counter that is reset by the non-inverted output from the first flip-flop and advances by the system synchronization clock input through the second line, and is reset by the inverted output of the first flip-flop. A second counter that increments according to the system synchronization clock input through the second line, a second flip-flop that inverts the output each time the system synchronization clock is input through the second line, and a second counter The third counter, which is reset by the non-inverted output from the flip-flop of the second flip-flop, is incremented by the system synchronous clock input through the first line, and is reset by the inverted output of the second flip-flop through the first line. A fourth counter that increments according to the input system synchronization clock, and a first counter And a gate for taking a logical sum of the outputs of the fourth counter.

Therefore, in the clock down detection circuit of the present invention, the two system synchronous clocks are mutually monitored, and the clock failure can be detected without setting the time constant according to the clock frequency which was necessary in the conventional detection circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the embodiment of FIG. 1 …… System synchronization clock 1st line 2 …… System synchronization clock 2nd line 3,4 …… Toggle flip-flop 5-8 …… 3 bit counter 9 …… OR gate 10,12 …… Counter reset output line 11,13 ...... Inversion counter reset output line 14 …… Clock down detection transmission line

Claims (1)

[Claims] 1. A clock down detection circuit for detecting a failure of a system synchronization clock in a digital electronic exchange, comprising: a first flip-flop that inverts an output every time the system synchronization clock is input through a first line; First counter that is reset by the non-inverted output from the flip-flop and is incremented by the system synchronization clock input through the second line, and is reset by the inverted output of the first flip-flop through the second line. A second counter that advances by the input system synchronization clock, a second flip-flop that inverts the output every time the system synchronization clock is input through the second line, and a non-inversion from the second flip-flop The system reset by the output and input through the first line A third counter that advances by the system synchronization clock, a fourth counter that is reset by the inverted output of the second flip-flop, and advances by the system synchronization clock that is input through the first line; And a OR gate that ORs the outputs of the 4 counters.