JP2605445B2 - Clock monitoring circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock monitoring circuit, and more particularly to a clock monitoring circuit having forward monitoring and backward monitoring.

[Conventional technology]

An example of such a conventional clock monitoring circuit is shown in FIG. 6 and described.

As a conventional clock monitoring circuit, there is a circuit using two monostable multivibrators as shown in FIG.

In the figure, 63 and 66 are monostable multivibrators (M /
M), this monostable multivibrator 63 is for backward monitoring, which is a monitor for confirming that the clock is continuously disconnected, and when the monitored clock is continuously disconnected, the time determined by the resistor 61 and the capacitor 62 is obtained. Later, the Q output becomes "0",
The output of the NAND gate 6 _B becomes "1". The monostable multivibrator 66 is for forward monitoring, which is a monitor for confirming that the clock is continuously input, and the clock to be monitored is restarted and the Q output of the monostable multivibrator 63 changes from "0" to "1". , The trigger is activated, and the output becomes “0” for the time determined by the resistor 64 and the capacitor 65. It was but go-between, the output between the NAND gate 6 _B to make sure that the clock resume is continuing is that you do not return to "0". Buffer 67,6 _A and resistor 68, capacitor 69 is a smoothing circuit for such whisker-like pulse idiopathic pulses cause narrow failure width to clock cross signal during clock resuming is not output.

[Problems to be solved by the invention]

In the conventional clock monitoring circuit described above, the detection time is set by a time constant circuit consisting of a resistor and a capacitor.To change the setting of the detection time, prepare as many resistors and capacitors as the number of settings. There is a need.

Since it has an analog section and cannot be fully digitalized, it cannot be formed into a gate array.

Since the setting time depends on the analog element, accuracy and stability are lacking.

There was a problem that.

[Means for solving the problem]

The clock monitoring circuit according to the present invention comprises a reset pulse generating means for generating a reset pulse at a changing point of a monitored clock, a reset pulse from the reset pulse generating means as a reset input, and a shift clock as a clock input. A first shift register having a data input of "1", and a rearward monitoring circuit for outputting the output of a predetermined stage as an output signal, and an output signal generated when the rearward monitoring circuit cuts off the monitored clock as a reset input. And a forward monitor circuit comprising a second shift register having a shift clock input as a clock input and a logic "1" input as a data input. The output of a predetermined stage of the second shift register is provided as a monitored clock cutoff signal. Is what you do.

[Action]

In the present invention, the forward monitoring circuit and the backward monitoring circuit can be realized by a full digital circuit, the detection time can be easily set digitally, and the accuracy and stability are improved.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a clock monitoring circuit according to the present invention.

In the figure, reference numeral 11 denotes a clock oscillating unit, and reference numeral 12 denotes a clock dividing unit for dividing the output of the clock oscillating unit 11. 13,1
4 is flip-flop (F / F), 15 is flip-flop 13
An AND gate having the Q output and the output of the flip-flop 14 as inputs, these constitute reset pulse generating means for generating a reset pulse at a change point of the monitored clock. Reference numeral 16 designates a reset pulse input from the reset pulse generating means as a reset input, a shift clock as a clock input, and a logic "1" input as a data input.
The shift register 16 constitutes a backward monitoring circuit. Reference numeral 17 denotes a second shift register (SR) in which an output signal generated when the backward monitoring circuit is disconnected from the monitored clock is used as a reset input, a shift clock is input as a clock input, and a logic "1" is input as a data input. This shift register 17 constitutes a forward monitoring circuit.

The clock oscillating section 11 serves as a basic clock for operating the clock monitoring circuit shown in FIG. The output of the clock oscillating unit 11 is frequency-divided by the clock frequency dividing unit 12, and becomes the clock input of the rearward monitoring shift register 16 and the forwardward monitoring shift register 17.

The flip-flops 13 and 14 and the AND gate 15 are for generating a reset pulse for the rising edge of the monitored clock, and the operation will be described with reference to the reset pulse timing chart shown in FIG.

2A shows the monitored clock, FIG. 2B shows the clock input CK of the flip-flops 13 and 14, FIG. 2C shows the Q output of the flip-flop 13, and FIG.
(D) shows the output of the flip-flop 14, and (e) shows the output of the AND gate 15 (= reset pulse).

When the monitored clock shown in FIG. 2A rises, the clock input of the flip-flop 13 shown in FIG.
The data is fetched at the next rising edge of CK, and the Q output of the flip-flop 13 becomes "1".

Then, at the next rising edge of the clock input CK of the flip-flop 14, the data whose Q output of the flip-flop 13 is "1" is taken in. As a result, the output of the flip-flop 14 becomes "0". When the Q output of the flip-flop 13 and the output of the flip-flop 14 are both "1", the output of the AND gate 15 is "1". Therefore, as shown in FIG. 2, the flip-flops 13 and 14 immediately after the rising of the monitored clock. A reset pulse corresponding to one cycle of the clock input CK is output.

Next, the operation of the backward monitoring circuit will be described with reference to the backward monitoring timing chart shown in FIG.

In FIG. 3, (a) shows the monitored clock, (b) shows the reset input RES of the shift register 16, (c) shows the clock input CK of the shift register 16,
(D) shows Q ₈ output which is the output of a given stage of the shift register 16 is the (e) is of a predetermined stage of the shift register 17 outputs ▲
▼ Output (= clock disconnection signal).

Since "1" is always input to the shift register 16 as a data input, the data is shifted in the direction of Q ₁ → Q ₈ together with the shift clock. However, since the shift register 16 is reset every rise of the monitored clock, "1" to the Q ₈ output is normally not shifted. However, when the monitored clock is sectional reset certain time after Q ₈ output Te is summer without also becomes "1", so that the clock disconnection signal shift register 17 is reset is output. This clock disconnection signal is not output unless the clock disconnection state continues for a certain period of time (rear monitoring time), so that a momentary failure such as a clock instantaneous disconnection can be prevented.

Although the accuracy of the backward monitoring time may have an error of one cycle of the shift clock at the maximum, it is not an 8-bit shift register as in the embodiment shown in FIG. The higher the frequency of the shift clock, the higher the accuracy.
Also, the setting of the backward monitoring time is possible only by changing the frequency of the shift clock. This can be achieved by digitally controlling the clock frequency divider 12 to change the frequency division number, or by using an input selector. Can be easier.

Next, the operation of the forward monitoring circuit will be described with reference to the forward monitoring timing chart shown in FIG.

In FIG. 4, (a) represents and shows the monitored clock, (b) is Q ₈ outputs of the shift register 16, (c)
Shows the clock input CK of the shift register 17, and (d) shows the output of the shift register 17 (= clock disconnection signal).

In a state where a monitored clock is continuously input, Q ₈ output of the shift register 17 is a come, "1" is shifted data input "1". Accordingly, the output of the shift register 17 is "0". And when clock Dan takes Yotsute reset to Q ₈ output of the above as the shift register 16, the shift register 17 ▲
▼ The output becomes “1”. Here, the shift register 16 is reset when the monitored clock resumes its Q ₈
The output is "0". Accordingly, the shift register 17 comes out of the reset state and shifts the data input "1". When eight shift clocks are inputted to the shift register 17, the shift register 17 is turned on.
The output becomes "0".

That is, the clock disconnection signal stops. Since the clock resumption state must continue for a certain period of time (forward monitoring time) before the clock disconnection signal stops, it is possible to eliminate the phenomenon that the monitored clock appears to have restarted for a while due to noise or the like. it can. The accuracy and setting of the forward monitoring time are the same as those for the backward monitoring time.

5A and 5B are explanatory diagrams of forward monitoring / rearward monitoring. FIG. 5A shows a clock to be monitored, and FIG. 5B shows a clock disconnection signal.

〔The invention's effect〕

As described above, according to the present invention, the forward monitoring circuit and the backward monitoring circuit can be realized by a fully digital circuit having a relatively simple circuit configuration. As a result, first, the detection time can be set digitally easily. Secondly, there is an effect that a gate array can be formed, and thirdly, accuracy and stability can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a clock monitoring circuit according to the present invention, FIG. 2 is a reset pulse generating section timing chart, FIG. 3 is a backward monitoring timing chart, FIG. 4 is a forward monitoring timing chart, and FIG. FIG. 1 is an explanatory diagram of forward monitoring / backward monitoring, and FIG. 6 is a circuit diagram showing an example of a conventional clock monitoring circuit. 11: Clock oscillator, 12: Clock divider, 13, 14
…… Flip flop (F / F), 15 …… And gate, 1
6,17 ... Shift register (SR).

Claims (1)

(57) [Claims] A reset pulse generating means for generating a reset pulse at a changing point of a monitored clock; a reset pulse from the reset pulse generating means as a reset input; a shift clock as a clock input; A first shift register input to the data input,
A backward monitoring circuit that uses the output of the predetermined stage as an output signal, an output signal generated when the backward monitoring circuit is disconnected from the monitored clock is used as a reset input, a shift clock is used as a clock input, and logic "1" is used as a data input A clock monitoring circuit, comprising: a forward monitoring circuit including a second shift register input to a second shift register, wherein an output of a predetermined stage of the second shift register is used as a monitored clock cutoff signal.