JPH01208909A - Timer device - Google Patents

Abstract

PURPOSE:To eliminate noise by giving a both start and reset command signals to a control circuit via a digital filter circuit using an output of a time limit oscillation circuit as a clock signal source. CONSTITUTION:A start command signal given to a control circuit 7 is given to be inputted to the control circuit 7 via a digital filter circuit 12 from an input terminal 10 and a reset command signal is given to be inputted to the control circuit 7 via a digital filter circuit 13 from an input terminal 11, the clock signal source of both the digital filter circuits 12, 13 is used for the output of an oscillation circuit 3, the output of the oscillation circuit 3 is branched and given the a frequency division circuit 14 and the frequency division circuit 14 frequency-divides the consecutive pulse from the oscillation circuit 3. Moreover, two D-FFs 15, 16 of cascade connection and an AND circuit 17 are provided and an output pulse of the frequency division circuit 14 from a terminal 18 is applied to the clock terminal of both the two D-FFs 15, 16. Furthermore, a command signal Di is given to the input terminal 10 of the D-FF 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an oscillation counting type timer device in which continuous pulses of variable frequency are generated by a CR oscillation circuit and the continuous pulses are controlled by a command signal.

[Conventional technology]

An example of a conventional oscillation counting type timer device is shown in the block diagram of FIG. It is configured so that it can be changed using a resistor 1. A counting circuit 4 connected to this oscillation circuit 3 divides the frequency of the input pulse using a flip-flop or the like and counts the frequency-divided output. When the counting of a predetermined number of pulses is completed, it issues a count-up signal and outputs the output circuit 5. It operates and outputs a signal from terminal 6. The control circuit 7 has a start signal terminal 8. It has a reset signal terminal 9 and is connected to the counting circuit 4 and the output circuit 5, and the counting circuit 4 and the output circuit 5 are started or reset by a command signal inputted to both signal terminals 8.9. Components other than the variable resistor 1 and capacitor 2 of such a timer device are usually configured as an IC, and the logic circuit that generates both the start and center command signals input to the control circuit 7 is also built into the IC. is normal.

[Problem to be solved by the invention]

By the way, if a logic circuit that generates both start and reset command signals is built into an IC, these signals must be at relatively low levels, making it extremely sensitive to noise, and a C-R filter etc. is required outside of tC. It is necessary to provide noise removal means, which is an obstacle to making the timer device smaller and cheaper.

SUMMARY OF THE INVENTION An object of the present invention is to provide a small and inexpensive timer device that eliminates noise mixed in from both signal terminals of a control circuit in a timer device constituting an IC circuit.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention includes an oscillation circuit that generates continuous pulses, a counting circuit that divides and counts the continuous pulses generated by this oscillation circuit, and a counter that receives both start and reset command signals. The timer device includes a control circuit for controlling a counting circuit, and the timer device is configured such that both the start and reset command signals are inputted via a digital filter circuit that uses the output of the oscillation circuit as a clock signal source. Note that the clock signal input to the digital filter circuit is preferably connected so as to be obtained from the middle of frequency division of the counting circuit.

[Effect]

A digital filter circuit includes, for example, a predetermined number of delay flip-flops connected in cascade (hereinafter this delay flip-flop will be abbreviated as D-FF) and an A input to which the output of each D-FF is input.
When the input signal is at a high level (hereinafter this high level signal will be abbreviated as H) for more than n cycles of a clock signal corresponding to the number n of cascade-connected D-FFs, the output signal is A command signal to the control circuit is output. In this way, noise that does not extend beyond n cycles of the clock signal is not transmitted to the control circuit, and since the clock signal of the digital filter circuit is configured to be obtained from the output of the oscillation circuit, the frequency of this oscillation circuit must be adjusted. When the set time period is long, the filter characteristic has a sufficiently long time constant, and when the set time period is short, the command signal is taken in quickly.

Note that since the counting circuit is constituted by a frequency dividing circuit, if the clock signal is obtained from the middle of the frequency division of this counting circuit, the frequency dividing circuit can be saved.

〔Example〕

1 to 4 are embodiments of a timer device according to the present invention, and the same components as in FIG. 5 are given the same reference numerals as in FIG. 5, and detailed explanation thereof is omitted. FIG. 1 is a block diagram showing one embodiment of the oscillation circuit 3, which has a variable resistor 1 and a capacitor 2. The counting circuit 4゜output circuit 5 is the same as the conventional one, so its explanation will be omitted. The difference between the present invention and the conventional one is that the start command signal input to the control circuit 7 is input from the input terminal IO to the digital filter circuit 12. The reset command signal is connected to be input from the input terminal 11 to the control circuit 7 via the digital filter circuit 13, and both digital filter circuits 12 and 13 The clock signal source is the output of the oscillation circuit 3. Here, the output of the oscillation circuit 3 is branched and connected to the frequency divider circuit 14, and the continuous pulse of the oscillation circuit 3 is divided by the frequency divider circuit 14 and applied. This is what is happening. Both digital filter circuits 12 and 13 are exactly the same circuit, and for example, as shown in FIG.
- Equipped with F F 15, 16 and AND circuit 17, both D
The output pulse of the frequency divider circuit 14 is applied from the terminal 18 to the clock terminal of -F F 15.16. Also D-FF
A command signal is input to the input terminal 10 of 15. AN
One input terminal of the D circuit 17 is connected to the Q and output terminals of the D-FF 15, and the other input terminal is connected to the Q and output terminals of the D-FF 16. The output terminal is connected to the control circuit 7.

The operation of this digital filter circuit 12 will be explained with reference to the time chart shown in FIG. In FIG. 3, times t1 to t each indicate the rise time (phase) of the clock signal CK. The signal DI input to the D-FF 15 is at a low level at time ts (hereinafter, this low level signal is abbreviated as L). When the output Q1 of the D-FF15 becomes H at time t, and goes from H to L at time t, the output Q1 of the D-FF15 becomes H at time t1 when the clock signal CK rises next to time t, and D
- It is input to the FF 16, but becomes L at the next rise time t2 of the clock signal C. While this output Q is H, D-
Since the clock signal CK applied to the FF16 does not rise, the output Q8 of the D-FF16 continues to be L.

Therefore, the output signal of the AND circuit 17 is positive.

Next, when the signal Di becomes H from time tc to time t4, the output Q1 changes from time t to time t.

Until then, it becomes H. Therefore, the output Q dew is at time t.

It becomes H at the next time t4, and becomes L at time t.

Therefore, the signal Dh becomes H from time t4 when the re-outputs Q r and Q z become H at the same time to time t. In this way, the digital filter circuits 12, 13 transmit the signal D1 to the control circuit 7 only when the signal Dm continues for a time width of two cycles of the clock signal CI[. And 2
Noise with a time width shorter than the period is not transmitted to the control circuit 7. If the variable resistor 1 is adjusted here to change the period of the clock signal CM, the signal D! can be transmitted. You can also change the time range. In other words, by increasing the resistance value of the variable resistor l and lengthening the period of the clock signal CK, the time width of the command signal correction transmitted to the control circuit 7 becomes longer, and relatively long period noise can also be removed. In addition, by reducing the resistance value of the variable resistor 1 (by shortening the period of the clock signal GK), the time width of the command signal Di transmitted to the control circuit 7 can also be shortened, and the command signal Di can be taken in quickly. Of course, if the digital filter circuit changes the number of cascaded D-FFs, it is convenient when the command signal continues beyond the time width determined by the period of the clock signal CM corresponding to the number of D-FFs. This command signal is then transmitted to the control circuit 7.

Figure 4 is a block diagram showing an embodiment different from Figure 1.
The difference from the diagram is that the frequency divider circuit 14 is replaced by the oscillation circuit 3 and the counting circuit 4.
It is the connection between This embodiment is suitable for a long-time timer device in which the number of connected FF stages of the counting circuit 4 is large, and a part of the frequency dividing circuit 14 for the counting circuit 4 is normally used as the frequency dividing circuit for the digital filter circuit 12. This circuit is convenient for realizing Ic because it can be constructed with fewer elements.The operation of this circuit is similar to that shown in FIG. 1, so its explanation will be omitted.

〔Effect of the invention〕

According to the present invention, since both the start and reset command signals are input to the control circuit via the digital filter circuit whose clock signal source is the output of the time-limited oscillation circuit, Only the command signals with a predetermined signal width or more are transmitted to the control circuit, and noise shorter than this time width is not transmitted to the control circuit, so there is no need to use large filter circuits such as C and R, and it can be easily integrated into an IC. It has the effect of being able to be made smaller. In addition, by changing the period of the time limit oscillation circuit, the period of the clock signal of the digital filter circuit can be changed to obtain the optimal filter characteristics according to the set time limit of the timer device, and there is no need for a special oscillation circuit for the digital filter circuit. There is an effect that

[Brief explanation of the drawing]

1 to 3 show an embodiment of a timer device according to the present invention, FIG. 1 is a block diagram thereof, FIG. 2 is a wiring diagram showing an example of the configuration of a digital filter circuit, and FIG. 3 is a diagram illustrating a configuration example of a digital filter circuit. FIG. 4 is a block diagram showing an embodiment different from that in FIG. 1, and FIG. 5 is a block diagram showing an example of a conventional timer device. 3: Oscillation circuit, 4: Counting circuit, 7: Control circuit, 12,
ts: Digital filter circuit, 7-2, Figure 1 10 18 Figure 2 13

Claims (1)

[Claims] 1) An oscillation circuit that generates continuous pulses, a counting circuit that divides and counts the continuous pulses generated by this oscillation circuit, and a control circuit that receives both start and reset command signals and controls the counting circuit. In a timer device equipped with
A timer device characterized in that said start and reset command signals are inputted via a digital filter circuit whose clock signal source is the output of said oscillation circuit.