JPH03159310A - Timer - Google Patents

Abstract

PURPOSE:To reduce the readout of erroneous data by constituting a transfer pulse generation circuit with a read pulse/synchronous transfer pulse generating part and a clock synchronization transfer pulse generating part. CONSTITUTION:The transfer pulse generation circuit 2A is composed of the read pulse/synchronization transfer pulse generating part 7 and the clock synchronization transfer pulse generating part 8. When a read pulse is inputted while a clock is being changed from a high level to a low level, a transfer pulse by the clock synchronization transfer pulse generating part 8 is cancelled. At this time, the read pulse/synchronization transfer pulse generating part 7 generates the transfer pulse with prescribed pulse width at the fall of the read pulse, and data is transferred from a counter 1 to a register 4 with the transfer pulse TE. Thereby, it is possible to prevent erroneous data read out even when the read pulse is inputted with an arbitrary timing.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a timer with high data reading accuracy. [Prior Art] The configuration of a conventional example will be explained with reference to Fig. 4. Figure 4 is a circuit diagram showing a conventional timer. In FIG. 4, the conventional timer includes a counter (1) connected to clock generation means (not shown), a clock synchronous transfer pulse generation circuit (2) connected to clock generation means and read pulse generation means (not shown), A switch (3) connected to the counter (1) and the clock synchronous transfer pulse generation circuit (2), a read register (4) connected to this switch (3), this register (4), and a read pulse It consists of a switch (5) connected to the generating means and a data path (6) connected to this switch (5). Next, the operation of the conventional example described above is shown in FIGS. 5, 6, and 7.
This will be explained with reference to Fig. 8 and Fig. 8. 5 to 8 are signal waveform diagrams showing the operation of a conventional timer. FIG. 5 shows the operation of the timer when no read pulse (READ) is input. When a read pulse is not input, the clock synchronous transfer pulse generation circuit (2) outputs an inverted version of the clock (CLOCK) as a transfer pulse (TE). Figure 6 shows the operation of the timer when a read pulse is input while a transfer pulse is being output. The pulse width T1 of the read pulse is actually calculated from the counter (1) to the register (4).
> is sufficiently large compared to the time it takes to transfer data to
Data transfer is completed while the read pulse is being input, so erroneous data will not be read.

FIGS. 7 and 8 show the operation of the timer when the clock becomes low level "L" while inputting the read pulse. When the clock is reversed to "L゜", the transfer pulse normally rises and transfer starts, but as shown in Figure 7, the time T2 from the start of transfer to the fall of the read pulse is necessary for data transfer. If it is short compared to the time,
Due to data transfer, reading may end before the data in register (4) is finalized, resulting in incorrect data being read. Therefore, in reality, as shown in FIG. 8, if the clock falls during read pulse input, the transfer pulse of that cycle is canceled. [The problem that the invention tries to solve! ! ! ] In the conventional timer as described above, as shown in FIG. 9, the read pulse R is generated before the next transfer pulse (TE2) after the canceled transfer pulse (TE.
If 2 is input, data is not transferred from the counter (1) to the read register (4), so the read pulse R2 reads the count value at clock C1 instead of the count value at clock C2. There is a problem in that a read error occurs when the data is read out.

This invention has been made to solve the above-mentioned problems, and aims to provide a timer that will not read incorrect data even if a read pulse is input at an arbitrary timing. [Means for Solving the Problems] A timer according to the present invention includes the following means. (i>. First transfer pulse generation means that generates a first transfer pulse synchronized with a clock.

(ii>.Second transfer pulse generation means that generates a second transfer pulse synchronized with a read pulse for reading data from a register. [Operation] In this invention, the first transfer pulse generation means synchronizes with a clock The second transfer pulse is generated by the second transfer pulse generating means, which is synchronized with the read pulse for reading data from the register. The above-mentioned data is transferred from the counter to the above-mentioned register based on the transfer pulse of . [Embodiment] The horizontal command of the embodiment of this invention will be explained with reference to FIGS. 1 and 2. FIG. , is a circuit diagram showing an embodiment of the present invention, and the counter (1), switch <3> to data bus (6) are completely the same as those of the above-mentioned conventional example.

In FIG. 1, one embodiment of the present invention has a device that is exactly the same as the conventional example described above, and the input side is connected to clock generation means and read pulse generation means (not shown), and the output side is connected to a switch (3). It consists of a transfer pulse generation circuit (2^). Further, the transfer pulse generation circuit (2^>) includes a read pulse synchronous transfer pulse generation section (7) connected to a read pulse generation means (not shown), and a clock synchronous transfer pulse generation section (7) connected to the read pulse generation means and the clock generation means. It consists of a generating part (8). FIG. 2 is a circuit diagram showing a transfer pulse generation circuit according to an embodiment of the present invention. The transfer pulse generation circuit (2^) includes a read pulse synchronous transfer pulse generation section (7), a clock synchronous transfer pulse generation section (8), and these transfer pulse generation sections (7) and (8).
A NAND gate (21) connected to
It consists of an inverting circuit (22>) connected to a gate (21>).

Further, the read pulse synchronous transfer pulse generating section (7) includes an inverting circuit (not shown) connected to a read pulse generating means (not shown).
71>, an inverting circuit (72) also connected to the read pulse generating means, an inverting circuit (73) connected to the inverting circuit (71>), and a NAND connected to the inverting circuits (72) and (73>). The clock synchronous transfer pulse generating section (8) includes a transmission gate (81) connected to the read pulse generating means and the clock generating means, and a transmission gate (81) connected to the transmission gate (81). another transmission gate (82), an inverting circuit (83) connected to the transmission gate (81), and an input side connected to this inverting circuit (83).
83> and whose output side was connected to the transmission gate (82); one input side was connected to the transmission gate (81) and the other input side was connected to the clock generation means. NOR
It consists of a gate〈85). By the way, the first transfer pulse generating means of the present invention is the clock synchronous transfer pulse generating section (84) in the above-described embodiment of the present invention, and the second transfer pulse generating means is:
This is a read pulse synchronous transfer pulse generator. Next, the operation of the above embodiment will be explained with reference to FIG. FIG. 3 is a signal waveform diagram showing the operation of an embodiment of the present invention. If a read pulse is not input, a transfer pulse (with an inverted clock) is generated from the clock synchronous transfer pulse generator (8).
TE2) is generated. When a read pulse is input from the high level "H" of the clock to the low level "L", the latch circuit consisting of transmission gates (8l) and (82) and inverting circuits (83) and (84) causes the clock to go "H". is latched and the transfer pulse (TEA) is canceled due to the clock inversion of the cycle in which the read pulse was input.From the fall of the read pulse, the inversion circuit (
A read pulse synchronized transfer pulse generator (7) generates a transfer pulse (TE,) having a pulse width determined by the delay times of (71), (72), and (73). Above 2
A transfer pulse (TE) is created by ANDing the types of transfer pulses. This transfer pulse transfers data from the counter (1) to the register (4). In one embodiment of the present invention, even if the clock-synchronized transfer pulse is canceled by the read pulse, the counter (1) is reset by the transfer pulse synchronized with the read pulse.
Since the data is transferred from the register (4) to the read register (4), the data of each clock cycle is transferred to the register (4).
), which has the effect of eliminating data read errors. In addition, in the above embodiment, an example was shown in which a transfer pulse (TE.) synchronized with the read pulse is generated for all input read pulses, but the transfer pulse (TE.) synchronized with the clock is canceled. It goes without saying that the intended purpose can also be achieved by generating a transfer pulse (TE) in synchronization with the read pulse only in the case where the read pulse is synchronized. [Effects of the Invention] As described above, the present invention includes a first transfer pulse generating means for generating a first transfer pulse synchronized with a clock, and a second transfer pulse synchronized with a read pulse for reading data from a register. and a second transfer pulse generating means for generating a second transfer pulse, so that when the data is transferred from the counter to the register based on the first and second transfer pulses, a read pulse can be input at any timing. This has the effect that incorrect data will not be read even when the data is read out.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a transfer pulse generation circuit of an embodiment of the invention,
FIG. 3 is a signal waveform diagram showing the operation of an embodiment of the present invention;
Figure 4 is a circuit diagram showing a conventional timer, Figures 5 and 6,
7, 8, and 9 are signal waveform diagrams showing the operation of a conventional timer. In the figure, (1)... Counter, (2^)... Transfer pulse generation circuit, (3)...
・Switch, (4) (5) <6) (7) (8) In addition, is shown. Registers, switches, data paths, read pulse synchronous transfer pulse generator Clock synchronous transfer pulse generator In each figure, the same symbols indicate the same or equivalent parts.

Claims (1)

[Claims] A first transfer pulse generation means for generating a first transfer pulse synchronized with a clock; and a second transfer pulse generation means for generating a second transfer pulse synchronized with a read pulse for reading data from a register; A timer characterized in that the data is transferred from the counter to the register based on first and second transfer pulses.