JPH01100700A - Measuring device - Google Patents

Abstract

PURPOSE:To prevent an erroneous recognition by recognizing a reading state, delaying a data fetch time during a reading, thereby, eliminating the change of the value of a measuring register during the reading. CONSTITUTION:When a fetches signal CAP from the counter 1 of a pulse duration measuring type timer is inputted, the signal CAP passes through a path 8 in a fetch signal control circuit 3 and is outputted as a fetch permitting signal (a) from an OR circuit 10. Thereby, the count value of the counter 1 is fetched to the measuring register 2. Then, when the signal CAP is inputted during the reading by a signal RD, the signal CAP enters a one cycle delay circuit 4, is delayed until the reading operation is completed and outputted as the delayed fetch permitting signal (a). Thereby, the value of the measuring register is not changed during the reading operation to stably execute the reading operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a measuring device, and particularly to a data acquisition method thereof.

[Conventional technology]

FIG. 2 is a system diagram showing a measuring device section of a conventional pulse width measuring timer, in which 1 is a counter, and 2 is a measurement register that stores the value of the counter 1 using a capture signal CAP.

FIG. 3 is a time chart for explaining the operation of a conventional device and a device according to the present invention, in which (a) is a count pulse, (b) is a count value, and (C) is a capture signal CAP.
, (d) is the capture permission signal a% which will be explained in the example below.
(61 indicates a read signal RD, (fl indicates a measurement register value, period T1 in FIG. 3 corresponds to the operation of the conventional device, and period T2 corresponds to the operation of the device according to the present invention.

Next, the operation of the apparatus shown in FIG. 2 will be explained using FIG. 3. The value of the counter 1 at that time is taken into the measurement register 2 by the take-in signal CAP generated at the rising or falling edge of the pulse. This value is read out to the outside by a read signal RD. As shown in FIG. 3 (C1, (dl), in the conventional device, the capture signal CAP directly becomes the capture permission signal a.

Although the series of operations is as described above, the counter 1 continues counting even after the acquisition signal CAP is input, and prepares for the next measurement (input of the acquisition signal CAP).

[Problem that the invention seeks to solve]

The measurement device section of the conventional pulse width measurement timer is configured as described above, and when the capture signal CAP is input during the read operation, the value of the measurement register 2 changes. If there is little time available at this time, the changing value is read out,
There was a problem of misrecognition.

The present invention has been made in view of these points, and its purpose is to provide a measurement system that can eliminate changes in the value of a measurement register during reading and also stabilize the data being read. It's about getting the equipment.

[Means for solving problems]

In order to achieve such an object, the present invention is provided with a recognition means for recognizing the read state and a delay circuit that delays the timing of data acquisition when it is recognized that reading is in progress.

[Effect]

In the measuring device according to the present invention, measured values are read out stably, and there is no misrecognition.

〔Example〕

FIG. 1 is a system diagram showing one embodiment of a measuring device according to the present invention. In FIG. 1, 1 is a counter, 2 is a measurement register that stores the value of counter 1, 3 is an acquisition signal control circuit, 4 is an l-cycle delay circuit, 5 is an inverter, and 6 is an inverter.
．． 7 is an AND circuit, 8.9 is a path, and 10 is an OR circuit, and the inverter 5 and AND circuits 6 and 7 constitute recognition means.

Furthermore, all the circuits in FIG. 1 are described as circuits that operate using the rHJ level signal as a significant signal.

The operation will be explained below using FIG. 3.

First, count value acquisition when no read operation is being performed will be described (see period T1 in FIG. 3). 1st
Since all of the circuits in the figure operate using the rHJ level signal as a significant signal, the read signal RD is at the rLJ level when no read operation is being performed. Therefore, when the capture signal CAP is input, the signal CAP passes through the path 8 in the capture signal control circuit 3 and is output from the OR circuit IO as the capture permission signal a.

As a result, the count value of counter 1 is changed to measurement register 2.
be taken in.

Next, a case will be described in which the capture signal CAP is input during the read operation (see period T2 in FIG. 3). In this case, read signal RD is at rHJ level. Therefore,
The input capture signal CAP enters the l-cycle delay circuit 4 and is delayed until one cycle after the completion of the read operation.
The signal is output from the OR circuit 10 via the path 9 as a capture permission signal a. That is, the capture signal CAP during a read operation is delayed by one cycle, and this delayed capture signal C
The count value of the counter 1 is loaded into the measurement register 2 by the loading permission signal a which is AP.

Since the operation is as described above, the value of the measurement register 2 does not change during the read operation, and the read operation can be performed stably.

In the above embodiment, the delay amount is fixed at one cycle, but if the read operation does not end within a certain period, the completion of the read operation is determined by taking the read signal RD into the delay circuit 4, and the take-in signal is It is also possible to output the CAP.

It is also possible to include all the circuits according to the present invention in one semiconductor integrated circuit.

〔Effect of the invention〕

As explained above, the present invention recognizes the read state and delays the data capture timing when it is recognized that the read is in progress, so that the value of the measurement register does not change during the read operation, so the measurement This has the effect of not only being able to stably read out the value, but also eliminating erroneous recognition and improving the stability of the device.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing an embodiment of a measuring device according to the present invention, FIG. 2 is a time chart for explaining the operation of the device, and FIG. 3 is a system diagram showing a conventional device. DESCRIPTION OF SYMBOLS 1... Counter, 2... Measurement register, 3... Capture signal control circuit, 4... l cycle delay circuit, 5...
...Inverter, 6.7...AND circuit, 8.9...
・Route, 10...OR circuit.

Claims (1)

[Claims] A measuring device comprising: recognition means for recognizing a read state; and a delay circuit for delaying data acquisition when recognizing that reading is in progress.