JPH01223675A - Seek control circuit - Google Patents

Abstract

PURPOSE:To more quickly execute seek to a target track by providing a window control circuit and executing the elimination of an unnecessary track count signal and insertion against the omission of a track count signal. CONSTITUTION:A tracking error 1 is binarized by a comparator 2, and thereafter, for instance, leading edge is detected by a detecting circuit 3 and a track count signal 14 is outputted. On the other hand, in an initial state, a window control circuit 9 outputs continuously a window gate pulse 10 in a state of '1'. When the signal 14 is inputted to an AND gate 4, an output signal from the gate 4 passes through an OR gate 5 and inputted to a counter 6 as a reset signal, and also, inputted to a counter 8 as a count signal 15. By the counter 6, a register 7 and the circuit 9, the elimination of an unnecessary signal of a track count signal, and insertion for an omission are executed, and normal count can be executed by a counter 8. In such a way, the seek to a target track can be executed quickly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a seek control circuit, and more particularly to a tracking counter for an optical disk device.

[Conventional technology]

Conventionally, this type of tracking counter has a comparator 2 that binarizes a tracking error signal and a counter 8 that counts the rise or fall of the output of this comparator, as shown in FIG. Error 1 is binarized by a comparator 2, and counted by a counter 8 through a detection circuit 3 that detects the rise or fall of the signal.

[Problem to be solved by the invention]

The conventional tracking counter described above counts the number of passed tracks based on the tracking error.
When seeking to the desired track, if the disk passes through a part of the mirror that has no scratches or groups (grooves), a miscount will occur, resulting in an error of several to dozens of tracks. The disadvantage was that it required a jump.

〔the purpose〕

An object of the present invention is to provide a tracking counter capable of removing unnecessary track signals and protecting against missing track signals, in contrast to the conventional tracking counter described above.

[Means to solve the problem]

The tracking counter of the present invention includes a comparator that binarizes a tracking error signal, a detection circuit that detects the rise or fall of the output from this comparator, and a counter that measures the time it takes to pass one track. and a register that holds the passing time of the previous track, and the output of that register as the expected value.A window gate pulse is generated based on the output of the measurement counter at a time centered on this expected value, and that pulse is A window control circuit that generates a pseudo track count signal when a track count signal does not arrive within the valid period of the window gate pulse, and a window control circuit that only makes valid the track count signal that has arrived during the valid period of the window gate pulse, and controls other counts. It has an AND gate that invalidates a signal, an OR gate that inputs the signal from the AND gate and a pseudo track count signal, and a counter that measures the signal from the OR gate.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. After the tracking error 1 is binarized by the comparator 2, the rising or falling edge is detected by the detection circuit 3 and the pulse corresponding to the track (hereinafter referred to as track error) is detected.
A count signal (referred to as a count signal) 14 serves as one input of the AND gate 4. The output of AND gate 4 becomes one input of OR gate 5, and its output 15 is input to counter 6 and counter 8 as a reset signal. A reference clock 12 is also input to the counter 6 for measuring the interval of track count signals. The interval of the track count signal measured by the counter 6 is loaded into a register 7, and according to the contents of this register 7, a window gate pulse 10 is outputted from the window control circuit 9 to the other input of the AND gate 4. Ru. On the other hand, from the window control circuit 9, the OR gate 5
A pseudo track count signal 11 is output to the other input of the .

Next, the operation of the present invention will be explained with reference to the timing chart of FIG.

Tracking error 1 is determined by comparator 2.
After being binarized as shown in FIG. 3, the detection circuit 3 detects, for example, the rising edge of the track count signal 1.
4 is output. This track count signal 14 is A
It becomes one input of the ND gate 4. On the other hand, in the initial state, the window control circuit 9 continues to output the window gate pulse 10 in the state of 1'' and waits for the input of the track count signal 14 which is input to one side of the AND gate 4. When the signal 14 is input, the output signal from the AND gate 4 is inputted to the counter 6 as a reset signal through the OR gate 5, and also inputted to the counter 8 as a count signal 15. The interval of the count signal is loaded in the register 7, and the window control circuit 9 uses the contents of the register 7 as an expected value and shifts to the normal operation of generating the window gate pulse 10 only for several clocks before and after this. , the track count signal 14 from the detection circuit 3 is the only signal outputted while the window gate pulse is outputted to the AND gate 4.
The output is

Now, considering the case where the tracking error 1 approaches the damaged location 16, the tracking error at the damaged location 16 is binarized by the comparator 2, the rising edge is detected by the detection circuit 3, and then the AND gate 4 This is one input. At this time, only the track count signal 14 when the window gate pulse 10 is input to the other input becomes valid, and a normal count signal 15 is obtained.

Next, considering the case where the tracking error 1 approaches the mirror part 17, since the track count signal 14 is not output in the mirror part 17, the AND gate 4
No signal is output from. If the count signal 15 is not detected, the window control circuit 9 outputs a pseudo track count signal 11 in accordance with the falling edge of the window gate pulse by the counter 6, and a signal is output from the OR gate 5, allowing normal counting. A signal 15 is obtained.

In this manner, the counter 6, the register 7, and the window control circuit remove unnecessary signals from the track count signal and insert missing signals, thereby allowing the counter 8 to count the normal count signal 15.

〔Effect of the invention〕

As described above, in the present invention, by providing a window control circuit, unnecessary track count signals can be removed and track count signals can be inserted in case of omissions, so that more accurate track counting can be performed. This has the effect that it is possible to seek to the target track more quickly because jumps due to errors after the seek operation are reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart of the embodiment shown in FIG. 1, and FIG. 3 is a block diagram of a conventional tracking counter. l...Tracking error, 2...
Comparator, 3... Voltage detection circuit, 4...
・Logic AND gate, 5...Logic OR gate, 6...
...Counter, 7...Register, Death...
...Counter, 9...Window control circuit, 1
0...Window gate pulse, 11-0
．． ...Pseudo track count signal, 12...
Standard clock (reference clock), 13...
...Binarized tracking error signal, 14...
...Track count signal, 15...Count signal, 16...Damaged area, 17...
Part of Mira. Agent Patent Attorney Uchi Hara Oto 1-1-\ 'O \ W\ ,',-t Ji\ Bet- \ To 11 90-

Claims (1)

[Claims] a comparator that binarizes a track signal; a detection circuit that detects the output from the comparator; a first counter that measures the time it takes for the track signal to pass through one track; and a first counter that measures the time it takes for the track signal to pass through one track. A register that holds time; an output from the register is set as an expected value; a window gate pulse is generated based on the output from the first counter at a time centering on the expected value; - A window control circuit that generates a pseudo track count signal when the counter signal is not output from the counter within the valid period of the gate pulse, and a window control circuit that generates a pseudo track count signal from the detection circuit that is input during the valid period of the window gate pulse. an AND gate that makes only the detection signal valid, an OR gate that receives the output from the AND gate and the pseudo track count signal as input, and a second counter that measures the output signal from the OR gate. A seek control circuit comprising: